1 /* 2 * Component description for OSC32KCTRL 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_OSC32KCTRL_COMPONENT_H_ 22 #define _PIC32CXSG41_OSC32KCTRL_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR OSC32KCTRL */ 26 /* ************************************************************************** */ 27 28 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 29 #define OSC32KCTRL_INTENCLR_RESETVALUE _UINT32_(0x00) /* (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Reset Value */ 30 31 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos _UINT32_(0) /* (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */ 32 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk (_UINT32_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */ 33 #define OSC32KCTRL_INTENCLR_XOSC32KRDY(value) (OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTENCLR register */ 34 #define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos _UINT32_(2) /* (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */ 35 #define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk (_UINT32_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */ 36 #define OSC32KCTRL_INTENCLR_XOSC32KFAIL(value) (OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTENCLR register */ 37 #define OSC32KCTRL_INTENCLR_Msk _UINT32_(0x00000005) /* (OSC32KCTRL_INTENCLR) Register Mask */ 38 39 40 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 41 #define OSC32KCTRL_INTENSET_RESETVALUE _UINT32_(0x00) /* (OSC32KCTRL_INTENSET) Interrupt Enable Set Reset Value */ 42 43 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos _UINT32_(0) /* (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */ 44 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk (_UINT32_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */ 45 #define OSC32KCTRL_INTENSET_XOSC32KRDY(value) (OSC32KCTRL_INTENSET_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTENSET register */ 46 #define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos _UINT32_(2) /* (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */ 47 #define OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk (_UINT32_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */ 48 #define OSC32KCTRL_INTENSET_XOSC32KFAIL(value) (OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTENSET register */ 49 #define OSC32KCTRL_INTENSET_Msk _UINT32_(0x00000005) /* (OSC32KCTRL_INTENSET) Register Mask */ 50 51 52 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 53 #define OSC32KCTRL_INTFLAG_RESETVALUE _UINT32_(0x00) /* (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 54 55 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos _UINT32_(0) /* (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */ 56 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk (_UINT32_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) /* (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */ 57 #define OSC32KCTRL_INTFLAG_XOSC32KRDY(value) (OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_INTFLAG register */ 58 #define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos _UINT32_(2) /* (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */ 59 #define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk (_UINT32_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos) /* (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */ 60 #define OSC32KCTRL_INTFLAG_XOSC32KFAIL(value) (OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_INTFLAG register */ 61 #define OSC32KCTRL_INTFLAG_Msk _UINT32_(0x00000005) /* (OSC32KCTRL_INTFLAG) Register Mask */ 62 63 64 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */ 65 #define OSC32KCTRL_STATUS_RESETVALUE _UINT32_(0x00) /* (OSC32KCTRL_STATUS) Power and Clocks Status Reset Value */ 66 67 #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos _UINT32_(0) /* (OSC32KCTRL_STATUS) XOSC32K Ready Position */ 68 #define OSC32KCTRL_STATUS_XOSC32KRDY_Msk (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) /* (OSC32KCTRL_STATUS) XOSC32K Ready Mask */ 69 #define OSC32KCTRL_STATUS_XOSC32KRDY(value) (OSC32KCTRL_STATUS_XOSC32KRDY_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)) /* Assignment of value for XOSC32KRDY in the OSC32KCTRL_STATUS register */ 70 #define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos _UINT32_(2) /* (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */ 71 #define OSC32KCTRL_STATUS_XOSC32KFAIL_Msk (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos) /* (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */ 72 #define OSC32KCTRL_STATUS_XOSC32KFAIL(value) (OSC32KCTRL_STATUS_XOSC32KFAIL_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)) /* Assignment of value for XOSC32KFAIL in the OSC32KCTRL_STATUS register */ 73 #define OSC32KCTRL_STATUS_XOSC32KSW_Pos _UINT32_(3) /* (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */ 74 #define OSC32KCTRL_STATUS_XOSC32KSW_Msk (_UINT32_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos) /* (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */ 75 #define OSC32KCTRL_STATUS_XOSC32KSW(value) (OSC32KCTRL_STATUS_XOSC32KSW_Msk & (_UINT32_(value) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)) /* Assignment of value for XOSC32KSW in the OSC32KCTRL_STATUS register */ 76 #define OSC32KCTRL_STATUS_Msk _UINT32_(0x0000000D) /* (OSC32KCTRL_STATUS) Register Mask */ 77 78 79 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */ 80 #define OSC32KCTRL_RTCCTRL_RESETVALUE _UINT8_(0x00) /* (OSC32KCTRL_RTCCTRL) RTC Clock Selection Reset Value */ 81 82 #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos _UINT8_(0) /* (OSC32KCTRL_RTCCTRL) RTC Clock Selection Position */ 83 #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_UINT8_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /* (OSC32KCTRL_RTCCTRL) RTC Clock Selection Mask */ 84 #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & (_UINT8_(value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)) /* Assignment of value for RTCSEL in the OSC32KCTRL_RTCCTRL register */ 85 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _UINT8_(0x0) /* (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ 86 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _UINT8_(0x1) /* (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ 87 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _UINT8_(0x4) /* (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 88 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _UINT8_(0x5) /* (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ 89 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /* (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator Position */ 90 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /* (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator Position */ 91 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /* (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position */ 92 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /* (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position */ 93 #define OSC32KCTRL_RTCCTRL_Msk _UINT8_(0x07) /* (OSC32KCTRL_RTCCTRL) Register Mask */ 94 95 96 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ 97 #define OSC32KCTRL_XOSC32K_RESETVALUE _UINT16_(0x2080) /* (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Reset Value */ 98 99 #define OSC32KCTRL_XOSC32K_ENABLE_Pos _UINT16_(1) /* (OSC32KCTRL_XOSC32K) Oscillator Enable Position */ 100 #define OSC32KCTRL_XOSC32K_ENABLE_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) /* (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */ 101 #define OSC32KCTRL_XOSC32K_ENABLE(value) (OSC32KCTRL_XOSC32K_ENABLE_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_ENABLE_Pos)) /* Assignment of value for ENABLE in the OSC32KCTRL_XOSC32K register */ 102 #define OSC32KCTRL_XOSC32K_XTALEN_Pos _UINT16_(2) /* (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */ 103 #define OSC32KCTRL_XOSC32K_XTALEN_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) /* (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */ 104 #define OSC32KCTRL_XOSC32K_XTALEN(value) (OSC32KCTRL_XOSC32K_XTALEN_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_XTALEN_Pos)) /* Assignment of value for XTALEN in the OSC32KCTRL_XOSC32K register */ 105 #define OSC32KCTRL_XOSC32K_EN32K_Pos _UINT16_(3) /* (OSC32KCTRL_XOSC32K) 32kHz Output Enable Position */ 106 #define OSC32KCTRL_XOSC32K_EN32K_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) /* (OSC32KCTRL_XOSC32K) 32kHz Output Enable Mask */ 107 #define OSC32KCTRL_XOSC32K_EN32K(value) (OSC32KCTRL_XOSC32K_EN32K_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_EN32K_Pos)) /* Assignment of value for EN32K in the OSC32KCTRL_XOSC32K register */ 108 #define OSC32KCTRL_XOSC32K_EN1K_Pos _UINT16_(4) /* (OSC32KCTRL_XOSC32K) 1kHz Output Enable Position */ 109 #define OSC32KCTRL_XOSC32K_EN1K_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) /* (OSC32KCTRL_XOSC32K) 1kHz Output Enable Mask */ 110 #define OSC32KCTRL_XOSC32K_EN1K(value) (OSC32KCTRL_XOSC32K_EN1K_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_EN1K_Pos)) /* Assignment of value for EN1K in the OSC32KCTRL_XOSC32K register */ 111 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos _UINT16_(6) /* (OSC32KCTRL_XOSC32K) Run in Standby Position */ 112 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) /* (OSC32KCTRL_XOSC32K) Run in Standby Mask */ 113 #define OSC32KCTRL_XOSC32K_RUNSTDBY(value) (OSC32KCTRL_XOSC32K_RUNSTDBY_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the OSC32KCTRL_XOSC32K register */ 114 #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos _UINT16_(7) /* (OSC32KCTRL_XOSC32K) On Demand Control Position */ 115 #define OSC32KCTRL_XOSC32K_ONDEMAND_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) /* (OSC32KCTRL_XOSC32K) On Demand Control Mask */ 116 #define OSC32KCTRL_XOSC32K_ONDEMAND(value) (OSC32KCTRL_XOSC32K_ONDEMAND_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the OSC32KCTRL_XOSC32K register */ 117 #define OSC32KCTRL_XOSC32K_STARTUP_Pos _UINT16_(8) /* (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Position */ 118 #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_UINT16_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Mask */ 119 #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) /* Assignment of value for STARTUP in the OSC32KCTRL_XOSC32K register */ 120 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val _UINT16_(0x0) /* (OSC32KCTRL_XOSC32K) 62.6 ms */ 121 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val _UINT16_(0x1) /* (OSC32KCTRL_XOSC32K) 125 ms */ 122 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val _UINT16_(0x2) /* (OSC32KCTRL_XOSC32K) 500 ms */ 123 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val _UINT16_(0x3) /* (OSC32KCTRL_XOSC32K) 1000 ms */ 124 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val _UINT16_(0x4) /* (OSC32KCTRL_XOSC32K) 2000 ms */ 125 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val _UINT16_(0x5) /* (OSC32KCTRL_XOSC32K) 4000 ms */ 126 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val _UINT16_(0x6) /* (OSC32KCTRL_XOSC32K) 8000 ms */ 127 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 62.6 ms Position */ 128 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 125 ms Position */ 129 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 500 ms Position */ 130 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 1000 ms Position */ 131 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 2000 ms Position */ 132 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 4000 ms Position */ 133 #define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /* (OSC32KCTRL_XOSC32K) 8000 ms Position */ 134 #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos _UINT16_(12) /* (OSC32KCTRL_XOSC32K) Write Lock Position */ 135 #define OSC32KCTRL_XOSC32K_WRTLOCK_Msk (_UINT16_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) /* (OSC32KCTRL_XOSC32K) Write Lock Mask */ 136 #define OSC32KCTRL_XOSC32K_WRTLOCK(value) (OSC32KCTRL_XOSC32K_WRTLOCK_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSC32KCTRL_XOSC32K register */ 137 #define OSC32KCTRL_XOSC32K_CGM_Pos _UINT16_(13) /* (OSC32KCTRL_XOSC32K) Control Gain Mode Position */ 138 #define OSC32KCTRL_XOSC32K_CGM_Msk (_UINT16_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) Control Gain Mode Mask */ 139 #define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & (_UINT16_(value) << OSC32KCTRL_XOSC32K_CGM_Pos)) /* Assignment of value for CGM in the OSC32KCTRL_XOSC32K register */ 140 #define OSC32KCTRL_XOSC32K_CGM_XT_Val _UINT16_(0x1) /* (OSC32KCTRL_XOSC32K) Standard mode */ 141 #define OSC32KCTRL_XOSC32K_CGM_HS_Val _UINT16_(0x2) /* (OSC32KCTRL_XOSC32K) High Speed mode */ 142 #define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) Standard mode Position */ 143 #define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /* (OSC32KCTRL_XOSC32K) High Speed mode Position */ 144 #define OSC32KCTRL_XOSC32K_Msk _UINT16_(0x77DE) /* (OSC32KCTRL_XOSC32K) Register Mask */ 145 146 147 /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */ 148 #define OSC32KCTRL_CFDCTRL_RESETVALUE _UINT8_(0x00) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Reset Value */ 149 150 #define OSC32KCTRL_CFDCTRL_CFDEN_Pos _UINT8_(0) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */ 151 #define OSC32KCTRL_CFDCTRL_CFDEN_Msk (_UINT8_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */ 152 #define OSC32KCTRL_CFDCTRL_CFDEN(value) (OSC32KCTRL_CFDCTRL_CFDEN_Msk & (_UINT8_(value) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)) /* Assignment of value for CFDEN in the OSC32KCTRL_CFDCTRL register */ 153 #define OSC32KCTRL_CFDCTRL_SWBACK_Pos _UINT8_(1) /* (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */ 154 #define OSC32KCTRL_CFDCTRL_SWBACK_Msk (_UINT8_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos) /* (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */ 155 #define OSC32KCTRL_CFDCTRL_SWBACK(value) (OSC32KCTRL_CFDCTRL_SWBACK_Msk & (_UINT8_(value) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)) /* Assignment of value for SWBACK in the OSC32KCTRL_CFDCTRL register */ 156 #define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos _UINT8_(2) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */ 157 #define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk (_UINT8_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */ 158 #define OSC32KCTRL_CFDCTRL_CFDPRESC(value) (OSC32KCTRL_CFDCTRL_CFDPRESC_Msk & (_UINT8_(value) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)) /* Assignment of value for CFDPRESC in the OSC32KCTRL_CFDCTRL register */ 159 #define OSC32KCTRL_CFDCTRL_Msk _UINT8_(0x07) /* (OSC32KCTRL_CFDCTRL) Register Mask */ 160 161 162 /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */ 163 #define OSC32KCTRL_EVCTRL_RESETVALUE _UINT8_(0x00) /* (OSC32KCTRL_EVCTRL) Event Control Reset Value */ 164 165 #define OSC32KCTRL_EVCTRL_CFDEO_Pos _UINT8_(0) /* (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */ 166 #define OSC32KCTRL_EVCTRL_CFDEO_Msk (_UINT8_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos) /* (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */ 167 #define OSC32KCTRL_EVCTRL_CFDEO(value) (OSC32KCTRL_EVCTRL_CFDEO_Msk & (_UINT8_(value) << OSC32KCTRL_EVCTRL_CFDEO_Pos)) /* Assignment of value for CFDEO in the OSC32KCTRL_EVCTRL register */ 168 #define OSC32KCTRL_EVCTRL_Msk _UINT8_(0x01) /* (OSC32KCTRL_EVCTRL) Register Mask */ 169 170 171 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ 172 #define OSC32KCTRL_OSCULP32K_RESETVALUE _UINT32_(0x00) /* (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Reset Value */ 173 174 #define OSC32KCTRL_OSCULP32K_EN32K_Pos _UINT32_(1) /* (OSC32KCTRL_OSCULP32K) Enable Out 32k Position */ 175 #define OSC32KCTRL_OSCULP32K_EN32K_Msk (_UINT32_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos) /* (OSC32KCTRL_OSCULP32K) Enable Out 32k Mask */ 176 #define OSC32KCTRL_OSCULP32K_EN32K(value) (OSC32KCTRL_OSCULP32K_EN32K_Msk & (_UINT32_(value) << OSC32KCTRL_OSCULP32K_EN32K_Pos)) /* Assignment of value for EN32K in the OSC32KCTRL_OSCULP32K register */ 177 #define OSC32KCTRL_OSCULP32K_EN1K_Pos _UINT32_(2) /* (OSC32KCTRL_OSCULP32K) Enable Out 1k Position */ 178 #define OSC32KCTRL_OSCULP32K_EN1K_Msk (_UINT32_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos) /* (OSC32KCTRL_OSCULP32K) Enable Out 1k Mask */ 179 #define OSC32KCTRL_OSCULP32K_EN1K(value) (OSC32KCTRL_OSCULP32K_EN1K_Msk & (_UINT32_(value) << OSC32KCTRL_OSCULP32K_EN1K_Pos)) /* Assignment of value for EN1K in the OSC32KCTRL_OSCULP32K register */ 180 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos _UINT32_(15) /* (OSC32KCTRL_OSCULP32K) Write Lock Position */ 181 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Msk (_UINT32_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) /* (OSC32KCTRL_OSCULP32K) Write Lock Mask */ 182 #define OSC32KCTRL_OSCULP32K_WRTLOCK(value) (OSC32KCTRL_OSCULP32K_WRTLOCK_Msk & (_UINT32_(value) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)) /* Assignment of value for WRTLOCK in the OSC32KCTRL_OSCULP32K register */ 183 #define OSC32KCTRL_OSCULP32K_Msk _UINT32_(0x00008006) /* (OSC32KCTRL_OSCULP32K) Register Mask */ 184 185 186 /* OSC32KCTRL register offsets definitions */ 187 #define OSC32KCTRL_INTENCLR_REG_OFST _UINT32_(0x00) /* (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Offset */ 188 #define OSC32KCTRL_INTENSET_REG_OFST _UINT32_(0x04) /* (OSC32KCTRL_INTENSET) Interrupt Enable Set Offset */ 189 #define OSC32KCTRL_INTFLAG_REG_OFST _UINT32_(0x08) /* (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */ 190 #define OSC32KCTRL_STATUS_REG_OFST _UINT32_(0x0C) /* (OSC32KCTRL_STATUS) Power and Clocks Status Offset */ 191 #define OSC32KCTRL_RTCCTRL_REG_OFST _UINT32_(0x10) /* (OSC32KCTRL_RTCCTRL) RTC Clock Selection Offset */ 192 #define OSC32KCTRL_XOSC32K_REG_OFST _UINT32_(0x14) /* (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Offset */ 193 #define OSC32KCTRL_CFDCTRL_REG_OFST _UINT32_(0x16) /* (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Offset */ 194 #define OSC32KCTRL_EVCTRL_REG_OFST _UINT32_(0x17) /* (OSC32KCTRL_EVCTRL) Event Control Offset */ 195 #define OSC32KCTRL_OSCULP32K_REG_OFST _UINT32_(0x1C) /* (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Offset */ 196 197 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 198 /* OSC32KCTRL register API structure */ 199 typedef struct 200 { /* 32kHz Oscillators Control */ 201 __IO uint32_t OSC32KCTRL_INTENCLR; /* Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 202 __IO uint32_t OSC32KCTRL_INTENSET; /* Offset: 0x04 (R/W 32) Interrupt Enable Set */ 203 __IO uint32_t OSC32KCTRL_INTFLAG; /* Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 204 __I uint32_t OSC32KCTRL_STATUS; /* Offset: 0x0C (R/ 32) Power and Clocks Status */ 205 __IO uint8_t OSC32KCTRL_RTCCTRL; /* Offset: 0x10 (R/W 8) RTC Clock Selection */ 206 __I uint8_t Reserved1[0x03]; 207 __IO uint16_t OSC32KCTRL_XOSC32K; /* Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ 208 __IO uint8_t OSC32KCTRL_CFDCTRL; /* Offset: 0x16 (R/W 8) Clock Failure Detector Control */ 209 __IO uint8_t OSC32KCTRL_EVCTRL; /* Offset: 0x17 (R/W 8) Event Control */ 210 __I uint8_t Reserved2[0x04]; 211 __IO uint32_t OSC32KCTRL_OSCULP32K; /* Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 212 } osc32kctrl_registers_t; 213 214 215 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 #endif /* _PIC32CXSG41_OSC32KCTRL_COMPONENT_H_ */ 217
