1 /* 2 * Component description for NVMCTRL 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_NVMCTRL_COMPONENT_H_ 22 #define _PIC32CXSG41_NVMCTRL_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR NVMCTRL */ 26 /* ************************************************************************** */ 27 28 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 29 #define NVMCTRL_CTRLA_RESETVALUE _UINT16_(0x04) /* (NVMCTRL_CTRLA) Control A Reset Value */ 30 31 #define NVMCTRL_CTRLA_AUTOWS_Pos _UINT16_(2) /* (NVMCTRL_CTRLA) Auto Wait State Enable Position */ 32 #define NVMCTRL_CTRLA_AUTOWS_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos) /* (NVMCTRL_CTRLA) Auto Wait State Enable Mask */ 33 #define NVMCTRL_CTRLA_AUTOWS(value) (NVMCTRL_CTRLA_AUTOWS_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_AUTOWS_Pos)) /* Assignment of value for AUTOWS in the NVMCTRL_CTRLA register */ 34 #define NVMCTRL_CTRLA_SUSPEN_Pos _UINT16_(3) /* (NVMCTRL_CTRLA) Suspend Enable Position */ 35 #define NVMCTRL_CTRLA_SUSPEN_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos) /* (NVMCTRL_CTRLA) Suspend Enable Mask */ 36 #define NVMCTRL_CTRLA_SUSPEN(value) (NVMCTRL_CTRLA_SUSPEN_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_SUSPEN_Pos)) /* Assignment of value for SUSPEN in the NVMCTRL_CTRLA register */ 37 #define NVMCTRL_CTRLA_WMODE_Pos _UINT16_(4) /* (NVMCTRL_CTRLA) Write Mode Position */ 38 #define NVMCTRL_CTRLA_WMODE_Msk (_UINT16_(0x3) << NVMCTRL_CTRLA_WMODE_Pos) /* (NVMCTRL_CTRLA) Write Mode Mask */ 39 #define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_WMODE_Pos)) /* Assignment of value for WMODE in the NVMCTRL_CTRLA register */ 40 #define NVMCTRL_CTRLA_WMODE_MAN_Val _UINT16_(0x0) /* (NVMCTRL_CTRLA) Manual Write */ 41 #define NVMCTRL_CTRLA_WMODE_ADW_Val _UINT16_(0x1) /* (NVMCTRL_CTRLA) Automatic Double Word Write */ 42 #define NVMCTRL_CTRLA_WMODE_AQW_Val _UINT16_(0x2) /* (NVMCTRL_CTRLA) Automatic Quad Word */ 43 #define NVMCTRL_CTRLA_WMODE_AP_Val _UINT16_(0x3) /* (NVMCTRL_CTRLA) Automatic Page Write */ 44 #define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos) /* (NVMCTRL_CTRLA) Manual Write Position */ 45 #define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos) /* (NVMCTRL_CTRLA) Automatic Double Word Write Position */ 46 #define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos) /* (NVMCTRL_CTRLA) Automatic Quad Word Position */ 47 #define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos) /* (NVMCTRL_CTRLA) Automatic Page Write Position */ 48 #define NVMCTRL_CTRLA_PRM_Pos _UINT16_(6) /* (NVMCTRL_CTRLA) Power Reduction Mode during Sleep Position */ 49 #define NVMCTRL_CTRLA_PRM_Msk (_UINT16_(0x3) << NVMCTRL_CTRLA_PRM_Pos) /* (NVMCTRL_CTRLA) Power Reduction Mode during Sleep Mask */ 50 #define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_PRM_Pos)) /* Assignment of value for PRM in the NVMCTRL_CTRLA register */ 51 #define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _UINT16_(0x0) /* (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */ 52 #define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _UINT16_(0x1) /* (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */ 53 #define NVMCTRL_CTRLA_PRM_MANUAL_Val _UINT16_(0x3) /* (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */ 54 #define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) /* (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. Position */ 55 #define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) /* (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. Position */ 56 #define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos) /* (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. Position */ 57 #define NVMCTRL_CTRLA_RWS_Pos _UINT16_(8) /* (NVMCTRL_CTRLA) NVM Read Wait States Position */ 58 #define NVMCTRL_CTRLA_RWS_Msk (_UINT16_(0xF) << NVMCTRL_CTRLA_RWS_Pos) /* (NVMCTRL_CTRLA) NVM Read Wait States Mask */ 59 #define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_RWS_Pos)) /* Assignment of value for RWS in the NVMCTRL_CTRLA register */ 60 #define NVMCTRL_CTRLA_AHBNS0_Pos _UINT16_(12) /* (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated Position */ 61 #define NVMCTRL_CTRLA_AHBNS0_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos) /* (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated Mask */ 62 #define NVMCTRL_CTRLA_AHBNS0(value) (NVMCTRL_CTRLA_AHBNS0_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_AHBNS0_Pos)) /* Assignment of value for AHBNS0 in the NVMCTRL_CTRLA register */ 63 #define NVMCTRL_CTRLA_AHBNS1_Pos _UINT16_(13) /* (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated Position */ 64 #define NVMCTRL_CTRLA_AHBNS1_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos) /* (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated Mask */ 65 #define NVMCTRL_CTRLA_AHBNS1(value) (NVMCTRL_CTRLA_AHBNS1_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_AHBNS1_Pos)) /* Assignment of value for AHBNS1 in the NVMCTRL_CTRLA register */ 66 #define NVMCTRL_CTRLA_CACHEDIS0_Pos _UINT16_(14) /* (NVMCTRL_CTRLA) AHB0 Cache Disable Position */ 67 #define NVMCTRL_CTRLA_CACHEDIS0_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos) /* (NVMCTRL_CTRLA) AHB0 Cache Disable Mask */ 68 #define NVMCTRL_CTRLA_CACHEDIS0(value) (NVMCTRL_CTRLA_CACHEDIS0_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_CACHEDIS0_Pos)) /* Assignment of value for CACHEDIS0 in the NVMCTRL_CTRLA register */ 69 #define NVMCTRL_CTRLA_CACHEDIS1_Pos _UINT16_(15) /* (NVMCTRL_CTRLA) AHB1 Cache Disable Position */ 70 #define NVMCTRL_CTRLA_CACHEDIS1_Msk (_UINT16_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos) /* (NVMCTRL_CTRLA) AHB1 Cache Disable Mask */ 71 #define NVMCTRL_CTRLA_CACHEDIS1(value) (NVMCTRL_CTRLA_CACHEDIS1_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_CACHEDIS1_Pos)) /* Assignment of value for CACHEDIS1 in the NVMCTRL_CTRLA register */ 72 #define NVMCTRL_CTRLA_Msk _UINT16_(0xFFFC) /* (NVMCTRL_CTRLA) Register Mask */ 73 74 #define NVMCTRL_CTRLA_AHBNS_Pos _UINT16_(12) /* (NVMCTRL_CTRLA Position) Force AHBx access to NONSEQ, burst transfers are continuously rearbitrated */ 75 #define NVMCTRL_CTRLA_AHBNS_Msk (_UINT16_(0x3) << NVMCTRL_CTRLA_AHBNS_Pos) /* (NVMCTRL_CTRLA Mask) AHBNS */ 76 #define NVMCTRL_CTRLA_AHBNS(value) (NVMCTRL_CTRLA_AHBNS_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_AHBNS_Pos)) 77 #define NVMCTRL_CTRLA_CACHEDIS_Pos _UINT16_(14) /* (NVMCTRL_CTRLA Position) AHBx Cache Disable */ 78 #define NVMCTRL_CTRLA_CACHEDIS_Msk (_UINT16_(0x3) << NVMCTRL_CTRLA_CACHEDIS_Pos) /* (NVMCTRL_CTRLA Mask) CACHEDIS */ 79 #define NVMCTRL_CTRLA_CACHEDIS(value) (NVMCTRL_CTRLA_CACHEDIS_Msk & (_UINT16_(value) << NVMCTRL_CTRLA_CACHEDIS_Pos)) 80 81 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */ 82 #define NVMCTRL_CTRLB_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_CTRLB) Control B Reset Value */ 83 84 #define NVMCTRL_CTRLB_CMD_Pos _UINT16_(0) /* (NVMCTRL_CTRLB) Command Position */ 85 #define NVMCTRL_CTRLB_CMD_Msk (_UINT16_(0x7F) << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Command Mask */ 86 #define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & (_UINT16_(value) << NVMCTRL_CTRLB_CMD_Pos)) /* Assignment of value for CMD in the NVMCTRL_CTRLB register */ 87 #define NVMCTRL_CTRLB_CMD_EP_Val _UINT16_(0x0) /* (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */ 88 #define NVMCTRL_CTRLB_CMD_EB_Val _UINT16_(0x1) /* (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */ 89 #define NVMCTRL_CTRLB_CMD_WP_Val _UINT16_(0x3) /* (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */ 90 #define NVMCTRL_CTRLB_CMD_WQW_Val _UINT16_(0x4) /* (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */ 91 #define NVMCTRL_CTRLB_CMD_SWRST_Val _UINT16_(0x10) /* (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */ 92 #define NVMCTRL_CTRLB_CMD_LR_Val _UINT16_(0x11) /* (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */ 93 #define NVMCTRL_CTRLB_CMD_UR_Val _UINT16_(0x12) /* (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 94 #define NVMCTRL_CTRLB_CMD_SPRM_Val _UINT16_(0x13) /* (NVMCTRL_CTRLB) Sets the power reduction mode. */ 95 #define NVMCTRL_CTRLB_CMD_CPRM_Val _UINT16_(0x14) /* (NVMCTRL_CTRLB) Clears the power reduction mode. */ 96 #define NVMCTRL_CTRLB_CMD_PBC_Val _UINT16_(0x15) /* (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */ 97 #define NVMCTRL_CTRLB_CMD_SSB_Val _UINT16_(0x16) /* (NVMCTRL_CTRLB) Set Security Bit */ 98 #define NVMCTRL_CTRLB_CMD_BKSWRST_Val _UINT16_(0x17) /* (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */ 99 #define NVMCTRL_CTRLB_CMD_CELCK_Val _UINT16_(0x18) /* (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */ 100 #define NVMCTRL_CTRLB_CMD_CEULCK_Val _UINT16_(0x19) /* (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */ 101 #define NVMCTRL_CTRLB_CMD_SBPDIS_Val _UINT16_(0x1A) /* (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */ 102 #define NVMCTRL_CTRLB_CMD_CBPDIS_Val _UINT16_(0x1B) /* (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */ 103 #define NVMCTRL_CTRLB_CMD_SCEHL_Val _UINT16_(0x1C) /* (NVMCTRL_CTRLB) Set Chip Erase Hard Lock - DSU.CTRL.CE command is not available */ 104 #define NVMCTRL_CTRLB_CMD_SBPHL_Val _UINT16_(0x1D) /* (NVMCTRL_CTRLB) Set Boot Protect Hard Lock */ 105 #define NVMCTRL_CTRLB_CMD_ASEES0_Val _UINT16_(0x30) /* (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */ 106 #define NVMCTRL_CTRLB_CMD_ASEES1_Val _UINT16_(0x31) /* (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */ 107 #define NVMCTRL_CTRLB_CMD_SEERALOC_Val _UINT16_(0x32) /* (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */ 108 #define NVMCTRL_CTRLB_CMD_LSEE_Val _UINT16_(0x34) /* (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */ 109 #define NVMCTRL_CTRLB_CMD_USEE_Val _UINT16_(0x35) /* (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */ 110 #define NVMCTRL_CTRLB_CMD_LSEER_Val _UINT16_(0x36) /* (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */ 111 #define NVMCTRL_CTRLB_CMD_USEER_Val _UINT16_(0x37) /* (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */ 112 #define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. Position */ 113 #define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page Position */ 114 #define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page Position */ 115 #define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. Position */ 116 #define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers Position */ 117 #define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. Position */ 118 #define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. Position */ 119 #define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Sets the power reduction mode. Position */ 120 #define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Clears the power reduction mode. Position */ 121 #define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. Position */ 122 #define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Set Security Bit Position */ 123 #define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK Position */ 124 #define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available Position */ 125 #define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available Position */ 126 #define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence Position */ 127 #define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded Position */ 128 #define NVMCTRL_CTRLB_CMD_SCEHL (NVMCTRL_CTRLB_CMD_SCEHL_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Set Chip Erase Hard Lock - DSU.CTRL.CE command is not available Position */ 129 #define NVMCTRL_CTRLB_CMD_SBPHL (NVMCTRL_CTRLB_CMD_SBPHL_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Set Boot Protect Hard Lock Position */ 130 #define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 Position */ 131 #define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 Position */ 132 #define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm Position */ 133 #define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean Position */ 134 #define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data Position */ 135 #define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) Position */ 136 #define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos) /* (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) Position */ 137 #define NVMCTRL_CTRLB_CMDEX_Pos _UINT16_(8) /* (NVMCTRL_CTRLB) Command Execution Position */ 138 #define NVMCTRL_CTRLB_CMDEX_Msk (_UINT16_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos) /* (NVMCTRL_CTRLB) Command Execution Mask */ 139 #define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & (_UINT16_(value) << NVMCTRL_CTRLB_CMDEX_Pos)) /* Assignment of value for CMDEX in the NVMCTRL_CTRLB register */ 140 #define NVMCTRL_CTRLB_CMDEX_KEY_Val _UINT16_(0xA5) /* (NVMCTRL_CTRLB) Execution Key */ 141 #define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos) /* (NVMCTRL_CTRLB) Execution Key Position */ 142 #define NVMCTRL_CTRLB_Msk _UINT16_(0xFF7F) /* (NVMCTRL_CTRLB) Register Mask */ 143 144 145 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) ( R/ 32) NVM Parameter -------- */ 146 #define NVMCTRL_PARAM_RESETVALUE _UINT32_(0x60000) /* (NVMCTRL_PARAM) NVM Parameter Reset Value */ 147 148 #define NVMCTRL_PARAM_NVMP_Pos _UINT32_(0) /* (NVMCTRL_PARAM) NVM Pages Position */ 149 #define NVMCTRL_PARAM_NVMP_Msk (_UINT32_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) /* (NVMCTRL_PARAM) NVM Pages Mask */ 150 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & (_UINT32_(value) << NVMCTRL_PARAM_NVMP_Pos)) /* Assignment of value for NVMP in the NVMCTRL_PARAM register */ 151 #define NVMCTRL_PARAM_PSZ_Pos _UINT32_(16) /* (NVMCTRL_PARAM) Page Size Position */ 152 #define NVMCTRL_PARAM_PSZ_Msk (_UINT32_(0x7) << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) Page Size Mask */ 153 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & (_UINT32_(value) << NVMCTRL_PARAM_PSZ_Pos)) /* Assignment of value for PSZ in the NVMCTRL_PARAM register */ 154 #define NVMCTRL_PARAM_PSZ_8_Val _UINT32_(0x0) /* (NVMCTRL_PARAM) 8 bytes */ 155 #define NVMCTRL_PARAM_PSZ_16_Val _UINT32_(0x1) /* (NVMCTRL_PARAM) 16 bytes */ 156 #define NVMCTRL_PARAM_PSZ_32_Val _UINT32_(0x2) /* (NVMCTRL_PARAM) 32 bytes */ 157 #define NVMCTRL_PARAM_PSZ_64_Val _UINT32_(0x3) /* (NVMCTRL_PARAM) 64 bytes */ 158 #define NVMCTRL_PARAM_PSZ_128_Val _UINT32_(0x4) /* (NVMCTRL_PARAM) 128 bytes */ 159 #define NVMCTRL_PARAM_PSZ_256_Val _UINT32_(0x5) /* (NVMCTRL_PARAM) 256 bytes */ 160 #define NVMCTRL_PARAM_PSZ_512_Val _UINT32_(0x6) /* (NVMCTRL_PARAM) 512 bytes */ 161 #define NVMCTRL_PARAM_PSZ_1024_Val _UINT32_(0x7) /* (NVMCTRL_PARAM) 1024 bytes */ 162 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 8 bytes Position */ 163 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 16 bytes Position */ 164 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 32 bytes Position */ 165 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 64 bytes Position */ 166 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 128 bytes Position */ 167 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 256 bytes Position */ 168 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 512 bytes Position */ 169 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) /* (NVMCTRL_PARAM) 1024 bytes Position */ 170 #define NVMCTRL_PARAM_SEE_Pos _UINT32_(31) /* (NVMCTRL_PARAM) SmartEEPROM Supported Position */ 171 #define NVMCTRL_PARAM_SEE_Msk (_UINT32_(0x1) << NVMCTRL_PARAM_SEE_Pos) /* (NVMCTRL_PARAM) SmartEEPROM Supported Mask */ 172 #define NVMCTRL_PARAM_SEE(value) (NVMCTRL_PARAM_SEE_Msk & (_UINT32_(value) << NVMCTRL_PARAM_SEE_Pos)) /* Assignment of value for SEE in the NVMCTRL_PARAM register */ 173 #define NVMCTRL_PARAM_SEE_SMARTEEPROM_Val _UINT32_(0x1) /* (NVMCTRL_PARAM) SmartEEPROM is supported */ 174 #define NVMCTRL_PARAM_SEE_NOSMARTEEPROM_Val _UINT32_(0x0) /* (NVMCTRL_PARAM) No SmartEEPROM support */ 175 #define NVMCTRL_PARAM_SEE_SMARTEEPROM (NVMCTRL_PARAM_SEE_SMARTEEPROM_Val << NVMCTRL_PARAM_SEE_Pos) /* (NVMCTRL_PARAM) SmartEEPROM is supported Position */ 176 #define NVMCTRL_PARAM_SEE_NOSMARTEEPROM (NVMCTRL_PARAM_SEE_NOSMARTEEPROM_Val << NVMCTRL_PARAM_SEE_Pos) /* (NVMCTRL_PARAM) No SmartEEPROM support Position */ 177 #define NVMCTRL_PARAM_Msk _UINT32_(0x8007FFFF) /* (NVMCTRL_PARAM) Register Mask */ 178 179 180 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 181 #define NVMCTRL_INTENCLR_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_INTENCLR) Interrupt Enable Clear Reset Value */ 182 183 #define NVMCTRL_INTENCLR_DONE_Pos _UINT16_(0) /* (NVMCTRL_INTENCLR) Command Done Interrupt Clear Position */ 184 #define NVMCTRL_INTENCLR_DONE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_DONE_Pos) /* (NVMCTRL_INTENCLR) Command Done Interrupt Clear Mask */ 185 #define NVMCTRL_INTENCLR_DONE(value) (NVMCTRL_INTENCLR_DONE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_DONE_Pos)) /* Assignment of value for DONE in the NVMCTRL_INTENCLR register */ 186 #define NVMCTRL_INTENCLR_ADDRE_Pos _UINT16_(1) /* (NVMCTRL_INTENCLR) Address Error Position */ 187 #define NVMCTRL_INTENCLR_ADDRE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos) /* (NVMCTRL_INTENCLR) Address Error Mask */ 188 #define NVMCTRL_INTENCLR_ADDRE(value) (NVMCTRL_INTENCLR_ADDRE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_ADDRE_Pos)) /* Assignment of value for ADDRE in the NVMCTRL_INTENCLR register */ 189 #define NVMCTRL_INTENCLR_PROGE_Pos _UINT16_(2) /* (NVMCTRL_INTENCLR) Programming Error Interrupt Clear Position */ 190 #define NVMCTRL_INTENCLR_PROGE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos) /* (NVMCTRL_INTENCLR) Programming Error Interrupt Clear Mask */ 191 #define NVMCTRL_INTENCLR_PROGE(value) (NVMCTRL_INTENCLR_PROGE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_PROGE_Pos)) /* Assignment of value for PROGE in the NVMCTRL_INTENCLR register */ 192 #define NVMCTRL_INTENCLR_LOCKE_Pos _UINT16_(3) /* (NVMCTRL_INTENCLR) Lock Error Interrupt Clear Position */ 193 #define NVMCTRL_INTENCLR_LOCKE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos) /* (NVMCTRL_INTENCLR) Lock Error Interrupt Clear Mask */ 194 #define NVMCTRL_INTENCLR_LOCKE(value) (NVMCTRL_INTENCLR_LOCKE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_LOCKE_Pos)) /* Assignment of value for LOCKE in the NVMCTRL_INTENCLR register */ 195 #define NVMCTRL_INTENCLR_ECCSE_Pos _UINT16_(4) /* (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear Position */ 196 #define NVMCTRL_INTENCLR_ECCSE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos) /* (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear Mask */ 197 #define NVMCTRL_INTENCLR_ECCSE(value) (NVMCTRL_INTENCLR_ECCSE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_ECCSE_Pos)) /* Assignment of value for ECCSE in the NVMCTRL_INTENCLR register */ 198 #define NVMCTRL_INTENCLR_ECCDE_Pos _UINT16_(5) /* (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear Position */ 199 #define NVMCTRL_INTENCLR_ECCDE_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos) /* (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear Mask */ 200 #define NVMCTRL_INTENCLR_ECCDE(value) (NVMCTRL_INTENCLR_ECCDE_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_ECCDE_Pos)) /* Assignment of value for ECCDE in the NVMCTRL_INTENCLR register */ 201 #define NVMCTRL_INTENCLR_NVME_Pos _UINT16_(6) /* (NVMCTRL_INTENCLR) NVM Error Interrupt Clear Position */ 202 #define NVMCTRL_INTENCLR_NVME_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_NVME_Pos) /* (NVMCTRL_INTENCLR) NVM Error Interrupt Clear Mask */ 203 #define NVMCTRL_INTENCLR_NVME(value) (NVMCTRL_INTENCLR_NVME_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_NVME_Pos)) /* Assignment of value for NVME in the NVMCTRL_INTENCLR register */ 204 #define NVMCTRL_INTENCLR_SUSP_Pos _UINT16_(7) /* (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear Position */ 205 #define NVMCTRL_INTENCLR_SUSP_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos) /* (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear Mask */ 206 #define NVMCTRL_INTENCLR_SUSP(value) (NVMCTRL_INTENCLR_SUSP_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_SUSP_Pos)) /* Assignment of value for SUSP in the NVMCTRL_INTENCLR register */ 207 #define NVMCTRL_INTENCLR_SEESFULL_Pos _UINT16_(8) /* (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear Position */ 208 #define NVMCTRL_INTENCLR_SEESFULL_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos) /* (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear Mask */ 209 #define NVMCTRL_INTENCLR_SEESFULL(value) (NVMCTRL_INTENCLR_SEESFULL_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_SEESFULL_Pos)) /* Assignment of value for SEESFULL in the NVMCTRL_INTENCLR register */ 210 #define NVMCTRL_INTENCLR_SEESOVF_Pos _UINT16_(9) /* (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear Position */ 211 #define NVMCTRL_INTENCLR_SEESOVF_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos) /* (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear Mask */ 212 #define NVMCTRL_INTENCLR_SEESOVF(value) (NVMCTRL_INTENCLR_SEESOVF_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_SEESOVF_Pos)) /* Assignment of value for SEESOVF in the NVMCTRL_INTENCLR register */ 213 #define NVMCTRL_INTENCLR_SEEWRC_Pos _UINT16_(10) /* (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear Position */ 214 #define NVMCTRL_INTENCLR_SEEWRC_Msk (_UINT16_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos) /* (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear Mask */ 215 #define NVMCTRL_INTENCLR_SEEWRC(value) (NVMCTRL_INTENCLR_SEEWRC_Msk & (_UINT16_(value) << NVMCTRL_INTENCLR_SEEWRC_Pos)) /* Assignment of value for SEEWRC in the NVMCTRL_INTENCLR register */ 216 #define NVMCTRL_INTENCLR_Msk _UINT16_(0x07FF) /* (NVMCTRL_INTENCLR) Register Mask */ 217 218 219 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */ 220 #define NVMCTRL_INTENSET_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_INTENSET) Interrupt Enable Set Reset Value */ 221 222 #define NVMCTRL_INTENSET_DONE_Pos _UINT16_(0) /* (NVMCTRL_INTENSET) Command Done Interrupt Enable Position */ 223 #define NVMCTRL_INTENSET_DONE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_DONE_Pos) /* (NVMCTRL_INTENSET) Command Done Interrupt Enable Mask */ 224 #define NVMCTRL_INTENSET_DONE(value) (NVMCTRL_INTENSET_DONE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_DONE_Pos)) /* Assignment of value for DONE in the NVMCTRL_INTENSET register */ 225 #define NVMCTRL_INTENSET_ADDRE_Pos _UINT16_(1) /* (NVMCTRL_INTENSET) Address Error Interrupt Enable Position */ 226 #define NVMCTRL_INTENSET_ADDRE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos) /* (NVMCTRL_INTENSET) Address Error Interrupt Enable Mask */ 227 #define NVMCTRL_INTENSET_ADDRE(value) (NVMCTRL_INTENSET_ADDRE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_ADDRE_Pos)) /* Assignment of value for ADDRE in the NVMCTRL_INTENSET register */ 228 #define NVMCTRL_INTENSET_PROGE_Pos _UINT16_(2) /* (NVMCTRL_INTENSET) Programming Error Interrupt Enable Position */ 229 #define NVMCTRL_INTENSET_PROGE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_PROGE_Pos) /* (NVMCTRL_INTENSET) Programming Error Interrupt Enable Mask */ 230 #define NVMCTRL_INTENSET_PROGE(value) (NVMCTRL_INTENSET_PROGE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_PROGE_Pos)) /* Assignment of value for PROGE in the NVMCTRL_INTENSET register */ 231 #define NVMCTRL_INTENSET_LOCKE_Pos _UINT16_(3) /* (NVMCTRL_INTENSET) Lock Error Interrupt Enable Position */ 232 #define NVMCTRL_INTENSET_LOCKE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos) /* (NVMCTRL_INTENSET) Lock Error Interrupt Enable Mask */ 233 #define NVMCTRL_INTENSET_LOCKE(value) (NVMCTRL_INTENSET_LOCKE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_LOCKE_Pos)) /* Assignment of value for LOCKE in the NVMCTRL_INTENSET register */ 234 #define NVMCTRL_INTENSET_ECCSE_Pos _UINT16_(4) /* (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable Position */ 235 #define NVMCTRL_INTENSET_ECCSE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos) /* (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable Mask */ 236 #define NVMCTRL_INTENSET_ECCSE(value) (NVMCTRL_INTENSET_ECCSE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_ECCSE_Pos)) /* Assignment of value for ECCSE in the NVMCTRL_INTENSET register */ 237 #define NVMCTRL_INTENSET_ECCDE_Pos _UINT16_(5) /* (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable Position */ 238 #define NVMCTRL_INTENSET_ECCDE_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos) /* (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable Mask */ 239 #define NVMCTRL_INTENSET_ECCDE(value) (NVMCTRL_INTENSET_ECCDE_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_ECCDE_Pos)) /* Assignment of value for ECCDE in the NVMCTRL_INTENSET register */ 240 #define NVMCTRL_INTENSET_NVME_Pos _UINT16_(6) /* (NVMCTRL_INTENSET) NVM Error Interrupt Enable Position */ 241 #define NVMCTRL_INTENSET_NVME_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_NVME_Pos) /* (NVMCTRL_INTENSET) NVM Error Interrupt Enable Mask */ 242 #define NVMCTRL_INTENSET_NVME(value) (NVMCTRL_INTENSET_NVME_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_NVME_Pos)) /* Assignment of value for NVME in the NVMCTRL_INTENSET register */ 243 #define NVMCTRL_INTENSET_SUSP_Pos _UINT16_(7) /* (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable Position */ 244 #define NVMCTRL_INTENSET_SUSP_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_SUSP_Pos) /* (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable Mask */ 245 #define NVMCTRL_INTENSET_SUSP(value) (NVMCTRL_INTENSET_SUSP_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_SUSP_Pos)) /* Assignment of value for SUSP in the NVMCTRL_INTENSET register */ 246 #define NVMCTRL_INTENSET_SEESFULL_Pos _UINT16_(8) /* (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable Position */ 247 #define NVMCTRL_INTENSET_SEESFULL_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos) /* (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable Mask */ 248 #define NVMCTRL_INTENSET_SEESFULL(value) (NVMCTRL_INTENSET_SEESFULL_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_SEESFULL_Pos)) /* Assignment of value for SEESFULL in the NVMCTRL_INTENSET register */ 249 #define NVMCTRL_INTENSET_SEESOVF_Pos _UINT16_(9) /* (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable Position */ 250 #define NVMCTRL_INTENSET_SEESOVF_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos) /* (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable Mask */ 251 #define NVMCTRL_INTENSET_SEESOVF(value) (NVMCTRL_INTENSET_SEESOVF_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_SEESOVF_Pos)) /* Assignment of value for SEESOVF in the NVMCTRL_INTENSET register */ 252 #define NVMCTRL_INTENSET_SEEWRC_Pos _UINT16_(10) /* (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable Position */ 253 #define NVMCTRL_INTENSET_SEEWRC_Msk (_UINT16_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos) /* (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable Mask */ 254 #define NVMCTRL_INTENSET_SEEWRC(value) (NVMCTRL_INTENSET_SEEWRC_Msk & (_UINT16_(value) << NVMCTRL_INTENSET_SEEWRC_Pos)) /* Assignment of value for SEEWRC in the NVMCTRL_INTENSET register */ 255 #define NVMCTRL_INTENSET_Msk _UINT16_(0x07FF) /* (NVMCTRL_INTENSET) Register Mask */ 256 257 258 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */ 259 #define NVMCTRL_INTFLAG_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 260 261 #define NVMCTRL_INTFLAG_DONE_Pos _UINT16_(0) /* (NVMCTRL_INTFLAG) Command Done Position */ 262 #define NVMCTRL_INTFLAG_DONE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_DONE_Pos) /* (NVMCTRL_INTFLAG) Command Done Mask */ 263 #define NVMCTRL_INTFLAG_DONE(value) (NVMCTRL_INTFLAG_DONE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_DONE_Pos)) /* Assignment of value for DONE in the NVMCTRL_INTFLAG register */ 264 #define NVMCTRL_INTFLAG_ADDRE_Pos _UINT16_(1) /* (NVMCTRL_INTFLAG) Address Error Position */ 265 #define NVMCTRL_INTFLAG_ADDRE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos) /* (NVMCTRL_INTFLAG) Address Error Mask */ 266 #define NVMCTRL_INTFLAG_ADDRE(value) (NVMCTRL_INTFLAG_ADDRE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_ADDRE_Pos)) /* Assignment of value for ADDRE in the NVMCTRL_INTFLAG register */ 267 #define NVMCTRL_INTFLAG_PROGE_Pos _UINT16_(2) /* (NVMCTRL_INTFLAG) Programming Error Position */ 268 #define NVMCTRL_INTFLAG_PROGE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos) /* (NVMCTRL_INTFLAG) Programming Error Mask */ 269 #define NVMCTRL_INTFLAG_PROGE(value) (NVMCTRL_INTFLAG_PROGE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_PROGE_Pos)) /* Assignment of value for PROGE in the NVMCTRL_INTFLAG register */ 270 #define NVMCTRL_INTFLAG_LOCKE_Pos _UINT16_(3) /* (NVMCTRL_INTFLAG) Lock Error Position */ 271 #define NVMCTRL_INTFLAG_LOCKE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos) /* (NVMCTRL_INTFLAG) Lock Error Mask */ 272 #define NVMCTRL_INTFLAG_LOCKE(value) (NVMCTRL_INTFLAG_LOCKE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_LOCKE_Pos)) /* Assignment of value for LOCKE in the NVMCTRL_INTFLAG register */ 273 #define NVMCTRL_INTFLAG_ECCSE_Pos _UINT16_(4) /* (NVMCTRL_INTFLAG) ECC Single Error Position */ 274 #define NVMCTRL_INTFLAG_ECCSE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos) /* (NVMCTRL_INTFLAG) ECC Single Error Mask */ 275 #define NVMCTRL_INTFLAG_ECCSE(value) (NVMCTRL_INTFLAG_ECCSE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_ECCSE_Pos)) /* Assignment of value for ECCSE in the NVMCTRL_INTFLAG register */ 276 #define NVMCTRL_INTFLAG_ECCDE_Pos _UINT16_(5) /* (NVMCTRL_INTFLAG) ECC Dual Error Position */ 277 #define NVMCTRL_INTFLAG_ECCDE_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos) /* (NVMCTRL_INTFLAG) ECC Dual Error Mask */ 278 #define NVMCTRL_INTFLAG_ECCDE(value) (NVMCTRL_INTFLAG_ECCDE_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_ECCDE_Pos)) /* Assignment of value for ECCDE in the NVMCTRL_INTFLAG register */ 279 #define NVMCTRL_INTFLAG_NVME_Pos _UINT16_(6) /* (NVMCTRL_INTFLAG) NVM Error Position */ 280 #define NVMCTRL_INTFLAG_NVME_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_NVME_Pos) /* (NVMCTRL_INTFLAG) NVM Error Mask */ 281 #define NVMCTRL_INTFLAG_NVME(value) (NVMCTRL_INTFLAG_NVME_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_NVME_Pos)) /* Assignment of value for NVME in the NVMCTRL_INTFLAG register */ 282 #define NVMCTRL_INTFLAG_SUSP_Pos _UINT16_(7) /* (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation Position */ 283 #define NVMCTRL_INTFLAG_SUSP_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos) /* (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation Mask */ 284 #define NVMCTRL_INTFLAG_SUSP(value) (NVMCTRL_INTFLAG_SUSP_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_SUSP_Pos)) /* Assignment of value for SUSP in the NVMCTRL_INTFLAG register */ 285 #define NVMCTRL_INTFLAG_SEESFULL_Pos _UINT16_(8) /* (NVMCTRL_INTFLAG) Active SEES Full Position */ 286 #define NVMCTRL_INTFLAG_SEESFULL_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos) /* (NVMCTRL_INTFLAG) Active SEES Full Mask */ 287 #define NVMCTRL_INTFLAG_SEESFULL(value) (NVMCTRL_INTFLAG_SEESFULL_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_SEESFULL_Pos)) /* Assignment of value for SEESFULL in the NVMCTRL_INTFLAG register */ 288 #define NVMCTRL_INTFLAG_SEESOVF_Pos _UINT16_(9) /* (NVMCTRL_INTFLAG) Active SEES Overflow Position */ 289 #define NVMCTRL_INTFLAG_SEESOVF_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos) /* (NVMCTRL_INTFLAG) Active SEES Overflow Mask */ 290 #define NVMCTRL_INTFLAG_SEESOVF(value) (NVMCTRL_INTFLAG_SEESOVF_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_SEESOVF_Pos)) /* Assignment of value for SEESOVF in the NVMCTRL_INTFLAG register */ 291 #define NVMCTRL_INTFLAG_SEEWRC_Pos _UINT16_(10) /* (NVMCTRL_INTFLAG) SEE Write Completed Position */ 292 #define NVMCTRL_INTFLAG_SEEWRC_Msk (_UINT16_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos) /* (NVMCTRL_INTFLAG) SEE Write Completed Mask */ 293 #define NVMCTRL_INTFLAG_SEEWRC(value) (NVMCTRL_INTFLAG_SEEWRC_Msk & (_UINT16_(value) << NVMCTRL_INTFLAG_SEEWRC_Pos)) /* Assignment of value for SEEWRC in the NVMCTRL_INTFLAG register */ 294 #define NVMCTRL_INTFLAG_Msk _UINT16_(0x07FF) /* (NVMCTRL_INTFLAG) Register Mask */ 295 296 297 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) ( R/ 16) Status -------- */ 298 #define NVMCTRL_STATUS_RESETVALUE _UINT16_(0x00) /* (NVMCTRL_STATUS) Status Reset Value */ 299 300 #define NVMCTRL_STATUS_READY_Pos _UINT16_(0) /* (NVMCTRL_STATUS) Ready to accept a command Position */ 301 #define NVMCTRL_STATUS_READY_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_READY_Pos) /* (NVMCTRL_STATUS) Ready to accept a command Mask */ 302 #define NVMCTRL_STATUS_READY(value) (NVMCTRL_STATUS_READY_Msk & (_UINT16_(value) << NVMCTRL_STATUS_READY_Pos)) /* Assignment of value for READY in the NVMCTRL_STATUS register */ 303 #define NVMCTRL_STATUS_PRM_Pos _UINT16_(1) /* (NVMCTRL_STATUS) Power Reduction Mode Position */ 304 #define NVMCTRL_STATUS_PRM_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_PRM_Pos) /* (NVMCTRL_STATUS) Power Reduction Mode Mask */ 305 #define NVMCTRL_STATUS_PRM(value) (NVMCTRL_STATUS_PRM_Msk & (_UINT16_(value) << NVMCTRL_STATUS_PRM_Pos)) /* Assignment of value for PRM in the NVMCTRL_STATUS register */ 306 #define NVMCTRL_STATUS_LOAD_Pos _UINT16_(2) /* (NVMCTRL_STATUS) NVM Page Buffer Active Loading Position */ 307 #define NVMCTRL_STATUS_LOAD_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_LOAD_Pos) /* (NVMCTRL_STATUS) NVM Page Buffer Active Loading Mask */ 308 #define NVMCTRL_STATUS_LOAD(value) (NVMCTRL_STATUS_LOAD_Msk & (_UINT16_(value) << NVMCTRL_STATUS_LOAD_Pos)) /* Assignment of value for LOAD in the NVMCTRL_STATUS register */ 309 #define NVMCTRL_STATUS_SUSP_Pos _UINT16_(3) /* (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended Position */ 310 #define NVMCTRL_STATUS_SUSP_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_SUSP_Pos) /* (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended Mask */ 311 #define NVMCTRL_STATUS_SUSP(value) (NVMCTRL_STATUS_SUSP_Msk & (_UINT16_(value) << NVMCTRL_STATUS_SUSP_Pos)) /* Assignment of value for SUSP in the NVMCTRL_STATUS register */ 312 #define NVMCTRL_STATUS_AFIRST_Pos _UINT16_(4) /* (NVMCTRL_STATUS) BANKA First Position */ 313 #define NVMCTRL_STATUS_AFIRST_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_AFIRST_Pos) /* (NVMCTRL_STATUS) BANKA First Mask */ 314 #define NVMCTRL_STATUS_AFIRST(value) (NVMCTRL_STATUS_AFIRST_Msk & (_UINT16_(value) << NVMCTRL_STATUS_AFIRST_Pos)) /* Assignment of value for AFIRST in the NVMCTRL_STATUS register */ 315 #define NVMCTRL_STATUS_BPDIS_Pos _UINT16_(5) /* (NVMCTRL_STATUS) Boot Loader Protection Disable Position */ 316 #define NVMCTRL_STATUS_BPDIS_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_BPDIS_Pos) /* (NVMCTRL_STATUS) Boot Loader Protection Disable Mask */ 317 #define NVMCTRL_STATUS_BPDIS(value) (NVMCTRL_STATUS_BPDIS_Msk & (_UINT16_(value) << NVMCTRL_STATUS_BPDIS_Pos)) /* Assignment of value for BPDIS in the NVMCTRL_STATUS register */ 318 #define NVMCTRL_STATUS_BOOTPROT_Pos _UINT16_(8) /* (NVMCTRL_STATUS) Boot Loader Protection Size Position */ 319 #define NVMCTRL_STATUS_BOOTPROT_Msk (_UINT16_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) Boot Loader Protection Size Mask */ 320 #define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & (_UINT16_(value) << NVMCTRL_STATUS_BOOTPROT_Pos)) /* Assignment of value for BOOTPROT in the NVMCTRL_STATUS register */ 321 #define NVMCTRL_STATUS_BOOTPROT_0_Val _UINT16_(0xF) /* (NVMCTRL_STATUS) 0 kbytes */ 322 #define NVMCTRL_STATUS_BOOTPROT_8_Val _UINT16_(0xE) /* (NVMCTRL_STATUS) 8 kbytes */ 323 #define NVMCTRL_STATUS_BOOTPROT_16_Val _UINT16_(0xD) /* (NVMCTRL_STATUS) 16 kbytes */ 324 #define NVMCTRL_STATUS_BOOTPROT_24_Val _UINT16_(0xC) /* (NVMCTRL_STATUS) 24 kbytes */ 325 #define NVMCTRL_STATUS_BOOTPROT_32_Val _UINT16_(0xB) /* (NVMCTRL_STATUS) 32 kbytes */ 326 #define NVMCTRL_STATUS_BOOTPROT_40_Val _UINT16_(0xA) /* (NVMCTRL_STATUS) 40 kbytes */ 327 #define NVMCTRL_STATUS_BOOTPROT_48_Val _UINT16_(0x9) /* (NVMCTRL_STATUS) 48 kbytes */ 328 #define NVMCTRL_STATUS_BOOTPROT_56_Val _UINT16_(0x8) /* (NVMCTRL_STATUS) 56 kbytes */ 329 #define NVMCTRL_STATUS_BOOTPROT_64_Val _UINT16_(0x7) /* (NVMCTRL_STATUS) 64 kbytes */ 330 #define NVMCTRL_STATUS_BOOTPROT_72_Val _UINT16_(0x6) /* (NVMCTRL_STATUS) 72 kbytes */ 331 #define NVMCTRL_STATUS_BOOTPROT_80_Val _UINT16_(0x5) /* (NVMCTRL_STATUS) 80 kbytes */ 332 #define NVMCTRL_STATUS_BOOTPROT_88_Val _UINT16_(0x4) /* (NVMCTRL_STATUS) 88 kbytes */ 333 #define NVMCTRL_STATUS_BOOTPROT_96_Val _UINT16_(0x3) /* (NVMCTRL_STATUS) 96 kbytes */ 334 #define NVMCTRL_STATUS_BOOTPROT_104_Val _UINT16_(0x2) /* (NVMCTRL_STATUS) 104 kbytes */ 335 #define NVMCTRL_STATUS_BOOTPROT_112_Val _UINT16_(0x1) /* (NVMCTRL_STATUS) 112 kbytes */ 336 #define NVMCTRL_STATUS_BOOTPROT_120_Val _UINT16_(0x0) /* (NVMCTRL_STATUS) 120 kbytes */ 337 #define NVMCTRL_STATUS_BOOTPROT_0 (NVMCTRL_STATUS_BOOTPROT_0_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 0 kbytes Position */ 338 #define NVMCTRL_STATUS_BOOTPROT_8 (NVMCTRL_STATUS_BOOTPROT_8_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 8 kbytes Position */ 339 #define NVMCTRL_STATUS_BOOTPROT_16 (NVMCTRL_STATUS_BOOTPROT_16_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 16 kbytes Position */ 340 #define NVMCTRL_STATUS_BOOTPROT_24 (NVMCTRL_STATUS_BOOTPROT_24_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 24 kbytes Position */ 341 #define NVMCTRL_STATUS_BOOTPROT_32 (NVMCTRL_STATUS_BOOTPROT_32_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 32 kbytes Position */ 342 #define NVMCTRL_STATUS_BOOTPROT_40 (NVMCTRL_STATUS_BOOTPROT_40_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 40 kbytes Position */ 343 #define NVMCTRL_STATUS_BOOTPROT_48 (NVMCTRL_STATUS_BOOTPROT_48_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 48 kbytes Position */ 344 #define NVMCTRL_STATUS_BOOTPROT_56 (NVMCTRL_STATUS_BOOTPROT_56_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 56 kbytes Position */ 345 #define NVMCTRL_STATUS_BOOTPROT_64 (NVMCTRL_STATUS_BOOTPROT_64_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 64 kbytes Position */ 346 #define NVMCTRL_STATUS_BOOTPROT_72 (NVMCTRL_STATUS_BOOTPROT_72_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 72 kbytes Position */ 347 #define NVMCTRL_STATUS_BOOTPROT_80 (NVMCTRL_STATUS_BOOTPROT_80_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 80 kbytes Position */ 348 #define NVMCTRL_STATUS_BOOTPROT_88 (NVMCTRL_STATUS_BOOTPROT_88_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 88 kbytes Position */ 349 #define NVMCTRL_STATUS_BOOTPROT_96 (NVMCTRL_STATUS_BOOTPROT_96_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 96 kbytes Position */ 350 #define NVMCTRL_STATUS_BOOTPROT_104 (NVMCTRL_STATUS_BOOTPROT_104_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 104 kbytes Position */ 351 #define NVMCTRL_STATUS_BOOTPROT_112 (NVMCTRL_STATUS_BOOTPROT_112_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 112 kbytes Position */ 352 #define NVMCTRL_STATUS_BOOTPROT_120 (NVMCTRL_STATUS_BOOTPROT_120_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /* (NVMCTRL_STATUS) 120 kbytes Position */ 353 #define NVMCTRL_STATUS_DBPE_Pos _UINT16_(12) /* (NVMCTRL_STATUS) Dual Boot Protection Enable Position */ 354 #define NVMCTRL_STATUS_DBPE_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_DBPE_Pos) /* (NVMCTRL_STATUS) Dual Boot Protection Enable Mask */ 355 #define NVMCTRL_STATUS_DBPE(value) (NVMCTRL_STATUS_DBPE_Msk & (_UINT16_(value) << NVMCTRL_STATUS_DBPE_Pos)) /* Assignment of value for DBPE in the NVMCTRL_STATUS register */ 356 #define NVMCTRL_STATUS_BPHL_Pos _UINT16_(13) /* (NVMCTRL_STATUS) Boot Protect Hard Lock Position */ 357 #define NVMCTRL_STATUS_BPHL_Msk (_UINT16_(0x1) << NVMCTRL_STATUS_BPHL_Pos) /* (NVMCTRL_STATUS) Boot Protect Hard Lock Mask */ 358 #define NVMCTRL_STATUS_BPHL(value) (NVMCTRL_STATUS_BPHL_Msk & (_UINT16_(value) << NVMCTRL_STATUS_BPHL_Pos)) /* Assignment of value for BPHL in the NVMCTRL_STATUS register */ 359 #define NVMCTRL_STATUS_Msk _UINT16_(0x3F3F) /* (NVMCTRL_STATUS) Register Mask */ 360 361 362 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */ 363 #define NVMCTRL_ADDR_RESETVALUE _UINT32_(0x00) /* (NVMCTRL_ADDR) Address Reset Value */ 364 365 #define NVMCTRL_ADDR_ADDR_Pos _UINT32_(0) /* (NVMCTRL_ADDR) NVM Address Position */ 366 #define NVMCTRL_ADDR_ADDR_Msk (_UINT32_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos) /* (NVMCTRL_ADDR) NVM Address Mask */ 367 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & (_UINT32_(value) << NVMCTRL_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the NVMCTRL_ADDR register */ 368 #define NVMCTRL_ADDR_Msk _UINT32_(0x00FFFFFF) /* (NVMCTRL_ADDR) Register Mask */ 369 370 371 /* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) ( R/ 32) Lock Section -------- */ 372 #define NVMCTRL_RUNLOCK_RESETVALUE _UINT32_(0x00) /* (NVMCTRL_RUNLOCK) Lock Section Reset Value */ 373 374 #define NVMCTRL_RUNLOCK_RUNLOCK_Pos _UINT32_(0) /* (NVMCTRL_RUNLOCK) Region Un-Lock Bits Position */ 375 #define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_UINT32_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos) /* (NVMCTRL_RUNLOCK) Region Un-Lock Bits Mask */ 376 #define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & (_UINT32_(value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)) /* Assignment of value for RUNLOCK in the NVMCTRL_RUNLOCK register */ 377 #define NVMCTRL_RUNLOCK_Msk _UINT32_(0xFFFFFFFF) /* (NVMCTRL_RUNLOCK) Register Mask */ 378 379 380 /* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) ( R/ 32) Page Buffer Load Data x -------- */ 381 #define NVMCTRL_PBLDATA_RESETVALUE _UINT32_(0xFFFFFFFF) /* (NVMCTRL_PBLDATA) Page Buffer Load Data x Reset Value */ 382 383 #define NVMCTRL_PBLDATA_DATA_Pos _UINT32_(0) /* (NVMCTRL_PBLDATA) Page Buffer Data Position */ 384 #define NVMCTRL_PBLDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos) /* (NVMCTRL_PBLDATA) Page Buffer Data Mask */ 385 #define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & (_UINT32_(value) << NVMCTRL_PBLDATA_DATA_Pos)) /* Assignment of value for DATA in the NVMCTRL_PBLDATA register */ 386 #define NVMCTRL_PBLDATA_Msk _UINT32_(0xFFFFFFFF) /* (NVMCTRL_PBLDATA) Register Mask */ 387 388 389 /* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) ( R/ 32) ECC Error Status Register -------- */ 390 #define NVMCTRL_ECCERR_RESETVALUE _UINT32_(0x00) /* (NVMCTRL_ECCERR) ECC Error Status Register Reset Value */ 391 392 #define NVMCTRL_ECCERR_ADDR_Pos _UINT32_(0) /* (NVMCTRL_ECCERR) Error Address Position */ 393 #define NVMCTRL_ECCERR_ADDR_Msk (_UINT32_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos) /* (NVMCTRL_ECCERR) Error Address Mask */ 394 #define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & (_UINT32_(value) << NVMCTRL_ECCERR_ADDR_Pos)) /* Assignment of value for ADDR in the NVMCTRL_ECCERR register */ 395 #define NVMCTRL_ECCERR_TYPEL_Pos _UINT32_(28) /* (NVMCTRL_ECCERR) Low Double-Word Error Type Position */ 396 #define NVMCTRL_ECCERR_TYPEL_Msk (_UINT32_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos) /* (NVMCTRL_ECCERR) Low Double-Word Error Type Mask */ 397 #define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & (_UINT32_(value) << NVMCTRL_ECCERR_TYPEL_Pos)) /* Assignment of value for TYPEL in the NVMCTRL_ECCERR register */ 398 #define NVMCTRL_ECCERR_TYPEL_NONE_Val _UINT32_(0x0) /* (NVMCTRL_ECCERR) No Error Detected Since Last Read */ 399 #define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _UINT32_(0x1) /* (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */ 400 #define NVMCTRL_ECCERR_TYPEL_DUAL_Val _UINT32_(0x2) /* (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */ 401 #define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos) /* (NVMCTRL_ECCERR) No Error Detected Since Last Read Position */ 402 #define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos) /* (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read Position */ 403 #define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos) /* (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read Position */ 404 #define NVMCTRL_ECCERR_TYPEH_Pos _UINT32_(30) /* (NVMCTRL_ECCERR) High Double-Word Error Type Position */ 405 #define NVMCTRL_ECCERR_TYPEH_Msk (_UINT32_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos) /* (NVMCTRL_ECCERR) High Double-Word Error Type Mask */ 406 #define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & (_UINT32_(value) << NVMCTRL_ECCERR_TYPEH_Pos)) /* Assignment of value for TYPEH in the NVMCTRL_ECCERR register */ 407 #define NVMCTRL_ECCERR_TYPEH_NONE_Val _UINT32_(0x0) /* (NVMCTRL_ECCERR) No Error Detected Since Last Read */ 408 #define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _UINT32_(0x1) /* (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */ 409 #define NVMCTRL_ECCERR_TYPEH_DUAL_Val _UINT32_(0x2) /* (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */ 410 #define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos) /* (NVMCTRL_ECCERR) No Error Detected Since Last Read Position */ 411 #define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos) /* (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read Position */ 412 #define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos) /* (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read Position */ 413 #define NVMCTRL_ECCERR_Msk _UINT32_(0xF0FFFFFF) /* (NVMCTRL_ECCERR) Register Mask */ 414 415 416 /* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */ 417 #define NVMCTRL_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (NVMCTRL_DBGCTRL) Debug Control Reset Value */ 418 419 #define NVMCTRL_DBGCTRL_ECCDIS_Pos _UINT8_(0) /* (NVMCTRL_DBGCTRL) Debugger ECC Read Disable Position */ 420 #define NVMCTRL_DBGCTRL_ECCDIS_Msk (_UINT8_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos) /* (NVMCTRL_DBGCTRL) Debugger ECC Read Disable Mask */ 421 #define NVMCTRL_DBGCTRL_ECCDIS(value) (NVMCTRL_DBGCTRL_ECCDIS_Msk & (_UINT8_(value) << NVMCTRL_DBGCTRL_ECCDIS_Pos)) /* Assignment of value for ECCDIS in the NVMCTRL_DBGCTRL register */ 422 #define NVMCTRL_DBGCTRL_ECCELOG_Pos _UINT8_(1) /* (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode Position */ 423 #define NVMCTRL_DBGCTRL_ECCELOG_Msk (_UINT8_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos) /* (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode Mask */ 424 #define NVMCTRL_DBGCTRL_ECCELOG(value) (NVMCTRL_DBGCTRL_ECCELOG_Msk & (_UINT8_(value) << NVMCTRL_DBGCTRL_ECCELOG_Pos)) /* Assignment of value for ECCELOG in the NVMCTRL_DBGCTRL register */ 425 #define NVMCTRL_DBGCTRL_Msk _UINT8_(0x03) /* (NVMCTRL_DBGCTRL) Register Mask */ 426 427 428 /* -------- NVMCTRL_BCTRL : (NVMCTRL Offset: 0x29) (R/W 8) Boot Control -------- */ 429 #define NVMCTRL_BCTRL_RESETVALUE _UINT8_(0x00) /* (NVMCTRL_BCTRL) Boot Control Reset Value */ 430 431 #define NVMCTRL_BCTRL_BRPE_Pos _UINT8_(0) /* (NVMCTRL_BCTRL) Boot Read Protection Enable Position */ 432 #define NVMCTRL_BCTRL_BRPE_Msk (_UINT8_(0x1) << NVMCTRL_BCTRL_BRPE_Pos) /* (NVMCTRL_BCTRL) Boot Read Protection Enable Mask */ 433 #define NVMCTRL_BCTRL_BRPE(value) (NVMCTRL_BCTRL_BRPE_Msk & (_UINT8_(value) << NVMCTRL_BCTRL_BRPE_Pos)) /* Assignment of value for BRPE in the NVMCTRL_BCTRL register */ 434 #define NVMCTRL_BCTRL_Msk _UINT8_(0x01) /* (NVMCTRL_BCTRL) Register Mask */ 435 436 437 /* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */ 438 #define NVMCTRL_SEECFG_RESETVALUE _UINT8_(0x00) /* (NVMCTRL_SEECFG) SmartEEPROM Configuration Register Reset Value */ 439 440 #define NVMCTRL_SEECFG_WMODE_Pos _UINT8_(0) /* (NVMCTRL_SEECFG) Write Mode Position */ 441 #define NVMCTRL_SEECFG_WMODE_Msk (_UINT8_(0x1) << NVMCTRL_SEECFG_WMODE_Pos) /* (NVMCTRL_SEECFG) Write Mode Mask */ 442 #define NVMCTRL_SEECFG_WMODE(value) (NVMCTRL_SEECFG_WMODE_Msk & (_UINT8_(value) << NVMCTRL_SEECFG_WMODE_Pos)) /* Assignment of value for WMODE in the NVMCTRL_SEECFG register */ 443 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _UINT8_(0x0) /* (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */ 444 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos) /* (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer Position */ 445 #define NVMCTRL_SEECFG_APRDIS_Pos _UINT8_(1) /* (NVMCTRL_SEECFG) Automatic Page Reallocation Disable Position */ 446 #define NVMCTRL_SEECFG_APRDIS_Msk (_UINT8_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos) /* (NVMCTRL_SEECFG) Automatic Page Reallocation Disable Mask */ 447 #define NVMCTRL_SEECFG_APRDIS(value) (NVMCTRL_SEECFG_APRDIS_Msk & (_UINT8_(value) << NVMCTRL_SEECFG_APRDIS_Pos)) /* Assignment of value for APRDIS in the NVMCTRL_SEECFG register */ 448 #define NVMCTRL_SEECFG_Msk _UINT8_(0x03) /* (NVMCTRL_SEECFG) Register Mask */ 449 450 451 /* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) ( R/ 32) SmartEEPROM Status Register -------- */ 452 #define NVMCTRL_SEESTAT_RESETVALUE _UINT32_(0x00) /* (NVMCTRL_SEESTAT) SmartEEPROM Status Register Reset Value */ 453 454 #define NVMCTRL_SEESTAT_ASEES_Pos _UINT32_(0) /* (NVMCTRL_SEESTAT) Active SmartEEPROM Sector Position */ 455 #define NVMCTRL_SEESTAT_ASEES_Msk (_UINT32_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos) /* (NVMCTRL_SEESTAT) Active SmartEEPROM Sector Mask */ 456 #define NVMCTRL_SEESTAT_ASEES(value) (NVMCTRL_SEESTAT_ASEES_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_ASEES_Pos)) /* Assignment of value for ASEES in the NVMCTRL_SEESTAT register */ 457 #define NVMCTRL_SEESTAT_BUSY_Pos _UINT32_(2) /* (NVMCTRL_SEESTAT) Busy Position */ 458 #define NVMCTRL_SEESTAT_BUSY_Msk (_UINT32_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos) /* (NVMCTRL_SEESTAT) Busy Mask */ 459 #define NVMCTRL_SEESTAT_BUSY(value) (NVMCTRL_SEESTAT_BUSY_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_BUSY_Pos)) /* Assignment of value for BUSY in the NVMCTRL_SEESTAT register */ 460 #define NVMCTRL_SEESTAT_LOCK_Pos _UINT32_(3) /* (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked Position */ 461 #define NVMCTRL_SEESTAT_LOCK_Msk (_UINT32_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos) /* (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked Mask */ 462 #define NVMCTRL_SEESTAT_LOCK(value) (NVMCTRL_SEESTAT_LOCK_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_LOCK_Pos)) /* Assignment of value for LOCK in the NVMCTRL_SEESTAT register */ 463 #define NVMCTRL_SEESTAT_RLOCK_Pos _UINT32_(4) /* (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked Position */ 464 #define NVMCTRL_SEESTAT_RLOCK_Msk (_UINT32_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos) /* (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked Mask */ 465 #define NVMCTRL_SEESTAT_RLOCK(value) (NVMCTRL_SEESTAT_RLOCK_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_RLOCK_Pos)) /* Assignment of value for RLOCK in the NVMCTRL_SEESTAT register */ 466 #define NVMCTRL_SEESTAT_SBLK_Pos _UINT32_(8) /* (NVMCTRL_SEESTAT) Blocks Number In a Sector Position */ 467 #define NVMCTRL_SEESTAT_SBLK_Msk (_UINT32_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos) /* (NVMCTRL_SEESTAT) Blocks Number In a Sector Mask */ 468 #define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_SBLK_Pos)) /* Assignment of value for SBLK in the NVMCTRL_SEESTAT register */ 469 #define NVMCTRL_SEESTAT_PSZ_Pos _UINT32_(16) /* (NVMCTRL_SEESTAT) SmartEEPROM Page Size Position */ 470 #define NVMCTRL_SEESTAT_PSZ_Msk (_UINT32_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos) /* (NVMCTRL_SEESTAT) SmartEEPROM Page Size Mask */ 471 #define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & (_UINT32_(value) << NVMCTRL_SEESTAT_PSZ_Pos)) /* Assignment of value for PSZ in the NVMCTRL_SEESTAT register */ 472 #define NVMCTRL_SEESTAT_Msk _UINT32_(0x00070F1D) /* (NVMCTRL_SEESTAT) Register Mask */ 473 474 475 /* NVMCTRL register offsets definitions */ 476 #define NVMCTRL_CTRLA_REG_OFST _UINT32_(0x00) /* (NVMCTRL_CTRLA) Control A Offset */ 477 #define NVMCTRL_CTRLB_REG_OFST _UINT32_(0x04) /* (NVMCTRL_CTRLB) Control B Offset */ 478 #define NVMCTRL_PARAM_REG_OFST _UINT32_(0x08) /* (NVMCTRL_PARAM) NVM Parameter Offset */ 479 #define NVMCTRL_INTENCLR_REG_OFST _UINT32_(0x0C) /* (NVMCTRL_INTENCLR) Interrupt Enable Clear Offset */ 480 #define NVMCTRL_INTENSET_REG_OFST _UINT32_(0x0E) /* (NVMCTRL_INTENSET) Interrupt Enable Set Offset */ 481 #define NVMCTRL_INTFLAG_REG_OFST _UINT32_(0x10) /* (NVMCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */ 482 #define NVMCTRL_STATUS_REG_OFST _UINT32_(0x12) /* (NVMCTRL_STATUS) Status Offset */ 483 #define NVMCTRL_ADDR_REG_OFST _UINT32_(0x14) /* (NVMCTRL_ADDR) Address Offset */ 484 #define NVMCTRL_RUNLOCK_REG_OFST _UINT32_(0x18) /* (NVMCTRL_RUNLOCK) Lock Section Offset */ 485 #define NVMCTRL_PBLDATA_REG_OFST _UINT32_(0x1C) /* (NVMCTRL_PBLDATA) Page Buffer Load Data x Offset */ 486 #define NVMCTRL_PBLDATA0_REG_OFST _UINT32_(0x1C) /* (NVMCTRL_PBLDATA0) Page Buffer Load Data x Offset */ 487 #define NVMCTRL_PBLDATA1_REG_OFST _UINT32_(0x20) /* (NVMCTRL_PBLDATA1) Page Buffer Load Data x Offset */ 488 #define NVMCTRL_ECCERR_REG_OFST _UINT32_(0x24) /* (NVMCTRL_ECCERR) ECC Error Status Register Offset */ 489 #define NVMCTRL_DBGCTRL_REG_OFST _UINT32_(0x28) /* (NVMCTRL_DBGCTRL) Debug Control Offset */ 490 #define NVMCTRL_BCTRL_REG_OFST _UINT32_(0x29) /* (NVMCTRL_BCTRL) Boot Control Offset */ 491 #define NVMCTRL_SEECFG_REG_OFST _UINT32_(0x2A) /* (NVMCTRL_SEECFG) SmartEEPROM Configuration Register Offset */ 492 #define NVMCTRL_SEESTAT_REG_OFST _UINT32_(0x2C) /* (NVMCTRL_SEESTAT) SmartEEPROM Status Register Offset */ 493 494 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 495 /* NVMCTRL register API structure */ 496 typedef struct 497 { /* Non-Volatile Memory Controller */ 498 __IO uint16_t NVMCTRL_CTRLA; /* Offset: 0x00 (R/W 16) Control A */ 499 __I uint8_t Reserved1[0x02]; 500 __O uint16_t NVMCTRL_CTRLB; /* Offset: 0x04 ( /W 16) Control B */ 501 __I uint8_t Reserved2[0x02]; 502 __I uint32_t NVMCTRL_PARAM; /* Offset: 0x08 (R/ 32) NVM Parameter */ 503 __IO uint16_t NVMCTRL_INTENCLR; /* Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 504 __IO uint16_t NVMCTRL_INTENSET; /* Offset: 0x0E (R/W 16) Interrupt Enable Set */ 505 __IO uint16_t NVMCTRL_INTFLAG; /* Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */ 506 __I uint16_t NVMCTRL_STATUS; /* Offset: 0x12 (R/ 16) Status */ 507 __IO uint32_t NVMCTRL_ADDR; /* Offset: 0x14 (R/W 32) Address */ 508 __I uint32_t NVMCTRL_RUNLOCK; /* Offset: 0x18 (R/ 32) Lock Section */ 509 __I uint32_t NVMCTRL_PBLDATA[2]; /* Offset: 0x1C (R/ 32) Page Buffer Load Data x */ 510 __I uint32_t NVMCTRL_ECCERR; /* Offset: 0x24 (R/ 32) ECC Error Status Register */ 511 __IO uint8_t NVMCTRL_DBGCTRL; /* Offset: 0x28 (R/W 8) Debug Control */ 512 __IO uint8_t NVMCTRL_BCTRL; /* Offset: 0x29 (R/W 8) Boot Control */ 513 __IO uint8_t NVMCTRL_SEECFG; /* Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */ 514 __I uint8_t Reserved3[0x01]; 515 __I uint32_t NVMCTRL_SEESTAT; /* Offset: 0x2C (R/ 32) SmartEEPROM Status Register */ 516 } nvmctrl_registers_t; 517 518 519 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 520 #endif /* _PIC32CXSG41_NVMCTRL_COMPONENT_H_ */ 521
