1 /* 2 * Component description for DAC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_DAC_COMPONENT_H_ 22 #define _PIC32CXSG41_DAC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR DAC */ 26 /* ************************************************************************** */ 27 28 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 29 #define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ 30 31 #define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ 32 #define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ 33 #define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_CTRLA register */ 34 #define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable DAC Controller Position */ 35 #define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable DAC Controller Mask */ 36 #define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_CTRLA register */ 37 #define DAC_CTRLA_Msk _UINT8_(0x03) /* (DAC_CTRLA) Register Mask */ 38 39 40 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 41 #define DAC_CTRLB_RESETVALUE _UINT8_(0x02) /* (DAC_CTRLB) Control B Reset Value */ 42 43 #define DAC_CTRLB_DIFF_Pos _UINT8_(0) /* (DAC_CTRLB) Differential mode enable Position */ 44 #define DAC_CTRLB_DIFF_Msk (_UINT8_(0x1) << DAC_CTRLB_DIFF_Pos) /* (DAC_CTRLB) Differential mode enable Mask */ 45 #define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & (_UINT8_(value) << DAC_CTRLB_DIFF_Pos)) /* Assignment of value for DIFF in the DAC_CTRLB register */ 46 #define DAC_CTRLB_REFSEL_Pos _UINT8_(1) /* (DAC_CTRLB) Reference Selection for DAC0/1 Position */ 47 #define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ 48 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assignment of value for REFSEL in the DAC_CTRLB register */ 49 #define DAC_CTRLB_REFSEL_VREFAU_Val _UINT8_(0x0) /* (DAC_CTRLB) External reference unbuffered */ 50 #define DAC_CTRLB_REFSEL_AVDD_Val _UINT8_(0x1) /* (DAC_CTRLB) Analog supply */ 51 #define DAC_CTRLB_REFSEL_VREFAB_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference buffered */ 52 #define DAC_CTRLB_REFSEL_INTREF_Val _UINT8_(0x3) /* (DAC_CTRLB) Internal bandgap reference */ 53 #define DAC_CTRLB_REFSEL_VREFAU (DAC_CTRLB_REFSEL_VREFAU_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference unbuffered Position */ 54 #define DAC_CTRLB_REFSEL_AVDD (DAC_CTRLB_REFSEL_AVDD_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Analog supply Position */ 55 #define DAC_CTRLB_REFSEL_VREFAB (DAC_CTRLB_REFSEL_VREFAB_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference buffered Position */ 56 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal bandgap reference Position */ 57 #define DAC_CTRLB_Msk _UINT8_(0x07) /* (DAC_CTRLB) Register Mask */ 58 59 60 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 61 #define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ 62 63 #define DAC_EVCTRL_STARTEI0_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ 64 #define DAC_EVCTRL_STARTEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ 65 #define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI0_Pos)) /* Assignment of value for STARTEI0 in the DAC_EVCTRL register */ 66 #define DAC_EVCTRL_STARTEI1_Pos _UINT8_(1) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ 67 #define DAC_EVCTRL_STARTEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ 68 #define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI1_Pos)) /* Assignment of value for STARTEI1 in the DAC_EVCTRL register */ 69 #define DAC_EVCTRL_EMPTYEO0_Pos _UINT8_(2) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ 70 #define DAC_EVCTRL_EMPTYEO0_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ 71 #define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO0_Pos)) /* Assignment of value for EMPTYEO0 in the DAC_EVCTRL register */ 72 #define DAC_EVCTRL_EMPTYEO1_Pos _UINT8_(3) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ 73 #define DAC_EVCTRL_EMPTYEO1_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ 74 #define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO1_Pos)) /* Assignment of value for EMPTYEO1 in the DAC_EVCTRL register */ 75 #define DAC_EVCTRL_INVEI0_Pos _UINT8_(4) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ 76 #define DAC_EVCTRL_INVEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI0_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ 77 #define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI0_Pos)) /* Assignment of value for INVEI0 in the DAC_EVCTRL register */ 78 #define DAC_EVCTRL_INVEI1_Pos _UINT8_(5) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ 79 #define DAC_EVCTRL_INVEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI1_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ 80 #define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI1_Pos)) /* Assignment of value for INVEI1 in the DAC_EVCTRL register */ 81 #define DAC_EVCTRL_Msk _UINT8_(0x3F) /* (DAC_EVCTRL) Register Mask */ 82 83 #define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ 84 #define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL Mask) STARTEI */ 85 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) 86 #define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(2) /* (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ 87 #define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL Mask) EMPTYEO */ 88 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) 89 #define DAC_EVCTRL_INVEI_Pos _UINT8_(4) /* (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ 90 #define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL Mask) INVEI */ 91 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) 92 93 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 94 #define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ 95 96 #define DAC_INTENCLR_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ 97 #define DAC_INTENCLR_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ 98 #define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN0_Pos)) /* Assignment of value for UNDERRUN0 in the DAC_INTENCLR register */ 99 #define DAC_INTENCLR_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ 100 #define DAC_INTENCLR_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ 101 #define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN1_Pos)) /* Assignment of value for UNDERRUN1 in the DAC_INTENCLR register */ 102 #define DAC_INTENCLR_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ 103 #define DAC_INTENCLR_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ 104 #define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY0_Pos)) /* Assignment of value for EMPTY0 in the DAC_INTENCLR register */ 105 #define DAC_INTENCLR_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ 106 #define DAC_INTENCLR_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ 107 #define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY1_Pos)) /* Assignment of value for EMPTY1 in the DAC_INTENCLR register */ 108 #define DAC_INTENCLR_Msk _UINT8_(0x0F) /* (DAC_INTENCLR) Register Mask */ 109 110 #define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR Position) Underrun x Interrupt Enable */ 111 #define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR Mask) UNDERRUN */ 112 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) 113 #define DAC_INTENCLR_EMPTY_Pos _UINT8_(2) /* (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ 114 #define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR Mask) EMPTY */ 115 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) 116 117 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 118 #define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ 119 120 #define DAC_INTENSET_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ 121 #define DAC_INTENSET_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ 122 #define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN0_Pos)) /* Assignment of value for UNDERRUN0 in the DAC_INTENSET register */ 123 #define DAC_INTENSET_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ 124 #define DAC_INTENSET_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ 125 #define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN1_Pos)) /* Assignment of value for UNDERRUN1 in the DAC_INTENSET register */ 126 #define DAC_INTENSET_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ 127 #define DAC_INTENSET_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY0_Pos) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ 128 #define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY0_Pos)) /* Assignment of value for EMPTY0 in the DAC_INTENSET register */ 129 #define DAC_INTENSET_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ 130 #define DAC_INTENSET_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY1_Pos) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ 131 #define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY1_Pos)) /* Assignment of value for EMPTY1 in the DAC_INTENSET register */ 132 #define DAC_INTENSET_Msk _UINT8_(0x0F) /* (DAC_INTENSET) Register Mask */ 133 134 #define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET Position) Underrun x Interrupt Enable */ 135 #define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET Mask) UNDERRUN */ 136 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) 137 #define DAC_INTENSET_EMPTY_Pos _UINT8_(2) /* (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ 138 #define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET Mask) EMPTY */ 139 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) 140 141 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 142 #define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 143 144 #define DAC_INTFLAG_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTFLAG) Result 0 Underrun Position */ 145 #define DAC_INTFLAG_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /* (DAC_INTFLAG) Result 0 Underrun Mask */ 146 #define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN0_Pos)) /* Assignment of value for UNDERRUN0 in the DAC_INTFLAG register */ 147 #define DAC_INTFLAG_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTFLAG) Result 1 Underrun Position */ 148 #define DAC_INTFLAG_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /* (DAC_INTFLAG) Result 1 Underrun Mask */ 149 #define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN1_Pos)) /* Assignment of value for UNDERRUN1 in the DAC_INTFLAG register */ 150 #define DAC_INTFLAG_EMPTY0_Pos _UINT8_(2) /* (DAC_INTFLAG) Data Buffer 0 Empty Position */ 151 #define DAC_INTFLAG_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /* (DAC_INTFLAG) Data Buffer 0 Empty Mask */ 152 #define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY0_Pos)) /* Assignment of value for EMPTY0 in the DAC_INTFLAG register */ 153 #define DAC_INTFLAG_EMPTY1_Pos _UINT8_(3) /* (DAC_INTFLAG) Data Buffer 1 Empty Position */ 154 #define DAC_INTFLAG_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /* (DAC_INTFLAG) Data Buffer 1 Empty Mask */ 155 #define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY1_Pos)) /* Assignment of value for EMPTY1 in the DAC_INTFLAG register */ 156 #define DAC_INTFLAG_Msk _UINT8_(0x0F) /* (DAC_INTFLAG) Register Mask */ 157 158 #define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG Position) Result x Underrun */ 159 #define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG Mask) UNDERRUN */ 160 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) 161 #define DAC_INTFLAG_EMPTY_Pos _UINT8_(2) /* (DAC_INTFLAG Position) Data Buffer x Empty */ 162 #define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x3) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG Mask) EMPTY */ 163 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) 164 165 /* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ 166 #define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ 167 168 #define DAC_STATUS_READY0_Pos _UINT8_(0) /* (DAC_STATUS) DAC 0 Startup Ready Position */ 169 #define DAC_STATUS_READY0_Msk (_UINT8_(0x1) << DAC_STATUS_READY0_Pos) /* (DAC_STATUS) DAC 0 Startup Ready Mask */ 170 #define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & (_UINT8_(value) << DAC_STATUS_READY0_Pos)) /* Assignment of value for READY0 in the DAC_STATUS register */ 171 #define DAC_STATUS_READY1_Pos _UINT8_(1) /* (DAC_STATUS) DAC 1 Startup Ready Position */ 172 #define DAC_STATUS_READY1_Msk (_UINT8_(0x1) << DAC_STATUS_READY1_Pos) /* (DAC_STATUS) DAC 1 Startup Ready Mask */ 173 #define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & (_UINT8_(value) << DAC_STATUS_READY1_Pos)) /* Assignment of value for READY1 in the DAC_STATUS register */ 174 #define DAC_STATUS_EOC0_Pos _UINT8_(2) /* (DAC_STATUS) DAC 0 End of Conversion Position */ 175 #define DAC_STATUS_EOC0_Msk (_UINT8_(0x1) << DAC_STATUS_EOC0_Pos) /* (DAC_STATUS) DAC 0 End of Conversion Mask */ 176 #define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & (_UINT8_(value) << DAC_STATUS_EOC0_Pos)) /* Assignment of value for EOC0 in the DAC_STATUS register */ 177 #define DAC_STATUS_EOC1_Pos _UINT8_(3) /* (DAC_STATUS) DAC 1 End of Conversion Position */ 178 #define DAC_STATUS_EOC1_Msk (_UINT8_(0x1) << DAC_STATUS_EOC1_Pos) /* (DAC_STATUS) DAC 1 End of Conversion Mask */ 179 #define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & (_UINT8_(value) << DAC_STATUS_EOC1_Pos)) /* Assignment of value for EOC1 in the DAC_STATUS register */ 180 #define DAC_STATUS_Msk _UINT8_(0x0F) /* (DAC_STATUS) Register Mask */ 181 182 #define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS Position) DAC x Startup Ready */ 183 #define DAC_STATUS_READY_Msk (_UINT8_(0x3) << DAC_STATUS_READY_Pos) /* (DAC_STATUS Mask) READY */ 184 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) 185 #define DAC_STATUS_EOC_Pos _UINT8_(2) /* (DAC_STATUS Position) DAC x End of Conversion */ 186 #define DAC_STATUS_EOC_Msk (_UINT8_(0x3) << DAC_STATUS_EOC_Pos) /* (DAC_STATUS Mask) EOC */ 187 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & (_UINT8_(value) << DAC_STATUS_EOC_Pos)) 188 189 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 190 #define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ 191 192 #define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ 193 #define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ 194 #define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_SYNCBUSY register */ 195 #define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) DAC Enable Status Position */ 196 #define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) DAC Enable Status Mask */ 197 #define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_SYNCBUSY register */ 198 #define DAC_SYNCBUSY_DATA0_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data DAC 0 Position */ 199 #define DAC_SYNCBUSY_DATA0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /* (DAC_SYNCBUSY) Data DAC 0 Mask */ 200 #define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA0_Pos)) /* Assignment of value for DATA0 in the DAC_SYNCBUSY register */ 201 #define DAC_SYNCBUSY_DATA1_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data DAC 1 Position */ 202 #define DAC_SYNCBUSY_DATA1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /* (DAC_SYNCBUSY) Data DAC 1 Mask */ 203 #define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA1_Pos)) /* Assignment of value for DATA1 in the DAC_SYNCBUSY register */ 204 #define DAC_SYNCBUSY_DATABUF0_Pos _UINT32_(4) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ 205 #define DAC_SYNCBUSY_DATABUF0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ 206 #define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF0_Pos)) /* Assignment of value for DATABUF0 in the DAC_SYNCBUSY register */ 207 #define DAC_SYNCBUSY_DATABUF1_Pos _UINT32_(5) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ 208 #define DAC_SYNCBUSY_DATABUF1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ 209 #define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF1_Pos)) /* Assignment of value for DATABUF1 in the DAC_SYNCBUSY register */ 210 #define DAC_SYNCBUSY_Msk _UINT32_(0x0000003F) /* (DAC_SYNCBUSY) Register Mask */ 211 212 #define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY Position) Data DAC x */ 213 #define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY Mask) DATA */ 214 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) 215 #define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(4) /* (DAC_SYNCBUSY Position) Data Buffer DAC x */ 216 #define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY Mask) DATABUF */ 217 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) 218 219 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ 220 #define DAC_DACCTRL_RESETVALUE _UINT16_(0x00) /* (DAC_DACCTRL) DAC n Control Reset Value */ 221 222 #define DAC_DACCTRL_LEFTADJ_Pos _UINT16_(0) /* (DAC_DACCTRL) Left Adjusted Data Position */ 223 #define DAC_DACCTRL_LEFTADJ_Msk (_UINT16_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /* (DAC_DACCTRL) Left Adjusted Data Mask */ 224 #define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & (_UINT16_(value) << DAC_DACCTRL_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the DAC_DACCTRL register */ 225 #define DAC_DACCTRL_ENABLE_Pos _UINT16_(1) /* (DAC_DACCTRL) Enable DAC0 Position */ 226 #define DAC_DACCTRL_ENABLE_Msk (_UINT16_(0x1) << DAC_DACCTRL_ENABLE_Pos) /* (DAC_DACCTRL) Enable DAC0 Mask */ 227 #define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & (_UINT16_(value) << DAC_DACCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_DACCTRL register */ 228 #define DAC_DACCTRL_CCTRL_Pos _UINT16_(2) /* (DAC_DACCTRL) Current Control Position */ 229 #define DAC_DACCTRL_CCTRL_Msk (_UINT16_(0x3) << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) Current Control Mask */ 230 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & (_UINT16_(value) << DAC_DACCTRL_CCTRL_Pos)) /* Assignment of value for CCTRL in the DAC_DACCTRL register */ 231 #define DAC_DACCTRL_CCTRL_CC100K_Val _UINT16_(0x0) /* (DAC_DACCTRL) 100kSPS */ 232 #define DAC_DACCTRL_CCTRL_CC1M_Val _UINT16_(0x1) /* (DAC_DACCTRL) 500kSPS */ 233 #define DAC_DACCTRL_CCTRL_CC12M_Val _UINT16_(0x2) /* (DAC_DACCTRL) 1MSPS */ 234 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 100kSPS Position */ 235 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 500kSPS Position */ 236 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 1MSPS Position */ 237 #define DAC_DACCTRL_RUNSTDBY_Pos _UINT16_(6) /* (DAC_DACCTRL) Run in Standby Position */ 238 #define DAC_DACCTRL_RUNSTDBY_Msk (_UINT16_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /* (DAC_DACCTRL) Run in Standby Mask */ 239 #define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & (_UINT16_(value) << DAC_DACCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the DAC_DACCTRL register */ 240 #define DAC_DACCTRL_DITHER_Pos _UINT16_(7) /* (DAC_DACCTRL) Dithering Mode Position */ 241 #define DAC_DACCTRL_DITHER_Msk (_UINT16_(0x1) << DAC_DACCTRL_DITHER_Pos) /* (DAC_DACCTRL) Dithering Mode Mask */ 242 #define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & (_UINT16_(value) << DAC_DACCTRL_DITHER_Pos)) /* Assignment of value for DITHER in the DAC_DACCTRL register */ 243 #define DAC_DACCTRL_Msk _UINT16_(0x00CF) /* (DAC_DACCTRL) Register Mask */ 244 245 246 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ 247 #define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) DAC n Data Reset Value */ 248 249 #define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) DAC0 Data Position */ 250 #define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) DAC0 Data Mask */ 251 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assignment of value for DATA in the DAC_DATA register */ 252 #define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ 253 254 255 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ 256 #define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) DAC n Data Buffer Reset Value */ 257 258 #define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) DAC0 Data Buffer Position */ 259 #define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) DAC0 Data Buffer Mask */ 260 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assignment of value for DATABUF in the DAC_DATABUF register */ 261 #define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ 262 263 264 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ 265 #define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ 266 267 #define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ 268 #define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ 269 #define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the DAC_DBGCTRL register */ 270 #define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ 271 272 273 /* DAC register offsets definitions */ 274 #define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ 275 #define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ 276 #define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ 277 #define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ 278 #define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ 279 #define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ 280 #define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ 281 #define DAC_SYNCBUSY_REG_OFST _UINT32_(0x08) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ 282 #define DAC_DACCTRL_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL) DAC n Control Offset */ 283 #define DAC_DACCTRL0_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL0) DAC n Control Offset */ 284 #define DAC_DACCTRL1_REG_OFST _UINT32_(0x0E) /* (DAC_DACCTRL1) DAC n Control Offset */ 285 #define DAC_DATA_REG_OFST _UINT32_(0x10) /* (DAC_DATA) DAC n Data Offset */ 286 #define DAC_DATA0_REG_OFST _UINT32_(0x10) /* (DAC_DATA0) DAC n Data Offset */ 287 #define DAC_DATA1_REG_OFST _UINT32_(0x12) /* (DAC_DATA1) DAC n Data Offset */ 288 #define DAC_DATABUF_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF) DAC n Data Buffer Offset */ 289 #define DAC_DATABUF0_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF0) DAC n Data Buffer Offset */ 290 #define DAC_DATABUF1_REG_OFST _UINT32_(0x16) /* (DAC_DATABUF1) DAC n Data Buffer Offset */ 291 #define DAC_DBGCTRL_REG_OFST _UINT32_(0x18) /* (DAC_DBGCTRL) Debug Control Offset */ 292 293 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 294 /* DAC register API structure */ 295 typedef struct 296 { /* Digital-to-Analog Converter */ 297 __IO uint8_t DAC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ 298 __IO uint8_t DAC_CTRLB; /* Offset: 0x01 (R/W 8) Control B */ 299 __IO uint8_t DAC_EVCTRL; /* Offset: 0x02 (R/W 8) Event Control */ 300 __I uint8_t Reserved1[0x01]; 301 __IO uint8_t DAC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 302 __IO uint8_t DAC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ 303 __IO uint8_t DAC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 304 __I uint8_t DAC_STATUS; /* Offset: 0x07 (R/ 8) Status */ 305 __I uint32_t DAC_SYNCBUSY; /* Offset: 0x08 (R/ 32) Synchronization Busy */ 306 __IO uint16_t DAC_DACCTRL[2]; /* Offset: 0x0C (R/W 16) DAC n Control */ 307 __O uint16_t DAC_DATA[2]; /* Offset: 0x10 ( /W 16) DAC n Data */ 308 __O uint16_t DAC_DATABUF[2]; /* Offset: 0x14 ( /W 16) DAC n Data Buffer */ 309 __IO uint8_t DAC_DBGCTRL; /* Offset: 0x18 (R/W 8) Debug Control */ 310 } dac_registers_t; 311 312 313 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 #endif /* _PIC32CXSG41_DAC_COMPONENT_H_ */ 315
