1 /* 2 * Component description for ADC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_ADC_COMPONENT_H_ 22 #define _PIC32CXSG41_ADC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR ADC */ 26 /* ************************************************************************** */ 27 28 /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ 29 #define ADC_CTRLA_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLA) Control A Reset Value */ 30 31 #define ADC_CTRLA_SWRST_Pos _UINT16_(0) /* (ADC_CTRLA) Software Reset Position */ 32 #define ADC_CTRLA_SWRST_Msk (_UINT16_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ 33 #define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT16_(value) << ADC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_CTRLA register */ 34 #define ADC_CTRLA_ENABLE_Pos _UINT16_(1) /* (ADC_CTRLA) Enable Position */ 35 #define ADC_CTRLA_ENABLE_Msk (_UINT16_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ 36 #define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT16_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_CTRLA register */ 37 #define ADC_CTRLA_DUALSEL_Pos _UINT16_(3) /* (ADC_CTRLA) Dual Mode Trigger Selection Position */ 38 #define ADC_CTRLA_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Dual Mode Trigger Selection Mask */ 39 #define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLA_DUALSEL_Pos)) /* Assignment of value for DUALSEL in the ADC_CTRLA register */ 40 #define ADC_CTRLA_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ 41 #define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ 42 #define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ 43 #define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ 44 #define ADC_CTRLA_SLAVEEN_Pos _UINT16_(5) /* (ADC_CTRLA) Slave Enable Position */ 45 #define ADC_CTRLA_SLAVEEN_Msk (_UINT16_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ 46 #define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT16_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assignment of value for SLAVEEN in the ADC_CTRLA register */ 47 #define ADC_CTRLA_RUNSTDBY_Pos _UINT16_(6) /* (ADC_CTRLA) Run in Standby Position */ 48 #define ADC_CTRLA_RUNSTDBY_Msk (_UINT16_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run in Standby Mask */ 49 #define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT16_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the ADC_CTRLA register */ 50 #define ADC_CTRLA_ONDEMAND_Pos _UINT16_(7) /* (ADC_CTRLA) On Demand Control Position */ 51 #define ADC_CTRLA_ONDEMAND_Msk (_UINT16_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ 52 #define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT16_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the ADC_CTRLA register */ 53 #define ADC_CTRLA_PRESCALER_Pos _UINT16_(8) /* (ADC_CTRLA) Prescaler Configuration Position */ 54 #define ADC_CTRLA_PRESCALER_Msk (_UINT16_(0x7) << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Prescaler Configuration Mask */ 55 #define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & (_UINT16_(value) << ADC_CTRLA_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the ADC_CTRLA register */ 56 #define ADC_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x0) /* (ADC_CTRLA) Peripheral clock divided by 2 */ 57 #define ADC_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x1) /* (ADC_CTRLA) Peripheral clock divided by 4 */ 58 #define ADC_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x2) /* (ADC_CTRLA) Peripheral clock divided by 8 */ 59 #define ADC_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x3) /* (ADC_CTRLA) Peripheral clock divided by 16 */ 60 #define ADC_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x4) /* (ADC_CTRLA) Peripheral clock divided by 32 */ 61 #define ADC_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x5) /* (ADC_CTRLA) Peripheral clock divided by 64 */ 62 #define ADC_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x6) /* (ADC_CTRLA) Peripheral clock divided by 128 */ 63 #define ADC_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x7) /* (ADC_CTRLA) Peripheral clock divided by 256 */ 64 #define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 2 Position */ 65 #define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 4 Position */ 66 #define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 8 Position */ 67 #define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 16 Position */ 68 #define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 32 Position */ 69 #define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 64 Position */ 70 #define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 128 Position */ 71 #define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 256 Position */ 72 #define ADC_CTRLA_R2R_Pos _UINT16_(15) /* (ADC_CTRLA) Rail to Rail Operation Enable Position */ 73 #define ADC_CTRLA_R2R_Msk (_UINT16_(0x1) << ADC_CTRLA_R2R_Pos) /* (ADC_CTRLA) Rail to Rail Operation Enable Mask */ 74 #define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & (_UINT16_(value) << ADC_CTRLA_R2R_Pos)) /* Assignment of value for R2R in the ADC_CTRLA register */ 75 #define ADC_CTRLA_Msk _UINT16_(0x87FB) /* (ADC_CTRLA) Register Mask */ 76 77 78 /* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ 79 #define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ 80 81 #define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ 82 #define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ 83 #define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assignment of value for FLUSHEI in the ADC_EVCTRL register */ 84 #define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ 85 #define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ 86 #define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the ADC_EVCTRL register */ 87 #define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ 88 #define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ 89 #define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assignment of value for FLUSHINV in the ADC_EVCTRL register */ 90 #define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ 91 #define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ 92 #define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assignment of value for STARTINV in the ADC_EVCTRL register */ 93 #define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ 94 #define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ 95 #define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assignment of value for RESRDYEO in the ADC_EVCTRL register */ 96 #define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ 97 #define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ 98 #define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assignment of value for WINMONEO in the ADC_EVCTRL register */ 99 #define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ 100 101 102 /* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ 103 #define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ 104 105 #define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ 106 #define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ 107 #define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the ADC_DBGCTRL register */ 108 #define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ 109 110 111 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ 112 #define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ 113 114 #define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ 115 #define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ 116 #define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the ADC_INPUTCTRL register */ 117 #define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ 118 #define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ 119 #define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ 120 #define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ 121 #define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ 122 #define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ 123 #define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ 124 #define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ 125 #define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ 126 #define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ 127 #define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ 128 #define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ 129 #define ADC_INPUTCTRL_MUXPOS_AIN12_Val _UINT16_(0xC) /* (ADC_INPUTCTRL) ADC AIN12 Pin */ 130 #define ADC_INPUTCTRL_MUXPOS_AIN13_Val _UINT16_(0xD) /* (ADC_INPUTCTRL) ADC AIN13 Pin */ 131 #define ADC_INPUTCTRL_MUXPOS_AIN14_Val _UINT16_(0xE) /* (ADC_INPUTCTRL) ADC AIN14 Pin */ 132 #define ADC_INPUTCTRL_MUXPOS_AIN15_Val _UINT16_(0xF) /* (ADC_INPUTCTRL) ADC AIN15 Pin */ 133 #define ADC_INPUTCTRL_MUXPOS_SCALEDVDDCORE_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) 1/4 Scaled VDDCORE Supply */ 134 #define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ 135 #define ADC_INPUTCTRL_MUXPOS_SCALEDVDD_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled VDD Supply */ 136 #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) Bandgap Voltage */ 137 #define ADC_INPUTCTRL_MUXPOS_DAC0_Val _UINT16_(0x1E) /* (ADC_INPUTCTRL) DAC0 output */ 138 #define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ 139 #define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ 140 #define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ 141 #define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ 142 #define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ 143 #define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ 144 #define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ 145 #define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ 146 #define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ 147 #define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ 148 #define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ 149 #define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ 150 #define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN12 Pin Position */ 151 #define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN13 Pin Position */ 152 #define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN14 Pin Position */ 153 #define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN15 Pin Position */ 154 #define ADC_INPUTCTRL_MUXPOS_SCALEDVDDCORE (ADC_INPUTCTRL_MUXPOS_SCALEDVDDCORE_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled VDDCORE Supply Position */ 155 #define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ 156 #define ADC_INPUTCTRL_MUXPOS_SCALEDVDD (ADC_INPUTCTRL_MUXPOS_SCALEDVDD_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled VDD Supply Position */ 157 #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ 158 #define ADC_INPUTCTRL_MUXPOS_DAC0 (ADC_INPUTCTRL_MUXPOS_DAC0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC0 output Position */ 159 #define ADC_INPUTCTRL_DIFFMODE_Pos _UINT16_(7) /* (ADC_INPUTCTRL) Differential Mode Position */ 160 #define ADC_INPUTCTRL_DIFFMODE_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /* (ADC_INPUTCTRL) Differential Mode Mask */ 161 #define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DIFFMODE_Pos)) /* Assignment of value for DIFFMODE in the ADC_INPUTCTRL register */ 162 #define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ 163 #define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ 164 #define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the ADC_INPUTCTRL register */ 165 #define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ 166 #define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ 167 #define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ 168 #define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ 169 #define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ 170 #define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ 171 #define ADC_INPUTCTRL_MUXNEG_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ 172 #define ADC_INPUTCTRL_MUXNEG_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ 173 #define ADC_INPUTCTRL_MUXNEG_AVSS_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ 174 #define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ 175 #define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ 176 #define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ 177 #define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ 178 #define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ 179 #define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ 180 #define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ 181 #define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ 182 #define ADC_INPUTCTRL_MUXNEG_AVSS (ADC_INPUTCTRL_MUXNEG_AVSS_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ 183 #define ADC_INPUTCTRL_DSEQSTOP_Pos _UINT16_(15) /* (ADC_INPUTCTRL) Stop DMA Sequencing Position */ 184 #define ADC_INPUTCTRL_DSEQSTOP_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /* (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ 185 #define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) /* Assignment of value for DSEQSTOP in the ADC_INPUTCTRL register */ 186 #define ADC_INPUTCTRL_Msk _UINT16_(0x9F9F) /* (ADC_INPUTCTRL) Register Mask */ 187 188 189 /* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ 190 #define ADC_CTRLB_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLB) Control B Reset Value */ 191 192 #define ADC_CTRLB_LEFTADJ_Pos _UINT16_(0) /* (ADC_CTRLB) Left-Adjusted Result Position */ 193 #define ADC_CTRLB_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /* (ADC_CTRLB) Left-Adjusted Result Mask */ 194 #define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLB_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the ADC_CTRLB register */ 195 #define ADC_CTRLB_FREERUN_Pos _UINT16_(1) /* (ADC_CTRLB) Free Running Mode Position */ 196 #define ADC_CTRLB_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLB_FREERUN_Pos) /* (ADC_CTRLB) Free Running Mode Mask */ 197 #define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLB_FREERUN_Pos)) /* Assignment of value for FREERUN in the ADC_CTRLB register */ 198 #define ADC_CTRLB_CORREN_Pos _UINT16_(2) /* (ADC_CTRLB) Digital Correction Logic Enable Position */ 199 #define ADC_CTRLB_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLB_CORREN_Pos) /* (ADC_CTRLB) Digital Correction Logic Enable Mask */ 200 #define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & (_UINT16_(value) << ADC_CTRLB_CORREN_Pos)) /* Assignment of value for CORREN in the ADC_CTRLB register */ 201 #define ADC_CTRLB_RESSEL_Pos _UINT16_(3) /* (ADC_CTRLB) Conversion Result Resolution Position */ 202 #define ADC_CTRLB_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) Conversion Result Resolution Mask */ 203 #define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLB_RESSEL_Pos)) /* Assignment of value for RESSEL in the ADC_CTRLB register */ 204 #define ADC_CTRLB_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLB) 12-bit result */ 205 #define ADC_CTRLB_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLB) For averaging mode output */ 206 #define ADC_CTRLB_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLB) 10-bit result */ 207 #define ADC_CTRLB_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLB) 8-bit result */ 208 #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 12-bit result Position */ 209 #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) For averaging mode output Position */ 210 #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 10-bit result Position */ 211 #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 8-bit result Position */ 212 #define ADC_CTRLB_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLB) Window Monitor Mode Position */ 213 #define ADC_CTRLB_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) Window Monitor Mode Mask */ 214 #define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLB_WINMODE_Pos)) /* Assignment of value for WINMODE in the ADC_CTRLB register */ 215 #define ADC_CTRLB_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLB) No window mode (default) */ 216 #define ADC_CTRLB_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLB) RESULT > WINLT */ 217 #define ADC_CTRLB_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLB) RESULT < WINUT */ 218 #define ADC_CTRLB_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLB) WINLT < RESULT < WINUT */ 219 #define ADC_CTRLB_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ 220 #define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) No window mode (default) Position */ 221 #define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT > WINLT Position */ 222 #define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT < WINUT Position */ 223 #define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) WINLT < RESULT < WINUT Position */ 224 #define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ 225 #define ADC_CTRLB_WINSS_Pos _UINT16_(11) /* (ADC_CTRLB) Window Single Sample Position */ 226 #define ADC_CTRLB_WINSS_Msk (_UINT16_(0x1) << ADC_CTRLB_WINSS_Pos) /* (ADC_CTRLB) Window Single Sample Mask */ 227 #define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & (_UINT16_(value) << ADC_CTRLB_WINSS_Pos)) /* Assignment of value for WINSS in the ADC_CTRLB register */ 228 #define ADC_CTRLB_Msk _UINT16_(0x0F1F) /* (ADC_CTRLB) Register Mask */ 229 230 231 /* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ 232 #define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ 233 234 #define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ 235 #define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ 236 #define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assignment of value for REFSEL in the ADC_REFCTRL register */ 237 #define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ 238 #define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 AVDD */ 239 #define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x3) /* (ADC_REFCTRL) AVDD */ 240 #define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x4) /* (ADC_REFCTRL) External Reference A */ 241 #define ADC_REFCTRL_REFSEL_AREFB_Val _UINT8_(0x5) /* (ADC_REFCTRL) External Reference B */ 242 #define ADC_REFCTRL_REFSEL_AREFC_Val _UINT8_(0x6) /* (ADC_REFCTRL) External Reference C (only on ADC1) */ 243 #define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ 244 #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 AVDD Position */ 245 #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) AVDD Position */ 246 #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference A Position */ 247 #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference B Position */ 248 #define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference C (only on ADC1) Position */ 249 #define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ 250 #define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ 251 #define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assignment of value for REFCOMP in the ADC_REFCTRL register */ 252 #define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ 253 254 255 /* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ 256 #define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ 257 258 #define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ 259 #define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ 260 #define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assignment of value for SAMPLENUM in the ADC_AVGCTRL register */ 261 #define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ 262 #define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ 263 #define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ 264 #define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ 265 #define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ 266 #define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ 267 #define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ 268 #define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ 269 #define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ 270 #define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ 271 #define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ 272 #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ 273 #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ 274 #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ 275 #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ 276 #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ 277 #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ 278 #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ 279 #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ 280 #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ 281 #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ 282 #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ 283 #define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ 284 #define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ 285 #define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assignment of value for ADJRES in the ADC_AVGCTRL register */ 286 #define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ 287 288 289 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ 290 #define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ 291 292 #define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ 293 #define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ 294 #define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assignment of value for SAMPLEN in the ADC_SAMPCTRL register */ 295 #define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ 296 #define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ 297 #define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assignment of value for OFFCOMP in the ADC_SAMPCTRL register */ 298 #define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ 299 300 301 /* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ 302 #define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ 303 304 #define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ 305 #define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ 306 #define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_WINLT register */ 307 #define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ 308 309 310 /* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ 311 #define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ 312 313 #define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ 314 #define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ 315 #define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_WINUT register */ 316 #define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ 317 318 319 /* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ 320 #define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ 321 322 #define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ 323 #define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ 324 #define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_GAINCORR register */ 325 #define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ 326 327 328 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ 329 #define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ 330 331 #define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ 332 #define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ 333 #define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_OFFSETCORR register */ 334 #define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ 335 336 337 /* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ 338 #define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ 339 340 #define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Conversion Flush Position */ 341 #define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Conversion Flush Mask */ 342 #define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assignment of value for FLUSH in the ADC_SWTRIG register */ 343 #define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ 344 #define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ 345 #define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assignment of value for START in the ADC_SWTRIG register */ 346 #define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ 347 348 349 /* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ 350 #define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ 351 352 #define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ 353 #define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ 354 #define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENCLR register */ 355 #define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ 356 #define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ 357 #define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENCLR register */ 358 #define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ 359 #define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ 360 #define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENCLR register */ 361 #define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ 362 363 364 /* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ 365 #define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ 366 367 #define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ 368 #define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ 369 #define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENSET register */ 370 #define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ 371 #define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ 372 #define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENSET register */ 373 #define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ 374 #define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ 375 #define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENSET register */ 376 #define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ 377 378 379 /* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ 380 #define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 381 382 #define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ 383 #define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ 384 #define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTFLAG register */ 385 #define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ 386 #define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ 387 #define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTFLAG register */ 388 #define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ 389 #define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ 390 #define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTFLAG register */ 391 #define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ 392 393 394 /* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ 395 #define ADC_STATUS_RESETVALUE _UINT8_(0x00) /* (ADC_STATUS) Status Reset Value */ 396 397 #define ADC_STATUS_ADCBUSY_Pos _UINT8_(0) /* (ADC_STATUS) ADC Busy Status Position */ 398 #define ADC_STATUS_ADCBUSY_Msk (_UINT8_(0x1) << ADC_STATUS_ADCBUSY_Pos) /* (ADC_STATUS) ADC Busy Status Mask */ 399 #define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & (_UINT8_(value) << ADC_STATUS_ADCBUSY_Pos)) /* Assignment of value for ADCBUSY in the ADC_STATUS register */ 400 #define ADC_STATUS_WCC_Pos _UINT8_(2) /* (ADC_STATUS) Window Comparator Counter Position */ 401 #define ADC_STATUS_WCC_Msk (_UINT8_(0x3F) << ADC_STATUS_WCC_Pos) /* (ADC_STATUS) Window Comparator Counter Mask */ 402 #define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & (_UINT8_(value) << ADC_STATUS_WCC_Pos)) /* Assignment of value for WCC in the ADC_STATUS register */ 403 #define ADC_STATUS_Msk _UINT8_(0xFD) /* (ADC_STATUS) Register Mask */ 404 405 406 /* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ 407 #define ADC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ 408 409 #define ADC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ 410 #define ADC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ 411 #define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_SYNCBUSY register */ 412 #define ADC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ 413 #define ADC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ 414 #define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_SYNCBUSY register */ 415 #define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT32_(2) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ 416 #define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ 417 #define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assignment of value for INPUTCTRL in the ADC_SYNCBUSY register */ 418 #define ADC_SYNCBUSY_CTRLB_Pos _UINT32_(3) /* (ADC_SYNCBUSY) Control B Synchronization Busy Position */ 419 #define ADC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /* (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ 420 #define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << ADC_SYNCBUSY_CTRLB_Pos)) /* Assignment of value for CTRLB in the ADC_SYNCBUSY register */ 421 #define ADC_SYNCBUSY_REFCTRL_Pos _UINT32_(4) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ 422 #define ADC_SYNCBUSY_REFCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ 423 #define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_REFCTRL_Pos)) /* Assignment of value for REFCTRL in the ADC_SYNCBUSY register */ 424 #define ADC_SYNCBUSY_AVGCTRL_Pos _UINT32_(5) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ 425 #define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ 426 #define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assignment of value for AVGCTRL in the ADC_SYNCBUSY register */ 427 #define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT32_(6) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ 428 #define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ 429 #define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assignment of value for SAMPCTRL in the ADC_SYNCBUSY register */ 430 #define ADC_SYNCBUSY_WINLT_Pos _UINT32_(7) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ 431 #define ADC_SYNCBUSY_WINLT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ 432 #define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_SYNCBUSY register */ 433 #define ADC_SYNCBUSY_WINUT_Pos _UINT32_(8) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ 434 #define ADC_SYNCBUSY_WINUT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ 435 #define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_SYNCBUSY register */ 436 #define ADC_SYNCBUSY_GAINCORR_Pos _UINT32_(9) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ 437 #define ADC_SYNCBUSY_GAINCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ 438 #define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_SYNCBUSY register */ 439 #define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT32_(10) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ 440 #define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ 441 #define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_SYNCBUSY register */ 442 #define ADC_SYNCBUSY_SWTRIG_Pos _UINT32_(11) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ 443 #define ADC_SYNCBUSY_SWTRIG_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ 444 #define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assignment of value for SWTRIG in the ADC_SYNCBUSY register */ 445 #define ADC_SYNCBUSY_Msk _UINT32_(0x00000FFF) /* (ADC_SYNCBUSY) Register Mask */ 446 447 448 /* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ 449 #define ADC_DSEQDATA_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ 450 451 #define ADC_DSEQDATA_DATA_Pos _UINT32_(0) /* (ADC_DSEQDATA) DMA Sequential Data Position */ 452 #define ADC_DSEQDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /* (ADC_DSEQDATA) DMA Sequential Data Mask */ 453 #define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & (_UINT32_(value) << ADC_DSEQDATA_DATA_Pos)) /* Assignment of value for DATA in the ADC_DSEQDATA register */ 454 #define ADC_DSEQDATA_Msk _UINT32_(0xFFFFFFFF) /* (ADC_DSEQDATA) Register Mask */ 455 456 457 /* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ 458 #define ADC_DSEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ 459 460 #define ADC_DSEQCTRL_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQCTRL) Input Control Position */ 461 #define ADC_DSEQCTRL_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /* (ADC_DSEQCTRL) Input Control Mask */ 462 #define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) /* Assignment of value for INPUTCTRL in the ADC_DSEQCTRL register */ 463 #define ADC_DSEQCTRL_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQCTRL) Control B Position */ 464 #define ADC_DSEQCTRL_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /* (ADC_DSEQCTRL) Control B Mask */ 465 #define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQCTRL_CTRLB_Pos)) /* Assignment of value for CTRLB in the ADC_DSEQCTRL register */ 466 #define ADC_DSEQCTRL_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQCTRL) Reference Control Position */ 467 #define ADC_DSEQCTRL_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /* (ADC_DSEQCTRL) Reference Control Mask */ 468 #define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_REFCTRL_Pos)) /* Assignment of value for REFCTRL in the ADC_DSEQCTRL register */ 469 #define ADC_DSEQCTRL_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQCTRL) Average Control Position */ 470 #define ADC_DSEQCTRL_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /* (ADC_DSEQCTRL) Average Control Mask */ 471 #define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AVGCTRL_Pos)) /* Assignment of value for AVGCTRL in the ADC_DSEQCTRL register */ 472 #define ADC_DSEQCTRL_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQCTRL) Sampling Time Control Position */ 473 #define ADC_DSEQCTRL_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /* (ADC_DSEQCTRL) Sampling Time Control Mask */ 474 #define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) /* Assignment of value for SAMPCTRL in the ADC_DSEQCTRL register */ 475 #define ADC_DSEQCTRL_WINLT_Pos _UINT32_(5) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ 476 #define ADC_DSEQCTRL_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ 477 #define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_DSEQCTRL register */ 478 #define ADC_DSEQCTRL_WINUT_Pos _UINT32_(6) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ 479 #define ADC_DSEQCTRL_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ 480 #define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_DSEQCTRL register */ 481 #define ADC_DSEQCTRL_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQCTRL) Gain Correction Position */ 482 #define ADC_DSEQCTRL_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /* (ADC_DSEQCTRL) Gain Correction Mask */ 483 #define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_DSEQCTRL register */ 484 #define ADC_DSEQCTRL_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQCTRL) Offset Correction Position */ 485 #define ADC_DSEQCTRL_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /* (ADC_DSEQCTRL) Offset Correction Mask */ 486 #define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_DSEQCTRL register */ 487 #define ADC_DSEQCTRL_AUTOSTART_Pos _UINT32_(31) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ 488 #define ADC_DSEQCTRL_AUTOSTART_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ 489 #define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AUTOSTART_Pos)) /* Assignment of value for AUTOSTART in the ADC_DSEQCTRL register */ 490 #define ADC_DSEQCTRL_Msk _UINT32_(0x800001FF) /* (ADC_DSEQCTRL) Register Mask */ 491 492 493 /* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ 494 #define ADC_DSEQSTAT_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ 495 496 #define ADC_DSEQSTAT_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQSTAT) Input Control Position */ 497 #define ADC_DSEQSTAT_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /* (ADC_DSEQSTAT) Input Control Mask */ 498 #define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) /* Assignment of value for INPUTCTRL in the ADC_DSEQSTAT register */ 499 #define ADC_DSEQSTAT_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQSTAT) Control B Position */ 500 #define ADC_DSEQSTAT_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /* (ADC_DSEQSTAT) Control B Mask */ 501 #define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQSTAT_CTRLB_Pos)) /* Assignment of value for CTRLB in the ADC_DSEQSTAT register */ 502 #define ADC_DSEQSTAT_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQSTAT) Reference Control Position */ 503 #define ADC_DSEQSTAT_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /* (ADC_DSEQSTAT) Reference Control Mask */ 504 #define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_REFCTRL_Pos)) /* Assignment of value for REFCTRL in the ADC_DSEQSTAT register */ 505 #define ADC_DSEQSTAT_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQSTAT) Average Control Position */ 506 #define ADC_DSEQSTAT_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /* (ADC_DSEQSTAT) Average Control Mask */ 507 #define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_AVGCTRL_Pos)) /* Assignment of value for AVGCTRL in the ADC_DSEQSTAT register */ 508 #define ADC_DSEQSTAT_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQSTAT) Sampling Time Control Position */ 509 #define ADC_DSEQSTAT_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /* (ADC_DSEQSTAT) Sampling Time Control Mask */ 510 #define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) /* Assignment of value for SAMPCTRL in the ADC_DSEQSTAT register */ 511 #define ADC_DSEQSTAT_WINLT_Pos _UINT32_(5) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ 512 #define ADC_DSEQSTAT_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ 513 #define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_DSEQSTAT register */ 514 #define ADC_DSEQSTAT_WINUT_Pos _UINT32_(6) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ 515 #define ADC_DSEQSTAT_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ 516 #define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_DSEQSTAT register */ 517 #define ADC_DSEQSTAT_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQSTAT) Gain Correction Position */ 518 #define ADC_DSEQSTAT_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /* (ADC_DSEQSTAT) Gain Correction Mask */ 519 #define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_DSEQSTAT register */ 520 #define ADC_DSEQSTAT_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQSTAT) Offset Correction Position */ 521 #define ADC_DSEQSTAT_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /* (ADC_DSEQSTAT) Offset Correction Mask */ 522 #define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_DSEQSTAT register */ 523 #define ADC_DSEQSTAT_BUSY_Pos _UINT32_(31) /* (ADC_DSEQSTAT) DMA Sequencing Busy Position */ 524 #define ADC_DSEQSTAT_BUSY_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /* (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ 525 #define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & (_UINT32_(value) << ADC_DSEQSTAT_BUSY_Pos)) /* Assignment of value for BUSY in the ADC_DSEQSTAT register */ 526 #define ADC_DSEQSTAT_Msk _UINT32_(0x800001FF) /* (ADC_DSEQSTAT) Register Mask */ 527 528 529 /* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ 530 #define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Conversion Value Reset Value */ 531 532 #define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Conversion Value Position */ 533 #define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Conversion Value Mask */ 534 #define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assignment of value for RESULT in the ADC_RESULT register */ 535 #define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ 536 537 538 /* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ 539 #define ADC_RESS_RESETVALUE _UINT16_(0x00) /* (ADC_RESS) Last Sample Result Reset Value */ 540 541 #define ADC_RESS_RESS_Pos _UINT16_(0) /* (ADC_RESS) Last ADC conversion result Position */ 542 #define ADC_RESS_RESS_Msk (_UINT16_(0xFFFF) << ADC_RESS_RESS_Pos) /* (ADC_RESS) Last ADC conversion result Mask */ 543 #define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & (_UINT16_(value) << ADC_RESS_RESS_Pos)) /* Assignment of value for RESS in the ADC_RESS register */ 544 #define ADC_RESS_Msk _UINT16_(0xFFFF) /* (ADC_RESS) Register Mask */ 545 546 547 /* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ 548 #define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ 549 550 #define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ 551 #define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ 552 #define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assignment of value for BIASCOMP in the ADC_CALIB register */ 553 #define ADC_CALIB_BIASR2R_Pos _UINT16_(4) /* (ADC_CALIB) Bias R2R Ampli scaling Position */ 554 #define ADC_CALIB_BIASR2R_Msk (_UINT16_(0x7) << ADC_CALIB_BIASR2R_Pos) /* (ADC_CALIB) Bias R2R Ampli scaling Mask */ 555 #define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & (_UINT16_(value) << ADC_CALIB_BIASR2R_Pos)) /* Assignment of value for BIASR2R in the ADC_CALIB register */ 556 #define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ 557 #define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ 558 #define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assignment of value for BIASREFBUF in the ADC_CALIB register */ 559 #define ADC_CALIB_Msk _UINT16_(0x0777) /* (ADC_CALIB) Register Mask */ 560 561 562 /* ADC register offsets definitions */ 563 #define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ 564 #define ADC_EVCTRL_REG_OFST _UINT32_(0x02) /* (ADC_EVCTRL) Event Control Offset */ 565 #define ADC_DBGCTRL_REG_OFST _UINT32_(0x03) /* (ADC_DBGCTRL) Debug Control Offset */ 566 #define ADC_INPUTCTRL_REG_OFST _UINT32_(0x04) /* (ADC_INPUTCTRL) Input Control Offset */ 567 #define ADC_CTRLB_REG_OFST _UINT32_(0x06) /* (ADC_CTRLB) Control B Offset */ 568 #define ADC_REFCTRL_REG_OFST _UINT32_(0x08) /* (ADC_REFCTRL) Reference Control Offset */ 569 #define ADC_AVGCTRL_REG_OFST _UINT32_(0x0A) /* (ADC_AVGCTRL) Average Control Offset */ 570 #define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0B) /* (ADC_SAMPCTRL) Sample Time Control Offset */ 571 #define ADC_WINLT_REG_OFST _UINT32_(0x0C) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ 572 #define ADC_WINUT_REG_OFST _UINT32_(0x0E) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ 573 #define ADC_GAINCORR_REG_OFST _UINT32_(0x10) /* (ADC_GAINCORR) Gain Correction Offset */ 574 #define ADC_OFFSETCORR_REG_OFST _UINT32_(0x12) /* (ADC_OFFSETCORR) Offset Correction Offset */ 575 #define ADC_SWTRIG_REG_OFST _UINT32_(0x14) /* (ADC_SWTRIG) Software Trigger Offset */ 576 #define ADC_INTENCLR_REG_OFST _UINT32_(0x2C) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ 577 #define ADC_INTENSET_REG_OFST _UINT32_(0x2D) /* (ADC_INTENSET) Interrupt Enable Set Offset */ 578 #define ADC_INTFLAG_REG_OFST _UINT32_(0x2E) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ 579 #define ADC_STATUS_REG_OFST _UINT32_(0x2F) /* (ADC_STATUS) Status Offset */ 580 #define ADC_SYNCBUSY_REG_OFST _UINT32_(0x30) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ 581 #define ADC_DSEQDATA_REG_OFST _UINT32_(0x34) /* (ADC_DSEQDATA) DMA Sequencial Data Offset */ 582 #define ADC_DSEQCTRL_REG_OFST _UINT32_(0x38) /* (ADC_DSEQCTRL) DMA Sequential Control Offset */ 583 #define ADC_DSEQSTAT_REG_OFST _UINT32_(0x3C) /* (ADC_DSEQSTAT) DMA Sequencial Status Offset */ 584 #define ADC_RESULT_REG_OFST _UINT32_(0x40) /* (ADC_RESULT) Result Conversion Value Offset */ 585 #define ADC_RESS_REG_OFST _UINT32_(0x44) /* (ADC_RESS) Last Sample Result Offset */ 586 #define ADC_CALIB_REG_OFST _UINT32_(0x48) /* (ADC_CALIB) Calibration Offset */ 587 588 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 589 /* ADC register API structure */ 590 typedef struct 591 { /* Analog Digital Converter */ 592 __IO uint16_t ADC_CTRLA; /* Offset: 0x00 (R/W 16) Control A */ 593 __IO uint8_t ADC_EVCTRL; /* Offset: 0x02 (R/W 8) Event Control */ 594 __IO uint8_t ADC_DBGCTRL; /* Offset: 0x03 (R/W 8) Debug Control */ 595 __IO uint16_t ADC_INPUTCTRL; /* Offset: 0x04 (R/W 16) Input Control */ 596 __IO uint16_t ADC_CTRLB; /* Offset: 0x06 (R/W 16) Control B */ 597 __IO uint8_t ADC_REFCTRL; /* Offset: 0x08 (R/W 8) Reference Control */ 598 __I uint8_t Reserved1[0x01]; 599 __IO uint8_t ADC_AVGCTRL; /* Offset: 0x0A (R/W 8) Average Control */ 600 __IO uint8_t ADC_SAMPCTRL; /* Offset: 0x0B (R/W 8) Sample Time Control */ 601 __IO uint16_t ADC_WINLT; /* Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ 602 __IO uint16_t ADC_WINUT; /* Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ 603 __IO uint16_t ADC_GAINCORR; /* Offset: 0x10 (R/W 16) Gain Correction */ 604 __IO uint16_t ADC_OFFSETCORR; /* Offset: 0x12 (R/W 16) Offset Correction */ 605 __IO uint8_t ADC_SWTRIG; /* Offset: 0x14 (R/W 8) Software Trigger */ 606 __I uint8_t Reserved2[0x17]; 607 __IO uint8_t ADC_INTENCLR; /* Offset: 0x2C (R/W 8) Interrupt Enable Clear */ 608 __IO uint8_t ADC_INTENSET; /* Offset: 0x2D (R/W 8) Interrupt Enable Set */ 609 __IO uint8_t ADC_INTFLAG; /* Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ 610 __I uint8_t ADC_STATUS; /* Offset: 0x2F (R/ 8) Status */ 611 __I uint32_t ADC_SYNCBUSY; /* Offset: 0x30 (R/ 32) Synchronization Busy */ 612 __O uint32_t ADC_DSEQDATA; /* Offset: 0x34 ( /W 32) DMA Sequencial Data */ 613 __IO uint32_t ADC_DSEQCTRL; /* Offset: 0x38 (R/W 32) DMA Sequential Control */ 614 __I uint32_t ADC_DSEQSTAT; /* Offset: 0x3C (R/ 32) DMA Sequencial Status */ 615 __I uint16_t ADC_RESULT; /* Offset: 0x40 (R/ 16) Result Conversion Value */ 616 __I uint8_t Reserved3[0x02]; 617 __I uint16_t ADC_RESS; /* Offset: 0x44 (R/ 16) Last Sample Result */ 618 __I uint8_t Reserved4[0x02]; 619 __IO uint16_t ADC_CALIB; /* Offset: 0x48 (R/W 16) Calibration */ 620 } adc_registers_t; 621 622 623 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 624 #endif /* _PIC32CXSG41_ADC_COMPONENT_H_ */ 625
