1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_WDT_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_WDT_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for WDT peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ 13 #define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ 14 #define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ 15 #define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ 16 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ 17 #define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ 18 #define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ 19 #define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ 20 #else 21 #define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ 22 #define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ 23 #define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ 24 #define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ 25 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ 26 #define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ 27 #define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ 28 #define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ 29 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 30 31 #endif /* _MICROCHIP_PIC32CXSG_WDT_INSTANCE_FIXUP_H_ */ 32
