1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TCC4_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TCC4_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for TCC4 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_TCC4_CTRLA (0x43001000) /**< \brief (TCC4) Control A */ 13 #define REG_TCC4_CTRLBCLR (0x43001004) /**< \brief (TCC4) Control B Clear */ 14 #define REG_TCC4_CTRLBSET (0x43001005) /**< \brief (TCC4) Control B Set */ 15 #define REG_TCC4_SYNCBUSY (0x43001008) /**< \brief (TCC4) Synchronization Busy */ 16 #define REG_TCC4_FCTRLA (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */ 17 #define REG_TCC4_FCTRLB (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */ 18 #define REG_TCC4_DRVCTRL (0x43001018) /**< \brief (TCC4) Driver Control */ 19 #define REG_TCC4_DBGCTRL (0x4300101E) /**< \brief (TCC4) Debug Control */ 20 #define REG_TCC4_EVCTRL (0x43001020) /**< \brief (TCC4) Event Control */ 21 #define REG_TCC4_INTENCLR (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */ 22 #define REG_TCC4_INTENSET (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */ 23 #define REG_TCC4_INTFLAG (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */ 24 #define REG_TCC4_STATUS (0x43001030) /**< \brief (TCC4) Status */ 25 #define REG_TCC4_COUNT (0x43001034) /**< \brief (TCC4) Count */ 26 #define REG_TCC4_WAVE (0x4300103C) /**< \brief (TCC4) Waveform Control */ 27 #define REG_TCC4_PER (0x43001040) /**< \brief (TCC4) Period */ 28 #define REG_TCC4_CC0 (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */ 29 #define REG_TCC4_CC1 (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */ 30 #define REG_TCC4_PERBUF (0x4300106C) /**< \brief (TCC4) Period Buffer */ 31 #define REG_TCC4_CCBUF0 (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */ 32 #define REG_TCC4_CCBUF1 (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */ 33 #else 34 #define REG_TCC4_CTRLA (*(RwReg *)0x43001000UL) /**< \brief (TCC4) Control A */ 35 #define REG_TCC4_CTRLBCLR (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */ 36 #define REG_TCC4_CTRLBSET (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */ 37 #define REG_TCC4_SYNCBUSY (*(RoReg *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */ 38 #define REG_TCC4_FCTRLA (*(RwReg *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */ 39 #define REG_TCC4_FCTRLB (*(RwReg *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */ 40 #define REG_TCC4_DRVCTRL (*(RwReg *)0x43001018UL) /**< \brief (TCC4) Driver Control */ 41 #define REG_TCC4_DBGCTRL (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */ 42 #define REG_TCC4_EVCTRL (*(RwReg *)0x43001020UL) /**< \brief (TCC4) Event Control */ 43 #define REG_TCC4_INTENCLR (*(RwReg *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */ 44 #define REG_TCC4_INTENSET (*(RwReg *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */ 45 #define REG_TCC4_INTFLAG (*(RwReg *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */ 46 #define REG_TCC4_STATUS (*(RwReg *)0x43001030UL) /**< \brief (TCC4) Status */ 47 #define REG_TCC4_COUNT (*(RwReg *)0x43001034UL) /**< \brief (TCC4) Count */ 48 #define REG_TCC4_WAVE (*(RwReg *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */ 49 #define REG_TCC4_PER (*(RwReg *)0x43001040UL) /**< \brief (TCC4) Period */ 50 #define REG_TCC4_CC0 (*(RwReg *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */ 51 #define REG_TCC4_CC1 (*(RwReg *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */ 52 #define REG_TCC4_PERBUF (*(RwReg *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */ 53 #define REG_TCC4_CCBUF0 (*(RwReg *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */ 54 #define REG_TCC4_CCBUF1 (*(RwReg *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */ 55 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 #endif /* _MICROCHIP_PIC32CXSG_TCC4_INSTANCE_FIXUP_H_ */ 58
