1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TCC1_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TCC1_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for TCC1 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_TCC1_CTRLA (0x41018000) /**< \brief (TCC1) Control A */ 13 #define REG_TCC1_CTRLBCLR (0x41018004) /**< \brief (TCC1) Control B Clear */ 14 #define REG_TCC1_CTRLBSET (0x41018005) /**< \brief (TCC1) Control B Set */ 15 #define REG_TCC1_SYNCBUSY (0x41018008) /**< \brief (TCC1) Synchronization Busy */ 16 #define REG_TCC1_FCTRLA (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */ 17 #define REG_TCC1_FCTRLB (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */ 18 #define REG_TCC1_WEXCTRL (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */ 19 #define REG_TCC1_DRVCTRL (0x41018018) /**< \brief (TCC1) Driver Control */ 20 #define REG_TCC1_DBGCTRL (0x4101801E) /**< \brief (TCC1) Debug Control */ 21 #define REG_TCC1_EVCTRL (0x41018020) /**< \brief (TCC1) Event Control */ 22 #define REG_TCC1_INTENCLR (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */ 23 #define REG_TCC1_INTENSET (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */ 24 #define REG_TCC1_INTFLAG (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 25 #define REG_TCC1_STATUS (0x41018030) /**< \brief (TCC1) Status */ 26 #define REG_TCC1_COUNT (0x41018034) /**< \brief (TCC1) Count */ 27 #define REG_TCC1_PATT (0x41018038) /**< \brief (TCC1) Pattern */ 28 #define REG_TCC1_WAVE (0x4101803C) /**< \brief (TCC1) Waveform Control */ 29 #define REG_TCC1_PER (0x41018040) /**< \brief (TCC1) Period */ 30 #define REG_TCC1_CC0 (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */ 31 #define REG_TCC1_CC1 (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */ 32 #define REG_TCC1_CC2 (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */ 33 #define REG_TCC1_CC3 (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */ 34 #define REG_TCC1_PATTBUF (0x41018064) /**< \brief (TCC1) Pattern Buffer */ 35 #define REG_TCC1_PERBUF (0x4101806C) /**< \brief (TCC1) Period Buffer */ 36 #define REG_TCC1_CCBUF0 (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 37 #define REG_TCC1_CCBUF1 (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 38 #define REG_TCC1_CCBUF2 (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */ 39 #define REG_TCC1_CCBUF3 (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */ 40 #else 41 #define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) /**< \brief (TCC1) Control A */ 42 #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */ 43 #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */ 44 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */ 45 #define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */ 46 #define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */ 47 #define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */ 48 #define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) /**< \brief (TCC1) Driver Control */ 49 #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */ 50 #define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) /**< \brief (TCC1) Event Control */ 51 #define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */ 52 #define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */ 53 #define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 54 #define REG_TCC1_STATUS (*(RwReg *)0x41018030UL) /**< \brief (TCC1) Status */ 55 #define REG_TCC1_COUNT (*(RwReg *)0x41018034UL) /**< \brief (TCC1) Count */ 56 #define REG_TCC1_PATT (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */ 57 #define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */ 58 #define REG_TCC1_PER (*(RwReg *)0x41018040UL) /**< \brief (TCC1) Period */ 59 #define REG_TCC1_CC0 (*(RwReg *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */ 60 #define REG_TCC1_CC1 (*(RwReg *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */ 61 #define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */ 62 #define REG_TCC1_CC3 (*(RwReg *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */ 63 #define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */ 64 #define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */ 65 #define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 66 #define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 67 #define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */ 68 #define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */ 69 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #endif /* _MICROCHIP_PIC32CXSG_TCC1_INSTANCE_FIXUP_H_ */ 72
