1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TCC0_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TCC0_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for TCC0 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_TCC0_CTRLA (0x41016000) /**< \brief (TCC0) Control A */ 13 #define REG_TCC0_CTRLBCLR (0x41016004) /**< \brief (TCC0) Control B Clear */ 14 #define REG_TCC0_CTRLBSET (0x41016005) /**< \brief (TCC0) Control B Set */ 15 #define REG_TCC0_SYNCBUSY (0x41016008) /**< \brief (TCC0) Synchronization Busy */ 16 #define REG_TCC0_FCTRLA (0x4101600C) /**< \brief (TCC0) Recoverable Fault A Configuration */ 17 #define REG_TCC0_FCTRLB (0x41016010) /**< \brief (TCC0) Recoverable Fault B Configuration */ 18 #define REG_TCC0_WEXCTRL (0x41016014) /**< \brief (TCC0) Waveform Extension Configuration */ 19 #define REG_TCC0_DRVCTRL (0x41016018) /**< \brief (TCC0) Driver Control */ 20 #define REG_TCC0_DBGCTRL (0x4101601E) /**< \brief (TCC0) Debug Control */ 21 #define REG_TCC0_EVCTRL (0x41016020) /**< \brief (TCC0) Event Control */ 22 #define REG_TCC0_INTENCLR (0x41016024) /**< \brief (TCC0) Interrupt Enable Clear */ 23 #define REG_TCC0_INTENSET (0x41016028) /**< \brief (TCC0) Interrupt Enable Set */ 24 #define REG_TCC0_INTFLAG (0x4101602C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ 25 #define REG_TCC0_STATUS (0x41016030) /**< \brief (TCC0) Status */ 26 #define REG_TCC0_COUNT (0x41016034) /**< \brief (TCC0) Count */ 27 #define REG_TCC0_PATT (0x41016038) /**< \brief (TCC0) Pattern */ 28 #define REG_TCC0_WAVE (0x4101603C) /**< \brief (TCC0) Waveform Control */ 29 #define REG_TCC0_PER (0x41016040) /**< \brief (TCC0) Period */ 30 #define REG_TCC0_CC0 (0x41016044) /**< \brief (TCC0) Compare and Capture 0 */ 31 #define REG_TCC0_CC1 (0x41016048) /**< \brief (TCC0) Compare and Capture 1 */ 32 #define REG_TCC0_CC2 (0x4101604C) /**< \brief (TCC0) Compare and Capture 2 */ 33 #define REG_TCC0_CC3 (0x41016050) /**< \brief (TCC0) Compare and Capture 3 */ 34 #define REG_TCC0_CC4 (0x41016054) /**< \brief (TCC0) Compare and Capture 4 */ 35 #define REG_TCC0_CC5 (0x41016058) /**< \brief (TCC0) Compare and Capture 5 */ 36 #define REG_TCC0_PATTBUF (0x41016064) /**< \brief (TCC0) Pattern Buffer */ 37 #define REG_TCC0_PERBUF (0x4101606C) /**< \brief (TCC0) Period Buffer */ 38 #define REG_TCC0_CCBUF0 (0x41016070) /**< \brief (TCC0) Compare and Capture Buffer 0 */ 39 #define REG_TCC0_CCBUF1 (0x41016074) /**< \brief (TCC0) Compare and Capture Buffer 1 */ 40 #define REG_TCC0_CCBUF2 (0x41016078) /**< \brief (TCC0) Compare and Capture Buffer 2 */ 41 #define REG_TCC0_CCBUF3 (0x4101607C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ 42 #define REG_TCC0_CCBUF4 (0x41016080) /**< \brief (TCC0) Compare and Capture Buffer 4 */ 43 #define REG_TCC0_CCBUF5 (0x41016084) /**< \brief (TCC0) Compare and Capture Buffer 5 */ 44 #else 45 #define REG_TCC0_CTRLA (*(RwReg *)0x41016000UL) /**< \brief (TCC0) Control A */ 46 #define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x41016004UL) /**< \brief (TCC0) Control B Clear */ 47 #define REG_TCC0_CTRLBSET (*(RwReg8 *)0x41016005UL) /**< \brief (TCC0) Control B Set */ 48 #define REG_TCC0_SYNCBUSY (*(RoReg *)0x41016008UL) /**< \brief (TCC0) Synchronization Busy */ 49 #define REG_TCC0_FCTRLA (*(RwReg *)0x4101600CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ 50 #define REG_TCC0_FCTRLB (*(RwReg *)0x41016010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ 51 #define REG_TCC0_WEXCTRL (*(RwReg *)0x41016014UL) /**< \brief (TCC0) Waveform Extension Configuration */ 52 #define REG_TCC0_DRVCTRL (*(RwReg *)0x41016018UL) /**< \brief (TCC0) Driver Control */ 53 #define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4101601EUL) /**< \brief (TCC0) Debug Control */ 54 #define REG_TCC0_EVCTRL (*(RwReg *)0x41016020UL) /**< \brief (TCC0) Event Control */ 55 #define REG_TCC0_INTENCLR (*(RwReg *)0x41016024UL) /**< \brief (TCC0) Interrupt Enable Clear */ 56 #define REG_TCC0_INTENSET (*(RwReg *)0x41016028UL) /**< \brief (TCC0) Interrupt Enable Set */ 57 #define REG_TCC0_INTFLAG (*(RwReg *)0x4101602CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ 58 #define REG_TCC0_STATUS (*(RwReg *)0x41016030UL) /**< \brief (TCC0) Status */ 59 #define REG_TCC0_COUNT (*(RwReg *)0x41016034UL) /**< \brief (TCC0) Count */ 60 #define REG_TCC0_PATT (*(RwReg16*)0x41016038UL) /**< \brief (TCC0) Pattern */ 61 #define REG_TCC0_WAVE (*(RwReg *)0x4101603CUL) /**< \brief (TCC0) Waveform Control */ 62 #define REG_TCC0_PER (*(RwReg *)0x41016040UL) /**< \brief (TCC0) Period */ 63 #define REG_TCC0_CC0 (*(RwReg *)0x41016044UL) /**< \brief (TCC0) Compare and Capture 0 */ 64 #define REG_TCC0_CC1 (*(RwReg *)0x41016048UL) /**< \brief (TCC0) Compare and Capture 1 */ 65 #define REG_TCC0_CC2 (*(RwReg *)0x4101604CUL) /**< \brief (TCC0) Compare and Capture 2 */ 66 #define REG_TCC0_CC3 (*(RwReg *)0x41016050UL) /**< \brief (TCC0) Compare and Capture 3 */ 67 #define REG_TCC0_CC4 (*(RwReg *)0x41016054UL) /**< \brief (TCC0) Compare and Capture 4 */ 68 #define REG_TCC0_CC5 (*(RwReg *)0x41016058UL) /**< \brief (TCC0) Compare and Capture 5 */ 69 #define REG_TCC0_PATTBUF (*(RwReg16*)0x41016064UL) /**< \brief (TCC0) Pattern Buffer */ 70 #define REG_TCC0_PERBUF (*(RwReg *)0x4101606CUL) /**< \brief (TCC0) Period Buffer */ 71 #define REG_TCC0_CCBUF0 (*(RwReg *)0x41016070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ 72 #define REG_TCC0_CCBUF1 (*(RwReg *)0x41016074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ 73 #define REG_TCC0_CCBUF2 (*(RwReg *)0x41016078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ 74 #define REG_TCC0_CCBUF3 (*(RwReg *)0x4101607CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ 75 #define REG_TCC0_CCBUF4 (*(RwReg *)0x41016080UL) /**< \brief (TCC0) Compare and Capture Buffer 4 */ 76 #define REG_TCC0_CCBUF5 (*(RwReg *)0x41016084UL) /**< \brief (TCC0) Compare and Capture Buffer 5 */ 77 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #endif /* _MICROCHIP_PIC32CXSG_TCC0_INSTANCE_FIXUP_H_ */ 80
