1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TC0_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TC0_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for TC0 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_TC0_CTRLA (0x40003800) /**< \brief (TC0) Control A */ 13 #define REG_TC0_CTRLBCLR (0x40003804) /**< \brief (TC0) Control B Clear */ 14 #define REG_TC0_CTRLBSET (0x40003805) /**< \brief (TC0) Control B Set */ 15 #define REG_TC0_EVCTRL (0x40003806) /**< \brief (TC0) Event Control */ 16 #define REG_TC0_INTENCLR (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */ 17 #define REG_TC0_INTENSET (0x40003809) /**< \brief (TC0) Interrupt Enable Set */ 18 #define REG_TC0_INTFLAG (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */ 19 #define REG_TC0_STATUS (0x4000380B) /**< \brief (TC0) Status */ 20 #define REG_TC0_WAVE (0x4000380C) /**< \brief (TC0) Waveform Generation Control */ 21 #define REG_TC0_DRVCTRL (0x4000380D) /**< \brief (TC0) Control C */ 22 #define REG_TC0_DBGCTRL (0x4000380F) /**< \brief (TC0) Debug Control */ 23 #define REG_TC0_SYNCBUSY (0x40003810) /**< \brief (TC0) Synchronization Status */ 24 #define REG_TC0_COUNT16_COUNT (0x40003814) /**< \brief (TC0) COUNT16 Count */ 25 #define REG_TC0_COUNT16_CC0 (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 26 #define REG_TC0_COUNT16_CC1 (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 27 #define REG_TC0_COUNT16_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 28 #define REG_TC0_COUNT16_CCBUF1 (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 29 #define REG_TC0_COUNT32_COUNT (0x40003814) /**< \brief (TC0) COUNT32 Count */ 30 #define REG_TC0_COUNT32_CC0 (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 31 #define REG_TC0_COUNT32_CC1 (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 32 #define REG_TC0_COUNT32_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 33 #define REG_TC0_COUNT32_CCBUF1 (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 34 #define REG_TC0_COUNT8_COUNT (0x40003814) /**< \brief (TC0) COUNT8 Count */ 35 #define REG_TC0_COUNT8_PER (0x4000381B) /**< \brief (TC0) COUNT8 Period */ 36 #define REG_TC0_COUNT8_CC0 (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 37 #define REG_TC0_COUNT8_CC1 (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 38 #define REG_TC0_COUNT8_PERBUF (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */ 39 #define REG_TC0_COUNT8_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 40 #define REG_TC0_COUNT8_CCBUF1 (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 41 #else 42 #define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) /**< \brief (TC0) Control A */ 43 #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */ 44 #define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */ 45 #define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */ 46 #define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */ 47 #define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */ 48 #define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ 49 #define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */ 50 #define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */ 51 #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */ 52 #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */ 53 #define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) /**< \brief (TC0) Synchronization Status */ 54 #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */ 55 #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 56 #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 57 #define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 58 #define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 59 #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */ 60 #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 61 #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 62 #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 63 #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 64 #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */ 65 #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */ 66 #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 67 #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 68 #define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */ 69 #define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 70 #define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 71 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #endif /* _MICROCHIP_PIC32CXSG_TC0_INSTANCE_FIXUP_H_ */ 74
