1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_SERCOM1_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_SERCOM1_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for SERCOM1 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_SERCOM1_I2CM_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CM Control A */ 13 #define REG_SERCOM1_I2CM_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CM Control B */ 14 #define REG_SERCOM1_I2CM_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CM Control C */ 15 #define REG_SERCOM1_I2CM_BAUD (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */ 16 #define REG_SERCOM1_I2CM_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 17 #define REG_SERCOM1_I2CM_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 18 #define REG_SERCOM1_I2CM_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 19 #define REG_SERCOM1_I2CM_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CM Status */ 20 #define REG_SERCOM1_I2CM_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */ 21 #define REG_SERCOM1_I2CM_ADDR (0x40003424) /**< \brief (SERCOM1) I2CM Address */ 22 #define REG_SERCOM1_I2CM_DATA (0x40003428) /**< \brief (SERCOM1) I2CM Data */ 23 #define REG_SERCOM1_I2CM_DBGCTRL (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */ 24 #define REG_SERCOM1_I2CS_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CS Control A */ 25 #define REG_SERCOM1_I2CS_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CS Control B */ 26 #define REG_SERCOM1_I2CS_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CS Control C */ 27 #define REG_SERCOM1_I2CS_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 28 #define REG_SERCOM1_I2CS_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 29 #define REG_SERCOM1_I2CS_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 30 #define REG_SERCOM1_I2CS_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CS Status */ 31 #define REG_SERCOM1_I2CS_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */ 32 #define REG_SERCOM1_I2CS_LENGTH (0x40003422) /**< \brief (SERCOM1) I2CS Length */ 33 #define REG_SERCOM1_I2CS_ADDR (0x40003424) /**< \brief (SERCOM1) I2CS Address */ 34 #define REG_SERCOM1_I2CS_DATA (0x40003428) /**< \brief (SERCOM1) I2CS Data */ 35 #define REG_SERCOM1_SPI_CTRLA (0x40003400) /**< \brief (SERCOM1) SPI Control A */ 36 #define REG_SERCOM1_SPI_CTRLB (0x40003404) /**< \brief (SERCOM1) SPI Control B */ 37 #define REG_SERCOM1_SPI_CTRLC (0x40003408) /**< \brief (SERCOM1) SPI Control C */ 38 #define REG_SERCOM1_SPI_BAUD (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */ 39 #define REG_SERCOM1_SPI_INTENCLR (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 40 #define REG_SERCOM1_SPI_INTENSET (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 41 #define REG_SERCOM1_SPI_INTFLAG (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 42 #define REG_SERCOM1_SPI_STATUS (0x4000341A) /**< \brief (SERCOM1) SPI Status */ 43 #define REG_SERCOM1_SPI_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */ 44 #define REG_SERCOM1_SPI_LENGTH (0x40003422) /**< \brief (SERCOM1) SPI Length */ 45 #define REG_SERCOM1_SPI_ADDR (0x40003424) /**< \brief (SERCOM1) SPI Address */ 46 #define REG_SERCOM1_SPI_DATA (0x40003428) /**< \brief (SERCOM1) SPI Data */ 47 #define REG_SERCOM1_SPI_DBGCTRL (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */ 48 #define REG_SERCOM1_USART_CTRLA (0x40003400) /**< \brief (SERCOM1) USART Control A */ 49 #define REG_SERCOM1_USART_CTRLB (0x40003404) /**< \brief (SERCOM1) USART Control B */ 50 #define REG_SERCOM1_USART_CTRLC (0x40003408) /**< \brief (SERCOM1) USART Control C */ 51 #define REG_SERCOM1_USART_BAUD (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */ 52 #define REG_SERCOM1_USART_RXPL (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */ 53 #define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 54 #define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 55 #define REG_SERCOM1_USART_INTFLAG (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 56 #define REG_SERCOM1_USART_STATUS (0x4000341A) /**< \brief (SERCOM1) USART Status */ 57 #define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */ 58 #define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */ 59 #define REG_SERCOM1_USART_LENGTH (0x40003422) /**< \brief (SERCOM1) USART Length */ 60 #define REG_SERCOM1_USART_DATA (0x40003428) /**< \brief (SERCOM1) USART Data */ 61 #define REG_SERCOM1_USART_DBGCTRL (0x40003430) /**< \brief (SERCOM1) USART Debug Control */ 62 #else 63 #define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */ 64 #define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */ 65 #define REG_SERCOM1_I2CM_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */ 66 #define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ 67 #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 68 #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 69 #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 70 #define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */ 71 #define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */ 72 #define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */ 73 #define REG_SERCOM1_I2CM_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */ 74 #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */ 75 #define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */ 76 #define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */ 77 #define REG_SERCOM1_I2CS_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */ 78 #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 79 #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 80 #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 81 #define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */ 82 #define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */ 83 #define REG_SERCOM1_I2CS_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */ 84 #define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */ 85 #define REG_SERCOM1_I2CS_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */ 86 #define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */ 87 #define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */ 88 #define REG_SERCOM1_SPI_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */ 89 #define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */ 90 #define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 91 #define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 92 #define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 93 #define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */ 94 #define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */ 95 #define REG_SERCOM1_SPI_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */ 96 #define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */ 97 #define REG_SERCOM1_SPI_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */ 98 #define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */ 99 #define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */ 100 #define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */ 101 #define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */ 102 #define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */ 103 #define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ 104 #define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 105 #define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 106 #define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 107 #define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */ 108 #define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */ 109 #define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */ 110 #define REG_SERCOM1_USART_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */ 111 #define REG_SERCOM1_USART_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) USART Data */ 112 #define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */ 113 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 /* ========== Instance Parameter definitions for SERCOM1 peripheral ========== */ 116 #define SERCOM1_CLK_REDUCTION (1) /* Reduce clock options to pin 1 for SPI and USART */ 117 #define SERCOM1_DLY_COMPENSATION (1) /* Compensates for a fast DLY50 element. Assuming 20ns */ 118 #define SERCOM1_DMA (1) /* DMA support implemented? */ 119 #define SERCOM1_DMAC_ID_RX (6) /* Index of DMA RX trigger */ 120 #define SERCOM1_DMAC_ID_TX (7) /* Index of DMA TX trigger */ 121 #define SERCOM1_FIFO_DEPTH_POWER (1) /* 2^FIFO_DEPTH_POWER gives rx FIFO depth. */ 122 #define SERCOM1_GCLK_ID_CORE (8) 123 #define SERCOM1_GCLK_ID_SLOW (3) 124 #define SERCOM1_I2CM (1) /* I2C Master mode implemented? */ 125 #define SERCOM1_I2CS (1) /* I2C Slave mode implemented? */ 126 #define SERCOM1_I2CS_AUTO_ACK (1) /* I2C slave automatic acknowledge implemented? */ 127 #define SERCOM1_I2CS_GROUP_CMD (1) /* I2C slave group command implemented? */ 128 #define SERCOM1_I2CS_SDASETUP_CNT_SIZE (8) /* I2CS sda setup count size */ 129 #define SERCOM1_I2CS_SDASETUP_SIZE (4) /* I2CS sda setup size */ 130 #define SERCOM1_I2CS_SUDAT (1) /* I2C slave SDA setup implemented? */ 131 #define SERCOM1_I2C_0_INT_SRC (50) /* I2C 0 Interrupt */ 132 #define SERCOM1_I2C_1_INT_SRC (51) /* I2C 1 Interrupt */ 133 #define SERCOM1_I2C_2_INT_SRC (52) /* I2C 2 Interrupt */ 134 #define SERCOM1_I2C_3_INT_SRC (53) /* I2C 3 Interrupt */ 135 #define SERCOM1_I2C_FASTMP (1) /* I2C fast mode plus implemented? */ 136 #define SERCOM1_I2C_HSMODE (1) /* USART mode implemented? */ 137 #define SERCOM1_I2C_SCLSM_MODE (1) /* I2C SCL clock stretch mode implemented? */ 138 #define SERCOM1_I2C_SMB_TIMEOUTS (1) /* I2C SMBus timeouts implemented? */ 139 #define SERCOM1_I2C_TENBIT_ADR (1) /* I2C ten bit enabled? */ 140 #define SERCOM1_INSTANCE_ID (13) /* Instance index for SERCOM1 */ 141 #define SERCOM1_INT_MSB (6) 142 #define SERCOM1_PMSB (3) 143 #define SERCOM1_RETENTION_SUPPORT (0) /* Retention supported? */ 144 #define SERCOM1_SE_CNT (1) /* SE counter included? */ 145 #define SERCOM1_SPI (1) /* SPI mode implemented? */ 146 #define SERCOM1_SPI_ERROR_INT_SRC (53) /* SPI ERROR Interrupt */ 147 #define SERCOM1_SPI_HW_SS_CTRL (1) /* Master _SS hardware control implemented? */ 148 #define SERCOM1_SPI_ICSPACE_EXT (1) /* SPI inter character space implemented? */ 149 #define SERCOM1_SPI_OZMO (0) /* OZMO features implemented? */ 150 #define SERCOM1_SPI_RX_INT_SRC (52) /* SPI RX Interrupt */ 151 #define SERCOM1_SPI_TX_COMPLETE_INT_SRC (51) /* SPI TX COMPLETE Interrupt */ 152 #define SERCOM1_SPI_TX_READY_INT_SRC (50) /* SPI TX READY Interrupt */ 153 #define SERCOM1_SPI_WAKE_ON_SSL (1) /* _SS low detect implemented? */ 154 #define SERCOM1_TTBIT_EXTENSION (1) /* 32-bit extension implemented? */ 155 #define SERCOM1_USART (1) /* USART mode implemented? */ 156 #define SERCOM1_USART_AUTOBAUD (1) /* USART autobaud implemented? */ 157 #define SERCOM1_USART_COLDET (1) /* USART collision detection implemented? */ 158 #define SERCOM1_USART_ERROR_INT_SRC (53) /* USART ERROR Interrupt */ 159 #define SERCOM1_USART_FLOW_CTRL (1) /* USART flow control implemented? */ 160 #define SERCOM1_USART_FRAC_BAUD (1) /* USART fractional BAUD implemented? */ 161 #define SERCOM1_USART_IRDA (1) /* USART IrDA implemented? */ 162 #define SERCOM1_USART_ISO7816 (1) /* USART ISO7816 mode implemented? */ 163 #define SERCOM1_USART_LIN_MASTER (1) /* USART LIN Master mode implemented? */ 164 #define SERCOM1_USART_RS485 (1) /* USART RS485 mode implemented? */ 165 #define SERCOM1_USART_RX_INT_SRC (52) /* USART RX Interrupt */ 166 #define SERCOM1_USART_SAMPA_EXT (1) /* USART sample adjust implemented? */ 167 #define SERCOM1_USART_SAMPR_EXT (1) /* USART oversampling adjustment implemented? */ 168 #define SERCOM1_USART_TX_COMPLETE_INT_SRC (51) /* USART TX COMPLETE Interrupt */ 169 #define SERCOM1_USART_TX_READY_INT_SRC (50) /* USART TX READY Interrupt */ 170 171 #endif /* _MICROCHIP_PIC32CXSG_SERCOM1_INSTANCE_FIXUP_H_ */ 172
