1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_QSPI_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_QSPI_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for QSPI peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */ 13 #define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */ 14 #define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */ 15 #define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */ 16 #define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */ 17 #define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */ 18 #define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */ 19 #define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */ 20 #define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */ 21 #define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */ 22 #define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */ 23 #define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */ 24 #define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */ 25 #define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */ 26 #else 27 #define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */ 28 #define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */ 29 #define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */ 30 #define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */ 31 #define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */ 32 #define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */ 33 #define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */ 34 #define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */ 35 #define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */ 36 #define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */ 37 #define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */ 38 #define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */ 39 #define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */ 40 #define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */ 41 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 #endif /* _MICROCHIP_PIC32CXSG_QSPI_INSTANCE_FIXUP_H_ */ 44
