1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PCC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PCC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for PCC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_PCC_MR (0x43002C00) /**< \brief (PCC) Mode Register */ 13 #define REG_PCC_IER (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */ 14 #define REG_PCC_IDR (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */ 15 #define REG_PCC_IMR (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */ 16 #define REG_PCC_ISR (0x43002C10) /**< \brief (PCC) Interrupt Status Register */ 17 #define REG_PCC_RHR (0x43002C14) /**< \brief (PCC) Reception Holding Register */ 18 #define REG_PCC_WPMR (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */ 19 #define REG_PCC_WPSR (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */ 20 #else 21 #define REG_PCC_MR (*(RwReg *)0x43002C00UL) /**< \brief (PCC) Mode Register */ 22 #define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */ 23 #define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */ 24 #define REG_PCC_IMR (*(RoReg *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */ 25 #define REG_PCC_ISR (*(RoReg *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */ 26 #define REG_PCC_RHR (*(RoReg *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */ 27 #define REG_PCC_WPMR (*(RwReg *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */ 28 #define REG_PCC_WPSR (*(RoReg *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */ 29 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 30 31 #endif /* _MICROCHIP_PIC32CXSG_PCC_INSTANCE_FIXUP_H_ */ 32
