1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PAC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PAC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for PAC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */ 13 #define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */ 14 #define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */ 15 #define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */ 16 #define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */ 17 #define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ 18 #define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ 19 #define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ 20 #define REG_PAC_INTFLAGD (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ 21 #define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */ 22 #define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */ 23 #define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */ 24 #define REG_PAC_STATUSD (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */ 25 #else 26 #define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */ 27 #define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */ 28 #define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */ 29 #define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */ 30 #define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */ 31 #define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ 32 #define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ 33 #define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ 34 #define REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ 35 #define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */ 36 #define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */ 37 #define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */ 38 #define REG_PAC_STATUSD (*(RoReg *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */ 39 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 40 41 #endif /* _MICROCHIP_PIC32CXSG_PAC_INSTANCE_FIXUP_H_ */ 42
