1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_NVMCTRL_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_NVMCTRL_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for NVMCTRL peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ 13 #define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ 14 #define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ 15 #define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 16 #define REG_NVMCTRL_INTENSET (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */ 17 #define REG_NVMCTRL_INTFLAG (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 18 #define REG_NVMCTRL_STATUS (0x41004012) /**< \brief (NVMCTRL) Status */ 19 #define REG_NVMCTRL_ADDR (0x41004014) /**< \brief (NVMCTRL) Address */ 20 #define REG_NVMCTRL_RUNLOCK (0x41004018) /**< \brief (NVMCTRL) Lock Section */ 21 #define REG_NVMCTRL_PBLDATA0 (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */ 22 #define REG_NVMCTRL_PBLDATA1 (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */ 23 #define REG_NVMCTRL_ECCERR (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */ 24 #define REG_NVMCTRL_DBGCTRL (0x41004028) /**< \brief (NVMCTRL) Debug Control */ 25 #define REG_NVMCTRL_SEECFG (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */ 26 #define REG_NVMCTRL_SEESTAT (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */ 27 #else 28 #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ 29 #define REG_NVMCTRL_CTRLB (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */ 30 #define REG_NVMCTRL_PARAM (*(RoReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ 31 #define REG_NVMCTRL_INTENCLR (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 32 #define REG_NVMCTRL_INTENSET (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */ 33 #define REG_NVMCTRL_INTFLAG (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 34 #define REG_NVMCTRL_STATUS (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */ 35 #define REG_NVMCTRL_ADDR (*(RwReg *)0x41004014UL) /**< \brief (NVMCTRL) Address */ 36 #define REG_NVMCTRL_RUNLOCK (*(RoReg *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */ 37 #define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */ 38 #define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */ 39 #define REG_NVMCTRL_ECCERR (*(RoReg *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */ 40 #define REG_NVMCTRL_DBGCTRL (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */ 41 #define REG_NVMCTRL_SEECFG (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */ 42 #define REG_NVMCTRL_SEESTAT (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */ 43 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 44 45 #endif /* _MICROCHIP_PIC32CXSG_NVMCTRL_INSTANCE_FIXUP_H_ */ 46
