1 /*
2  * Copyright (c) 2024 Microchip
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MICROCHIP_PIC32CXSG_MCLK_INSTANCE_FIXUP_H_
8 #define _MICROCHIP_PIC32CXSG_MCLK_INSTANCE_FIXUP_H_
9 
10 /* ========== Register definition for MCLK peripheral ========== */
11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
12 #define REG_MCLK_INTENCLR          (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
13 #define REG_MCLK_INTENSET          (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
14 #define REG_MCLK_INTFLAG           (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
15 #define REG_MCLK_HSDIV             (0x40000804) /**< \brief (MCLK) HS Clock Division */
16 #define REG_MCLK_CPUDIV            (0x40000805) /**< \brief (MCLK) CPU Clock Division */
17 #define REG_MCLK_AHBMASK           (0x40000810) /**< \brief (MCLK) AHB Mask */
18 #define REG_MCLK_APBAMASK          (0x40000814) /**< \brief (MCLK) APBA Mask */
19 #define REG_MCLK_APBBMASK          (0x40000818) /**< \brief (MCLK) APBB Mask */
20 #define REG_MCLK_APBCMASK          (0x4000081C) /**< \brief (MCLK) APBC Mask */
21 #define REG_MCLK_APBDMASK          (0x40000820) /**< \brief (MCLK) APBD Mask */
22 #else
23 #define REG_MCLK_INTENCLR          (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
24 #define REG_MCLK_INTENSET          (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
25 #define REG_MCLK_INTFLAG           (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
26 #define REG_MCLK_HSDIV             (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
27 #define REG_MCLK_CPUDIV            (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
28 #define REG_MCLK_AHBMASK           (*(RwReg  *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
29 #define REG_MCLK_APBAMASK          (*(RwReg  *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
30 #define REG_MCLK_APBBMASK          (*(RwReg  *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
31 #define REG_MCLK_APBCMASK          (*(RwReg  *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
32 #define REG_MCLK_APBDMASK          (*(RwReg  *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
33 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
34 
35 #endif /* _MICROCHIP_PIC32CXSG_MCLK_INSTANCE_FIXUP_H_ */
36