1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_ICM_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_ICM_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for ICM peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_ICM_CFG (0x42002C00) /**< \brief (ICM) Configuration */ 13 #define REG_ICM_CTRL (0x42002C04) /**< \brief (ICM) Control */ 14 #define REG_ICM_SR (0x42002C08) /**< \brief (ICM) Status */ 15 #define REG_ICM_IER (0x42002C10) /**< \brief (ICM) Interrupt Enable */ 16 #define REG_ICM_IDR (0x42002C14) /**< \brief (ICM) Interrupt Disable */ 17 #define REG_ICM_IMR (0x42002C18) /**< \brief (ICM) Interrupt Mask */ 18 #define REG_ICM_ISR (0x42002C1C) /**< \brief (ICM) Interrupt Status */ 19 #define REG_ICM_UASR (0x42002C20) /**< \brief (ICM) Undefined Access Status */ 20 #define REG_ICM_DSCR (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */ 21 #define REG_ICM_HASH (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */ 22 #define REG_ICM_UIHVAL0 (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */ 23 #define REG_ICM_UIHVAL1 (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */ 24 #define REG_ICM_UIHVAL2 (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */ 25 #define REG_ICM_UIHVAL3 (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */ 26 #define REG_ICM_UIHVAL4 (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */ 27 #define REG_ICM_UIHVAL5 (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */ 28 #define REG_ICM_UIHVAL6 (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */ 29 #define REG_ICM_UIHVAL7 (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */ 30 #else 31 #define REG_ICM_CFG (*(RwReg *)0x42002C00UL) /**< \brief (ICM) Configuration */ 32 #define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */ 33 #define REG_ICM_SR (*(RoReg *)0x42002C08UL) /**< \brief (ICM) Status */ 34 #define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */ 35 #define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */ 36 #define REG_ICM_IMR (*(RoReg *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */ 37 #define REG_ICM_ISR (*(RoReg *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */ 38 #define REG_ICM_UASR (*(RoReg *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */ 39 #define REG_ICM_DSCR (*(RwReg *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */ 40 #define REG_ICM_HASH (*(RwReg *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */ 41 #define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */ 42 #define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */ 43 #define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */ 44 #define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */ 45 #define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */ 46 #define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */ 47 #define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */ 48 #define REG_ICM_UIHVAL7 (*(WoReg *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */ 49 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 #endif /* _MICROCHIP_PIC32CXSG_ICM_INSTANCE_FIXUP_H_ */ 52
