1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_EIC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_EIC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for EIC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control A */ 13 #define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */ 14 #define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 15 #define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Synchronization Busy */ 16 #define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */ 17 #define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */ 18 #define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */ 19 #define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */ 20 #define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */ 21 #define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */ 22 #define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */ 23 #define REG_EIC_DEBOUNCEN (0x40002830) /**< \brief (EIC) Debouncer Enable */ 24 #define REG_EIC_DPRESCALER (0x40002834) /**< \brief (EIC) Debouncer Prescaler */ 25 #define REG_EIC_PINSTATE (0x40002838) /**< \brief (EIC) Pin State */ 26 #else 27 #define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */ 28 #define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */ 29 #define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 30 #define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */ 31 #define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */ 32 #define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */ 33 #define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */ 34 #define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ 35 #define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */ 36 #define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */ 37 #define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */ 38 #define REG_EIC_DEBOUNCEN (*(RwReg *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */ 39 #define REG_EIC_DPRESCALER (*(RwReg *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */ 40 #define REG_EIC_PINSTATE (*(RoReg *)0x40002838UL) /**< \brief (EIC) Pin State */ 41 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 #endif /* _MICROCHIP_PIC32CXSG_EIC_INSTANCE_FIXUP_H_ */ 44
