1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_DAC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_DAC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for DAC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */ 13 #define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */ 14 #define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */ 15 #define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */ 16 #define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */ 17 #define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */ 18 #define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */ 19 #define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */ 20 #define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */ 21 #define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */ 22 #define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */ 23 #define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */ 24 #define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */ 25 #define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */ 26 #define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */ 27 #define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */ 28 #define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */ 29 #else 30 #define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */ 31 #define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */ 32 #define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */ 33 #define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */ 34 #define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */ 35 #define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */ 36 #define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */ 37 #define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */ 38 #define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */ 39 #define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */ 40 #define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */ 41 #define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */ 42 #define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */ 43 #define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */ 44 #define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */ 45 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */ 46 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */ 47 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 48 49 #endif /* _MICROCHIP_PIC32CXSG_DAC_INSTANCE_FIXUP_H_ */ 50
