1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_ADC1_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_ADC1_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for ADC1 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_ADC1_CTRLA (0x43002000) /**< \brief (ADC1) Control A */ 13 #define REG_ADC1_EVCTRL (0x43002002) /**< \brief (ADC1) Event Control */ 14 #define REG_ADC1_DBGCTRL (0x43002003) /**< \brief (ADC1) Debug Control */ 15 #define REG_ADC1_INPUTCTRL (0x43002004) /**< \brief (ADC1) Input Control */ 16 #define REG_ADC1_CTRLB (0x43002006) /**< \brief (ADC1) Control B */ 17 #define REG_ADC1_REFCTRL (0x43002008) /**< \brief (ADC1) Reference Control */ 18 #define REG_ADC1_AVGCTRL (0x4300200A) /**< \brief (ADC1) Average Control */ 19 #define REG_ADC1_SAMPCTRL (0x4300200B) /**< \brief (ADC1) Sample Time Control */ 20 #define REG_ADC1_WINLT (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */ 21 #define REG_ADC1_WINUT (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */ 22 #define REG_ADC1_GAINCORR (0x43002010) /**< \brief (ADC1) Gain Correction */ 23 #define REG_ADC1_OFFSETCORR (0x43002012) /**< \brief (ADC1) Offset Correction */ 24 #define REG_ADC1_SWTRIG (0x43002014) /**< \brief (ADC1) Software Trigger */ 25 #define REG_ADC1_INTENCLR (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */ 26 #define REG_ADC1_INTENSET (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */ 27 #define REG_ADC1_INTFLAG (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */ 28 #define REG_ADC1_STATUS (0x4300202F) /**< \brief (ADC1) Status */ 29 #define REG_ADC1_SYNCBUSY (0x43002030) /**< \brief (ADC1) Synchronization Busy */ 30 #define REG_ADC1_DSEQDATA (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */ 31 #define REG_ADC1_DSEQCTRL (0x43002038) /**< \brief (ADC1) DMA Sequential Control */ 32 #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */ 33 #define REG_ADC1_RESULT (0x43002040) /**< \brief (ADC1) Result Conversion Value */ 34 #define REG_ADC1_RESS (0x43002044) /**< \brief (ADC1) Last Sample Result */ 35 #define REG_ADC1_CALIB (0x43002048) /**< \brief (ADC1) Calibration */ 36 #else 37 #define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */ 38 #define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */ 39 #define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */ 40 #define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */ 41 #define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */ 42 #define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */ 43 #define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */ 44 #define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */ 45 #define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */ 46 #define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */ 47 #define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */ 48 #define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */ 49 #define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */ 50 #define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */ 51 #define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */ 52 #define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */ 53 #define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */ 54 #define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */ 55 #define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */ 56 #define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */ 57 #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */ 58 #define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */ 59 #define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */ 60 #define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */ 61 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #endif /* _MICROCHIP_PIC32CXSG_ADC1_INSTANCE_FIXUP_H_ */ 64
