1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_ADC_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_ADC_FIXUP_H_ 9 10 #if defined(ADC_SYNCBUSY_Msk) 11 #define ADC_SYNC(adc) ((adc)->SYNCBUSY.reg) 12 #define ADC_SYNC_MASK (ADC_SYNCBUSY_Msk) 13 #elif defined(ADC_STATUS_SYNCBUSY) 14 #define ADC_SYNC(adc) ((adc)->STATUS.reg) 15 #define ADC_SYNC_MASK (ADC_STATUS_SYNCBUSY) 16 #else 17 #error ADC 'ADC_SYNCBUSY_MASK' not supported... 18 #endif 19 20 #if defined(ADC_INPUTCTRL_DIFFMODE) 21 #define ADC_DIFF(adc) (inputctrl) 22 #define ADC_DIFF_MASK (ADC_INPUTCTRL_DIFFMODE) 23 #elif defined(ADC_CTRLB_DIFFMODE) 24 #define ADC_DIFF(adc) ((adc)->CTRLB.reg) 25 #define ADC_DIFF_MASK (ADC_CTRLB_DIFFMODE) 26 #elif defined(ADC_CTRLC_DIFFMODE) 27 #define ADC_DIFF(adc) ((adc)->CTRLC.reg) 28 #define ADC_DIFF_MASK (ADC_CTRLC_DIFFMODE) 29 #else 30 #error ADC 'ADC_INPUTCTRL_DIFFMODE' not supported... 31 #endif 32 33 #if defined(ADC_CTRLB_RESSEL) 34 #define ADC_RESSEL(adc) ((adc)->CTRLB.bit.RESSEL) 35 #define ADC_RESSEL_8BIT ADC_CTRLB_RESSEL_8BIT_Val 36 #define ADC_RESSEL_10BIT ADC_CTRLB_RESSEL_10BIT_Val 37 #define ADC_RESSEL_12BIT ADC_CTRLB_RESSEL_12BIT_Val 38 #define ADC_RESSEL_16BIT ADC_CTRLB_RESSEL_16BIT_Val 39 #elif defined(ADC_CTRLC_RESSEL) 40 #define ADC_RESSEL(adc) ((adc)->CTRLC.bit.RESSEL) 41 #define ADC_RESSEL_8BIT ADC_CTRLC_RESSEL_8BIT_Val 42 #define ADC_RESSEL_10BIT ADC_CTRLC_RESSEL_10BIT_Val 43 #define ADC_RESSEL_12BIT ADC_CTRLC_RESSEL_12BIT_Val 44 #define ADC_RESSEL_16BIT ADC_CTRLC_RESSEL_16BIT_Val 45 #else 46 #error ADC 'ADC_CTRLB_RESSEL' not supported... 47 #endif 48 49 #if defined(ADC_CTRLA_PRESCALER) 50 #define ADC_PRESCALER(adc) ((adc)->CTRLA.bit.PRESCALER) 51 #define ADC_CTRLx_PRESCALER_DIV ADC_CTRLA_PRESCALER_DIV 52 #elif defined(ADC_CTRLB_PRESCALER) 53 #define ADC_PRESCALER(adc) ((adc)->CTRLB.bit.PRESCALER) 54 #define ADC_CTRLx_PRESCALER_DIV ADC_CTRLB_PRESCALER_DIV 55 #else 56 #error ADC 'ADC_CTRLA_PRESCALER' not supported... 57 #endif 58 59 #if 0 /* Microchip - This featured deprecated */ 60 #if defined(SYSCTRL_VREF_TSEN) 61 #define ADC_TSEN (SYSCTRL->VREF.bit.TSEN) 62 #elif defined(SUPC_VREF_TSEN) 63 #define ADC_TSEN (SUPC->VREF.bit.TSEN) 64 #else 65 #error ADC 'SYSCTRL_VREF_TSEN' not supported... 66 #endif 67 #endif /* Microchip */ 68 69 #if defined(SYSCTRL_VREF_BGOUTEN) 70 #define ADC_BGEN (SYSCTRL->VREF.bit.BGOUTEN) 71 #elif defined(SUPC_VREF_VREFOE) 72 #define ADC_BGEN (SUPC->VREF.bit.VREFOE) 73 #else 74 #error ADC 'SYSCTRL_VREF_BGOUTEN' not supported... 75 #endif 76 77 #if defined(MCLK) 78 /* a trailing underscore and/or lumpy concatenation is used to prevent expansion */ 79 #define ADC_SAM0_CALIB(prefix, val) \ 80 UTIL_CAT(ADC_CALIB_, val)( \ 81 (((*(uint32_t *)UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _ADDR)) \ 82 >> UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _Pos)) \ 83 & UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _Msk)) \ 84 ) 85 86 #if ADC_INST_NUM == 1 87 # define ADC_FUSES_PREFIX(n) ADC_ 88 #else 89 # define ADC_FUSES_PREFIX(n) UTIL_CAT(AD, UTIL_CAT(C, UTIL_CAT(n, _))) 90 #endif 91 92 #if defined(ADC_FUSES_BIASCOMP) || defined(ADC0_FUSES_BIASCOMP) 93 # define ADC_SAM0_BIASCOMP(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASCOMP) 94 #else 95 # define ADC_SAM0_BIASCOMP(n) 0 96 #endif 97 98 #if defined(ADC_FUSES_BIASR2R) || defined(ADC0_FUSES_BIASR2R) 99 # define ADC_SAM0_BIASR2R(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASR2R) 100 #else 101 # define ADC_SAM0_BIASR2R(n) 0 102 #endif 103 104 #if defined(ADC_FUSES_BIASREFBUF) || defined(ADC0_FUSES_BIASREFBUF) 105 # define ADC_SAM0_BIASREFBUF(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASREFBUF) 106 #else 107 # define ADC_SAM0_BIASREFBUF(n) 0 108 #endif 109 110 /* 111 * The following MCLK clock configuration fix-up symbols map to the applicable 112 * APB-specific symbols, in order to accommodate different SoC series with the 113 * ADC core connected to different APBs. 114 */ 115 #if defined(MCLK_APBDMASK_ADC) || defined(MCLK_APBDMASK_ADC0) 116 # define MCLK_ADC (MCLK->APBDMASK.reg) 117 #elif defined(MCLK_APBCMASK_ADC0) 118 # define MCLK_ADC (MCLK->APBCMASK.reg) 119 #else 120 # error ADC 'MCLK_APBDMASK_ADC) || defined(MCLK_APBDMASK_ADC0' not supported... 121 #endif 122 #endif /* MCLK */ 123 124 /* 125 * All SAM0 define the internal voltage reference as 1.0V by default. 126 */ 127 #ifndef ADC_REFCTRL_REFSEL_INTERNAL 128 # ifdef ADC_REFCTRL_REFSEL_INTREF 129 # define ADC_REFCTRL_REFSEL_INTERNAL ADC_REFCTRL_REFSEL_INTREF 130 # else 131 # define ADC_REFCTRL_REFSEL_INTERNAL ADC_REFCTRL_REFSEL_INT1V 132 # endif 133 #endif 134 135 /* 136 * Some SAM0 devices can use VDDANA as a direct reference. For the devices 137 * that not offer this option, the internal 1.0V reference will be used. 138 */ 139 #ifndef ADC_REFCTRL_REFSEL_VDD_1 140 # if defined(ADC0_BANDGAP) 141 # define ADC_REFCTRL_REFSEL_VDD_1 ADC_REFCTRL_REFSEL_INTVCC1 142 # elif defined(ADC_REFCTRL_REFSEL_INTVCC2) 143 # define ADC_REFCTRL_REFSEL_VDD_1 ADC_REFCTRL_REFSEL_INTVCC2 144 # endif 145 #endif 146 147 /* 148 * SAMD/E5x define ADC[0-1]_BANDGAP symbol. Only those devices use INTVCC0 to 149 * implement VDDANA / 2. 150 */ 151 #ifndef ADC_REFCTRL_REFSEL_VDD_1_2 152 # ifdef ADC0_BANDGAP 153 # define ADC_REFCTRL_REFSEL_VDD_1_2 ADC_REFCTRL_REFSEL_INTVCC0 154 # else 155 # define ADC_REFCTRL_REFSEL_VDD_1_2 ADC_REFCTRL_REFSEL_INTVCC1 156 # endif 157 #endif 158 159 #endif /* _MICROCHIP_PIC32CXSG_ADC_FIXUP_H_ */ 160
