1 /*******************************************************************************
2  * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * MPFS HAL Embedded Software
7  *
8  */
9 /*******************************************************************************
10  * @file mss_pmp.h
11  * @author Microchip-FPGA Embedded Systems Solutions
12  * @brief PolarFire SoC MSS PMP configuration using MSS configurator values.
13  *
14  */
15 /*=========================================================================*//**
16 
17  *//*=========================================================================*/
18 #ifndef MSS_PMP_H
19 #define MSS_PMP_H
20 
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #if !defined (LIBERO_SETTING_MEM_CONFIGS_ENABLED)
27 #define LIBERO_SETTING_MEM_CONFIGS_ENABLED      0ULL
28 /* Enabled when bit set to 1                               */
29 /* PMP                               [0:0]   RW value= 0x0 */
30 /* MPU                               [1:0]   RW value= 0x0 */
31 #endif
32 #define PMP_ENABLED_MASK      1UL
33 #define MPU_ENABLED_MASK      2UL
34 
35 /*
36  * Bit offsets associated with LIBERO_SETTING_CONTEXT_A_HART_EN and
37  * LIBERO_SETTING_CONTEXT_B_HART_EN
38  */
39 #define CONTEXT_EN_MASK_MMUART0        (1U<<0)
40 #define CONTEXT_EN_MASK_MMUART1        (1U<<1)
41 #define CONTEXT_EN_MASK_MMUART2        (1U<<2)
42 #define CONTEXT_EN_MASK_MMUART3        (1U<<3)
43 #define CONTEXT_EN_MASK_MMUART4        (1U<<4)
44 #define CONTEXT_EN_MASK_WDOG0          (1U<<5)
45 #define CONTEXT_EN_MASK_WDOG1          (1U<<6)
46 #define CONTEXT_EN_MASK_WDOG2          (1U<<7)
47 #define CONTEXT_EN_MASK_WDOG3          (1U<<8)
48 #define CONTEXT_EN_MASK_WDOG4          (1U<<9)
49 #define CONTEXT_EN_MASK_SPI0           (1U<<10)
50 #define CONTEXT_EN_MASK_SPI1           (1U<<11)
51 #define CONTEXT_EN_MASK_I2C0           (1U<<12)
52 #define CONTEXT_EN_MASK_I2C1           (1U<<13)
53 #define CONTEXT_EN_MASK_CAN0           (1U<<14)
54 #define CONTEXT_EN_MASK_CAN1           (1U<<15)
55 #define CONTEXT_EN_MASK_MAC0           (1U<<16)
56 #define CONTEXT_EN_MASK_MAC1           (1U<<17)
57 #define CONTEXT_EN_MASK_TIMER          (1U<<18)
58 #define CONTEXT_EN_MASK_GPIO0          (1U<<19)
59 #define CONTEXT_EN_MASK_GPIO1          (1U<<20)
60 #define CONTEXT_EN_MASK_GPIO2          (1U<<21)
61 #define CONTEXT_EN_MASK_RTC            (1U<<22)
62 #define CONTEXT_EN_MASK_H2FINT         (1U<<23)
63 #define CONTEXT_EN_MASK_CRYPTO         (1U<<24)
64 #define CONTEXT_EN_MASK_USB            (1U<<25)
65 #define CONTEXT_EN_MASK_QSPIXIP        (1U<<26)
66 #define CONTEXT_EN_MASK_ATHENA         (1U<<27)
67 #define CONTEXT_EN_MASK_TRACE          (1U<<28)
68 #define CONTEXT_EN_MASK_MAILBOX_SC     (1U<<29)
69 #define CONTEXT_EN_MASK_MMC            (1U<<30)
70 #define CONTEXT_EN_MASK_CFM            (1U<<31)
71 
72 /*
73  * Bit offsets associated with LIBERO_SETTING_CONTEXT_A_FIC_EN and
74  * LIBERO_SETTING_CONTEXT_B_FIC_EN
75  */
76 #define CONTEXT_EN_MASK_FIC0            (1U<<0)
77 #define CONTEXT_EN_MASK_FIC1            (1U<<1)
78 #define CONTEXT_EN_MASK_FIC2            (1U<<2)
79 #define CONTEXT_EN_MASK_FIC3            (1U<<3)
80 
81 
82 uint8_t pmp_configure(uint8_t hart_id);
83 void pmp_master_configs(uint8_t hart_id, uint64_t * pmp0cfg);
84 
85 #ifdef __cplusplus
86 }
87 #endif
88 
89 
90 #endif /* MSS_PMP_H */
91