1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_BDP_API_H
7 #define _MEC_BDP_API_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include "device_mec5.h"
14 #include "mec_defs.h"
15 #include "mec_retval.h"
16 
17 /* Microchip MEC5 BIOS debug I/O port capture.
18  * BDG can be configure to capture x86 system I/O writes to
19  * 1. One, two, and four byte writes to a 4-byte aligned I/O address range
20  * 2. One byte writes to an address alias of the first byte of the 4-byte range.
21  */
22 
23 /* Interfaces to any C modules */
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
29 enum mec5_bdp_status {
30     MEC5_BDP_STS_NOT_EMPTY = MEC_BIT(0), /* FIFO contains data */
31     MEC5_BDP_STS_OVERRUN   = MEC_BIT(1), /* FIFO has been overrun */
32     MEC5_BDP_STS_THRES     = MEC_BIT(2), /* FIFO contains >= threshold entries */
33 };
34 
35 #define MEC5_BDP_CFG_FIFO_THRES_POS         0
36 #define MEC5_BDP_CFG_FIFO_THRES_MSK         0x7
37 #define MEC5_BDP_CFG_FIFO_THRES_1           0
38 #define MEC5_BDP_CFG_FIFO_THRES_4           1
39 #define MEC5_BDP_CFG_FIFO_THRES_8           2
40 #define MEC5_BDP_CFG_FIFO_THRES_16          3
41 #define MEC5_BDP_CFG_FIFO_THRES_20          4
42 #define MEC5_BDP_CFG_FIFO_THRES_24          5
43 #define MEC5_BDP_CFG_FIFO_THRES_28          6
44 #define MEC5_BDP_CFG_FIFO_THRES_30          7
45 
46 #define MEC5_BDP_CFG_THRH_IEN_POS           4
47 #define MEC5_BDP_CFG_ALIAS_EN_POS           5
48 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_POS    6
49 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_MSK    (3u << 6)
50 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_0      0
51 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_1      (1u << 6)
52 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_2      (2u << 6)
53 #define MEC5_BDP_CFG_ALIAS_BYTE_LANE_3      (3u << 6)
54 
55 #define MEC5_BDP_CFG_ACTV_POS               12
56 #define MEC5_BDP_CFG_ALIAS_ACTV_POS         13
57 
58 /* BDP FIFO contains 32 16-bit entries */
59 #define MEC_BDP_FIFO_MAX_ENTRIES            32
60 
61 /* 16-bit FIFO entry */
62 #define MEC_BDP_FIFO_DATA_POS               0
63 #define MEC_BDP_FIFO_DATA_MSK               0xffu
64 #define MEC_BDP_FIFO_ATTR_POS               8
65 #define MEC_BDP_FIFO_ATTR_MSK               0x7fu
66 
67 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_POS     8
68 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_MSK     0x300u
69 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_0       0
70 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_1       0x100u
71 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_2       0x200u
72 #define MEC_BDP_FIFO_ATTR_BYTE_LANE_3       0x300u
73 
74 #define MEC_BDP_FIFO_ATTR_SIZE_POS          10
75 #define MEC_BDP_FIFO_ATTR_SIZE_MSK          0xc00u
76 #define MEC_BDP_FIFO_ATTR_SIZE_1            0
77 #define MEC_BDP_FIFO_ATTR_SIZE_2            0x400u
78 #define MEC_BDP_FIFO_ATTR_SIZE_4            0x800u
79 #define MEC_BDP_FIFO_ATTR_SIZE_INVAL        0xc00u
80 
81 /* read-only copy of FIFO Not Empty from the STATUS register */
82 #define MEC_BDP_FIFO_ATTR_NOT_EMPTY_POS     12
83 
84 /* read-only copy of FIFO Overrun from the STATUS register */
85 #define MEC_BDP_FIFO_ATTR_OVERRUN_POS       13
86 
87 /* read-only copy of FIFO Threshold status from the STATUS register */
88 #define MEC_BDP_FIFO_ATTR_THRES_POS         14
89 
90 /* forward reference */
91 struct mec_bdp_regs;
92 
93 int mec_hal_bdp_init(struct mec_bdp_regs *regs, uint32_t cfg_flags);
94 
95 #define MEC_BDP_SELECT_ALIAS 1
96 int mec_hal_bdp_activate(struct mec_bdp_regs *regs, uint8_t enable, uint8_t is_alias);
97 
98 void mec_hal_bdp_intr_en(struct mec_bdp_regs *regs, uint8_t enable);
99 
100 int mec_hal_bdp_girq_ctrl(struct mec_bdp_regs *regs, uint8_t enable);
101 int mec_hal_bdp_girq_status_clr(struct mec_bdp_regs *regs);
102 
103 /* set threshold level based on encoded value */
104 int mec_hal_bdp_fifo_thresh_set(struct mec_bdp_regs *regs, uint32_t cfg_thrh);
105 
106 /* return configured threshold level in bytes */
107 uint32_t mec_hal_bdp_fifo_thresh_get(struct mec_bdp_regs *regs);
108 
109 uint32_t mec_hal_bdp_status(struct mec_bdp_regs *regs);
110 uint32_t mec_hal_bdp_snapshot(struct mec_bdp_regs *regs);
111 
112 /* Captured Host I/O cycle
113  * flags[3:0] = start byte lane
114  * flags[7:4] = size = 1, 2, or 4 bytes
115  */
116 #define MEC_BDP_IO_LANE_POS 0
117 #define MEC_BDP_IO_LANE_MSK 0x3
118 #define MEC_BDP_IO_SIZE_POS 4
119 #define MEC_BDP_IO_SIZE_MSK 0x70
120 
121 struct mec_bdp_io {
122     uint32_t data;
123     uint8_t flags;
124 };
125 
126 int mec_hal_bdp_get_host_io(struct mec_bdp_regs *regs, struct mec_bdp_io *capio);
127 
128 
mec_hal_bdp_fifo_not_empty(struct mec_bdp_regs * regs)129 inline static uint32_t mec_hal_bdp_fifo_not_empty(struct mec_bdp_regs *regs)
130 {
131     return (regs->STATUS & MEC_BIT(0));
132 }
133 
134 /* FIFO 16-bit data and attributes read as a 32-bit value.
135  * b[7:0] = data only valid if FIFO not empty
136  * b[15:8] = attributes, always valid
137  * b[31:16] = 0 rsvd
138  */
mec_hal_bdp_fifo_read(struct mec_bdp_regs * regs)139 inline static uint32_t mec_hal_bdp_fifo_read(struct mec_bdp_regs *regs)
140 {
141     return regs->DATRB;
142 }
143 
144 #ifdef __cplusplus
145 }
146 #endif
147 
148 #endif /* #ifndef _MEC_BDP_API_H */
149