1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_PWM_V1_H 7 #define _MEC5_PWM_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief Pulse width modulator (MEC_PWM0) 15 */ 16 17 typedef struct mec_pwm_regs { /*!< (@ 0x40005800) MEC_PWM0 Structure */ 18 __IOM uint32_t CNT_ON; /*!< (@ 0x00000000) PWM counter on */ 19 __IOM uint32_t CNT_OFF; /*!< (@ 0x00000004) PWM counter off */ 20 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) PWM configuration */ 21 } MEC_PWM_Type; /*!< Size = 12 (0xc) */ 22 23 /** @} */ /* End of group Device_Peripheral_peripherals */ 24 25 /** @addtogroup PosMask_peripherals 26 * @{ 27 */ 28 /* ======================================================== CONFIG ========================================================= */ 29 #define MEC_PWM_CONFIG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 30 #define MEC_PWM_CONFIG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 31 #define MEC_PWM_CONFIG_CLK_SRC_SLOW_Pos (1UL) /*!< CLK_SRC_SLOW (Bit 1) */ 32 #define MEC_PWM_CONFIG_CLK_SRC_SLOW_Msk (0x2UL) /*!< CLK_SRC_SLOW (Bitfield-Mask: 0x01) */ 33 #define MEC_PWM_CONFIG_INVERT_Pos (2UL) /*!< INVERT (Bit 2) */ 34 #define MEC_PWM_CONFIG_INVERT_Msk (0x4UL) /*!< INVERT (Bitfield-Mask: 0x01) */ 35 #define MEC_PWM_CONFIG_CLKDIV_Pos (3UL) /*!< CLKDIV (Bit 3) */ 36 #define MEC_PWM_CONFIG_CLKDIV_Msk (0x78UL) /*!< CLKDIV (Bitfield-Mask: 0x0f) */ 37 38 /** @} */ /* End of group PosMask_peripherals */ 39 40 /** @addtogroup EnumValue_peripherals 41 * @{ 42 */ 43 /* ======================================================== CONFIG ========================================================= */ 44 /* ============================================= MEC_PWM CONFIG ENABLE [0..0] ============================================= */ 45 typedef enum { /*!< MEC_PWM_CONFIG_ENABLE */ 46 MEC_PWM_CONFIG_ENABLE_ON = 1, /*!< ON : Enable */ 47 } MEC_PWM_CONFIG_ENABLE_Enum; 48 49 /* ========================================== MEC_PWM CONFIG CLK_SRC_SLOW [1..1] ========================================== */ 50 typedef enum { /*!< MEC_PWM_CONFIG_CLK_SRC_SLOW */ 51 MEC_PWM_CONFIG_CLK_SRC_SLOW_ENABLE = 1, /*!< ENABLE : Use PCR slow clock as PWM source instead of 48MHz AHB 52 clock */ 53 } MEC_PWM_CONFIG_CLK_SRC_SLOW_Enum; 54 55 /* ============================================= MEC_PWM CONFIG INVERT [2..2] ============================================= */ 56 typedef enum { /*!< MEC_PWM_CONFIG_INVERT */ 57 MEC_PWM_CONFIG_INVERT_EN = 1, /*!< EN : Invert output */ 58 } MEC_PWM_CONFIG_INVERT_Enum; 59 60 /* ============================================= MEC_PWM CONFIG CLKDIV [3..6] ============================================= */ 61 typedef enum { /*!< MEC_PWM_CONFIG_CLKDIV */ 62 MEC_PWM_CONFIG_CLKDIV_PR1 = 0, /*!< PR1 : Pre-divider = 1 */ 63 MEC_PWM_CONFIG_CLKDIV_PR2 = 1, /*!< PR2 : Pre-divider = 2 */ 64 MEC_PWM_CONFIG_CLKDIV_PR3 = 2, /*!< PR3 : Pre-divider = 3 */ 65 MEC_PWM_CONFIG_CLKDIV_PR4 = 3, /*!< PR4 : Pre-divider = 4 */ 66 MEC_PWM_CONFIG_CLKDIV_PR5 = 4, /*!< PR5 : Pre-divider = 5 */ 67 MEC_PWM_CONFIG_CLKDIV_PR6 = 5, /*!< PR6 : Pre-divider = 6 */ 68 MEC_PWM_CONFIG_CLKDIV_PR7 = 6, /*!< PR7 : Pre-divider = 7 */ 69 MEC_PWM_CONFIG_CLKDIV_PR8 = 7, /*!< PR8 : Pre-divider = 8 */ 70 MEC_PWM_CONFIG_CLKDIV_PR9 = 8, /*!< PR9 : Pre-divider = 9 */ 71 MEC_PWM_CONFIG_CLKDIV_PR10 = 9, /*!< PR10 : Pre-divider = 10 */ 72 MEC_PWM_CONFIG_CLKDIV_PR11 = 10, /*!< PR11 : Pre-divider = 11 */ 73 MEC_PWM_CONFIG_CLKDIV_PR12 = 11, /*!< PR12 : Pre-divider = 12 */ 74 MEC_PWM_CONFIG_CLKDIV_PR13 = 12, /*!< PR13 : Pre-divider = 13 */ 75 MEC_PWM_CONFIG_CLKDIV_PR14 = 13, /*!< PR14 : Pre-divider = 14 */ 76 MEC_PWM_CONFIG_CLKDIV_PR15 = 14, /*!< PR15 : Pre-divider = 15 */ 77 MEC_PWM_CONFIG_CLKDIV_PR16 = 15, /*!< PR16 : Pre-divider = 16 */ 78 } MEC_PWM_CONFIG_CLKDIV_Enum; 79 80 /** @} */ /* End of group EnumValue_peripherals */ 81 82 #endif /* _MEC5_PWM_V1_H */ 83
