1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_ESPI_VW_V1_5_H 7 #define _MEC5_ESPI_VW_V1_5_H 8 9 /** @addtogroup Device_Peripheral_clusters 10 * @{ 11 */ 12 /** 13 * @brief MEC_ESPI_VW_CTVW [CTVW] (eSPI Host to Device Virtual Wire 96-bit registers) 14 */ 15 typedef struct mec_espi_vw_ctvw_regs { 16 __IOM uint32_t HIRSS; /*!< (@ 0x00000000) Host index, reset source and reset state for 17 the group of 4 virtual wires */ 18 __IOM uint32_t SRC_ISELS; /*!< (@ 0x00000004) VW group IRQ Select for each of the 4 VWires */ 19 __IOM uint32_t STATES; /*!< (@ 0x00000008) VW group VWire states */ 20 } MEC_ESPI_VW_CTVW_Type; /*!< Size = 12 (0xc) */ 21 22 23 /** 24 * @brief MEC_ESPI_VW_TCVW [TCVW] (Device to eSPI Host Wire 64-bit registers) 25 */ 26 typedef struct mec_espi_vw_tcvw_regs { 27 __IOM uint32_t HIRCS; /*!< (@ 0x00000000) Host index, reset configuration, and R/O change 28 status */ 29 __IOM uint32_t STATES; /*!< (@ 0x00000004) VW group register containing states of the 4 30 VWires */ 31 } MEC_ESPI_VW_TCVW_Type; /*!< Size = 8 (0x8) */ 32 33 /** @} */ /* End of group Device_Peripheral_clusters */ 34 35 /** @addtogroup Device_Peripheral_peripherals 36 * @{ 37 */ 38 /** 39 * @brief eSPI Virtual Wire Logic (MEC_ESPI_VW) 40 */ 41 42 typedef struct mec_espi_vw_regs { /*!< (@ 0x400F9C00) MEC_ESPI_VW Structure */ 43 __IOM MEC_ESPI_VW_CTVW_Type CTVW[11]; /*!< (@ 0x00000000) eSPI Host to Device Virtual Wire 96-bit registers */ 44 __IM uint32_t RESERVED[95]; 45 __IOM MEC_ESPI_VW_TCVW_Type TCVW[11]; /*!< (@ 0x00000200) Device to eSPI Host Wire 64-bit registers */ 46 } MEC_ESPI_VW_Type; /*!< Size = 600 (0x258) */ 47 48 /** @} */ /* End of group Device_Peripheral_peripherals */ 49 50 /** @addtogroup PosMask_clusters 51 * @{ 52 */ 53 /* ================ CTVW ================ */ 54 /* ========================================================= HIRSS ========================================================= */ 55 #define MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Pos (0UL) /*!< HOST_IDX (Bit 0) */ 56 #define MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Msk (0xffUL) /*!< HOST_IDX (Bitfield-Mask: 0xff) */ 57 #define MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_Pos (8UL) /*!< RST_SRC (Bit 8) */ 58 #define MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_Msk (0x300UL) /*!< RST_SRC (Bitfield-Mask: 0x03) */ 59 #define MEC_ESPI_VW_CTVW_HIRSS_RST_STATE_Pos (12UL) /*!< RST_STATE (Bit 12) */ 60 #define MEC_ESPI_VW_CTVW_HIRSS_RST_STATE_Msk (0xf000UL) /*!< RST_STATE (Bitfield-Mask: 0x0f) */ 61 /* ======================================================= SRC_ISELS ======================================================= */ 62 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Pos (0UL) /*!< SRC0_IRQ_SEL (Bit 0) */ 63 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Msk (0xfUL) /*!< SRC0_IRQ_SEL (Bitfield-Mask: 0x0f) */ 64 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_Pos (8UL) /*!< SRC1_IRQ_SEL (Bit 8) */ 65 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_Msk (0xf00UL) /*!< SRC1_IRQ_SEL (Bitfield-Mask: 0x0f) */ 66 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_Pos (16UL) /*!< SRC2_IRQ_SEL (Bit 16) */ 67 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_Msk (0xf0000UL) /*!< SRC2_IRQ_SEL (Bitfield-Mask: 0x0f) */ 68 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_Pos (24UL) /*!< SRC3_IRQ_SEL (Bit 24) */ 69 #define MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_Msk (0xf000000UL) /*!< SRC3_IRQ_SEL (Bitfield-Mask: 0x0f) */ 70 /* ======================================================== STATES ========================================================= */ 71 #define MEC_ESPI_VW_CTVW_STATES_SRC0_Pos (0UL) /*!< SRC0 (Bit 0) */ 72 #define MEC_ESPI_VW_CTVW_STATES_SRC0_Msk (0x1UL) /*!< SRC0 (Bitfield-Mask: 0x01) */ 73 #define MEC_ESPI_VW_CTVW_STATES_SRC1_Pos (8UL) /*!< SRC1 (Bit 8) */ 74 #define MEC_ESPI_VW_CTVW_STATES_SRC1_Msk (0x100UL) /*!< SRC1 (Bitfield-Mask: 0x01) */ 75 #define MEC_ESPI_VW_CTVW_STATES_SRC2_Pos (16UL) /*!< SRC2 (Bit 16) */ 76 #define MEC_ESPI_VW_CTVW_STATES_SRC2_Msk (0x10000UL) /*!< SRC2 (Bitfield-Mask: 0x01) */ 77 #define MEC_ESPI_VW_CTVW_STATES_SRC3_Pos (24UL) /*!< SRC3 (Bit 24) */ 78 #define MEC_ESPI_VW_CTVW_STATES_SRC3_Msk (0x1000000UL) /*!< SRC3 (Bitfield-Mask: 0x01) */ 79 80 /* ================ TCVW ================ */ 81 /* ========================================================= HIRCS ========================================================= */ 82 #define MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX_Pos (0UL) /*!< HOST_IDX (Bit 0) */ 83 #define MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX_Msk (0xffUL) /*!< HOST_IDX (Bitfield-Mask: 0xff) */ 84 #define MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_Pos (8UL) /*!< RST_SRC (Bit 8) */ 85 #define MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_Msk (0x300UL) /*!< RST_SRC (Bitfield-Mask: 0x03) */ 86 #define MEC_ESPI_VW_TCVW_HIRCS_RST_STATE_Pos (12UL) /*!< RST_STATE (Bit 12) */ 87 #define MEC_ESPI_VW_TCVW_HIRCS_RST_STATE_Msk (0xf000UL) /*!< RST_STATE (Bitfield-Mask: 0x0f) */ 88 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE0_Pos (16UL) /*!< CHANGE0 (Bit 16) */ 89 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE0_Msk (0x10000UL) /*!< CHANGE0 (Bitfield-Mask: 0x01) */ 90 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE1_Pos (17UL) /*!< CHANGE1 (Bit 17) */ 91 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE1_Msk (0x20000UL) /*!< CHANGE1 (Bitfield-Mask: 0x01) */ 92 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE2_Pos (18UL) /*!< CHANGE2 (Bit 18) */ 93 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE2_Msk (0x40000UL) /*!< CHANGE2 (Bitfield-Mask: 0x01) */ 94 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE3_Pos (19UL) /*!< CHANGE3 (Bit 19) */ 95 #define MEC_ESPI_VW_TCVW_HIRCS_CHANGE3_Msk (0x80000UL) /*!< CHANGE3 (Bitfield-Mask: 0x01) */ 96 /* ======================================================== STATES ========================================================= */ 97 #define MEC_ESPI_VW_TCVW_STATES_SRC0_Pos (0UL) /*!< SRC0 (Bit 0) */ 98 #define MEC_ESPI_VW_TCVW_STATES_SRC0_Msk (0x1UL) /*!< SRC0 (Bitfield-Mask: 0x01) */ 99 #define MEC_ESPI_VW_TCVW_STATES_SRC1_Pos (8UL) /*!< SRC1 (Bit 8) */ 100 #define MEC_ESPI_VW_TCVW_STATES_SRC1_Msk (0x100UL) /*!< SRC1 (Bitfield-Mask: 0x01) */ 101 #define MEC_ESPI_VW_TCVW_STATES_SRC2_Pos (16UL) /*!< SRC2 (Bit 16) */ 102 #define MEC_ESPI_VW_TCVW_STATES_SRC2_Msk (0x10000UL) /*!< SRC2 (Bitfield-Mask: 0x01) */ 103 #define MEC_ESPI_VW_TCVW_STATES_SRC3_Pos (24UL) /*!< SRC3 (Bit 24) */ 104 #define MEC_ESPI_VW_TCVW_STATES_SRC3_Msk (0x1000000UL) /*!< SRC3 (Bitfield-Mask: 0x01) */ 105 106 /** @} */ /* End of group PosMask_clusters */ 107 108 /** @addtogroup EnumValue_clusters 109 * @{ 110 */ 111 /* ========================================================= CTVW ========================================================= */ 112 typedef enum { /*!< MEC_ESPI_VW_CTVW */ 113 MEC_CTVW_IDX00 = 0, /*!< IDX00 : CTVW array index 0 */ 114 MEC_CTVW_IDX01 = 1, /*!< IDX01 : CTVW array index 1 */ 115 MEC_CTVW_IDX02 = 2, /*!< IDX02 : CTVW array index 2 */ 116 MEC_CTVW_IDX03 = 3, /*!< IDX03 : CTVW array index 3 */ 117 MEC_CTVW_IDX04 = 4, /*!< IDX04 : CTVW array index 4 */ 118 MEC_CTVW_IDX05 = 5, /*!< IDX05 : CTVW array index 5 */ 119 MEC_CTVW_IDX06 = 6, /*!< IDX06 : CTVW array index 6 */ 120 MEC_CTVW_IDX07 = 7, /*!< IDX07 : CTVW array index 7 */ 121 MEC_CTVW_IDX08 = 8, /*!< IDX08 : CTVW array index 8 */ 122 MEC_CTVW_IDX09 = 9, /*!< IDX09 : CTVW array index 9 */ 123 MEC_CTVW_IDX10 = 10, /*!< IDX10 : CTVW array index 10 */ 124 } MEC_CTVW_Enum; 125 126 /* ========================================================= HIRSS ========================================================= */ 127 /* ============================================== CTVW HIRSS HOST_IDX [0..7] =============================================== */ 128 typedef enum { /*!< MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX */ 129 MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_MIN = 2, /*!< MIN : Minimum Host index value */ 130 } MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Enum; 131 132 /* =============================================== CTVW HIRSS RST_SRC [8..9] =============================================== */ 133 typedef enum { /*!< MEC_ESPI_VW_CTVW_HIRSS_RST_SRC */ 134 MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_RST_ESPI = 0, /*!< RST_ESPI : VW group reset value loaded on rising edge of ESPI_nRESET */ 135 MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_RST_SYS = 1, /*!< RST_SYS : VW group reset value loaded on rising edge of RESET_SYS */ 136 MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_RST_SIO = 2, /*!< RST_SIO : VW group reset value loaded on rising edge of RESET_SIO */ 137 MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_PLTRST = 3, /*!< PLTRST : VW group reset value loaded on rising edge of PLTRST */ 138 } MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_Enum; 139 140 /* ============================================= CTVW HIRSS RST_STATE [12..15] ============================================= */ 141 typedef enum { /*!< MEC_ESPI_VW_CTVW_HIRSS_RST_STATE */ 142 MEC_ESPI_VW_CTVW_HIRSS_RST_STATE_ALL_ZERO = 0,/*!< ALL_ZERO : All 4 VWires reset to 0 */ 143 MEC_ESPI_VW_CTVW_HIRSS_RST_STATE_ALL_ONE = 15,/*!< ALL_ONE : All 4 VWires reset to 1 */ 144 } MEC_ESPI_VW_CTVW_HIRSS_RST_STATE_Enum; 145 146 /* ======================================================= SRC_ISELS ======================================================= */ 147 /* ========================================== CTVW SRC_ISELS SRC0_IRQ_SEL [0..3] =========================================== */ 148 typedef enum { /*!< MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL */ 149 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_LEVEL_LO = 0,/*!< LEVEL_LO : VWire interrupt on low level */ 150 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_LEVEL_HI = 1,/*!< LEVEL_HI : VWire interrupt on high level */ 151 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_DIS = 4,/*!< DIS : VWire interrupt disabled */ 152 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_RISING_EDGE = 13,/*!< RISING_EDGE : VWire interrupt on rising edge */ 153 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_FALLING_EDGE = 14,/*!< FALLING_EDGE : VWire interrupt on falling edge */ 154 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_EITHER_EDGE = 15,/*!< EITHER_EDGE : VWire interrupt on either edge */ 155 } MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Enum; 156 157 /* ========================================== CTVW SRC_ISELS SRC1_IRQ_SEL [8..11] ========================================== */ 158 typedef enum { /*!< MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL */ 159 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_LEVEL_LO = 0,/*!< LEVEL_LO : VWire interrupt on low level */ 160 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_LEVEL_HI = 1,/*!< LEVEL_HI : VWire interrupt on high level */ 161 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_DIS = 4,/*!< DIS : VWire interrupt disabled */ 162 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_RISING_EDGE = 13,/*!< RISING_EDGE : VWire interrupt on rising edge */ 163 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_FALLING_EDGE = 14,/*!< FALLING_EDGE : VWire interrupt on falling edge */ 164 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_EITHER_EDGE = 15,/*!< EITHER_EDGE : VWire interrupt on either edge */ 165 } MEC_ESPI_VW_CTVW_SRC_ISELS_SRC1_IRQ_SEL_Enum; 166 167 /* ========================================= CTVW SRC_ISELS SRC2_IRQ_SEL [16..19] ========================================== */ 168 typedef enum { /*!< MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL */ 169 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_LEVEL_LO = 0,/*!< LEVEL_LO : VWire interrupt on low level */ 170 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_LEVEL_HI = 1,/*!< LEVEL_HI : VWire interrupt on high level */ 171 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_DIS = 4,/*!< DIS : VWire interrupt disabled */ 172 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_RISING_EDGE = 13,/*!< RISING_EDGE : VWire interrupt on rising edge */ 173 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_FALLING_EDGE = 14,/*!< FALLING_EDGE : VWire interrupt on falling edge */ 174 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_EITHER_EDGE = 15,/*!< EITHER_EDGE : VWire interrupt on either edge */ 175 } MEC_ESPI_VW_CTVW_SRC_ISELS_SRC2_IRQ_SEL_Enum; 176 177 /* ========================================= CTVW SRC_ISELS SRC3_IRQ_SEL [24..27] ========================================== */ 178 typedef enum { /*!< MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL */ 179 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_LEVEL_LO = 0,/*!< LEVEL_LO : VWire interrupt on low level */ 180 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_LEVEL_HI = 1,/*!< LEVEL_HI : VWire interrupt on high level */ 181 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_DIS = 4,/*!< DIS : VWire interrupt disabled */ 182 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_RISING_EDGE = 13,/*!< RISING_EDGE : VWire interrupt on rising edge */ 183 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_FALLING_EDGE = 14,/*!< FALLING_EDGE : VWire interrupt on falling edge */ 184 MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_EITHER_EDGE = 15,/*!< EITHER_EDGE : VWire interrupt on either edge */ 185 } MEC_ESPI_VW_CTVW_SRC_ISELS_SRC3_IRQ_SEL_Enum; 186 187 /* ======================================================== STATES ========================================================= */ 188 /* ================================================ CTVW STATES SRC0 [0..0] ================================================ */ 189 typedef enum { /*!< MEC_ESPI_VW_CTVW_STATES_SRC0 */ 190 MEC_ESPI_VW_CTVW_STATES_SRC0_HIGH = 1, /*!< HIGH : VW group Source 0 is high */ 191 } MEC_ESPI_VW_CTVW_STATES_SRC0_Enum; 192 193 /* ================================================ CTVW STATES SRC1 [8..8] ================================================ */ 194 typedef enum { /*!< MEC_ESPI_VW_CTVW_STATES_SRC1 */ 195 MEC_ESPI_VW_CTVW_STATES_SRC1_HIGH = 1, /*!< HIGH : VW group Source 1 is high */ 196 } MEC_ESPI_VW_CTVW_STATES_SRC1_Enum; 197 198 /* =============================================== CTVW STATES SRC2 [16..16] =============================================== */ 199 typedef enum { /*!< MEC_ESPI_VW_CTVW_STATES_SRC2 */ 200 MEC_ESPI_VW_CTVW_STATES_SRC2_HIGH = 1, /*!< HIGH : VW group Source 2 is high */ 201 } MEC_ESPI_VW_CTVW_STATES_SRC2_Enum; 202 203 /* =============================================== CTVW STATES SRC3 [24..24] =============================================== */ 204 typedef enum { /*!< MEC_ESPI_VW_CTVW_STATES_SRC3 */ 205 MEC_ESPI_VW_CTVW_STATES_SRC3_HIGH = 1, /*!< HIGH : VW group Source 3 is high */ 206 } MEC_ESPI_VW_CTVW_STATES_SRC3_Enum; 207 208 /* ========================================================= TCVW ========================================================= */ 209 typedef enum { /*!< MEC_ESPI_VW_TCVW */ 210 MEC_TCVW_IDX00 = 0, /*!< IDX00 : TCVW array index 0 */ 211 MEC_TCVW_IDX01 = 1, /*!< IDX01 : TCVW array index 1 */ 212 MEC_TCVW_IDX02 = 2, /*!< IDX02 : TCVW array index 2 */ 213 MEC_TCVW_IDX03 = 3, /*!< IDX03 : TCVW array index 3 */ 214 MEC_TCVW_IDX04 = 4, /*!< IDX04 : TCVW array index 4 */ 215 MEC_TCVW_IDX05 = 5, /*!< IDX05 : TCVW array index 5 */ 216 MEC_TCVW_IDX06 = 6, /*!< IDX06 : TCVW array index 6 */ 217 MEC_TCVW_IDX07 = 7, /*!< IDX07 : TCVW array index 7 */ 218 MEC_TCVW_IDX08 = 8, /*!< IDX08 : TCVW array index 8 */ 219 MEC_TCVW_IDX09 = 9, /*!< IDX09 : TCVW array index 9 */ 220 MEC_TCVW_IDX10 = 10, /*!< IDX10 : TCVW array index 10 */ 221 } MEC_TCVW_Enum; 222 223 /* ========================================================= HIRCS ========================================================= */ 224 /* ============================================== TCVW HIRCS HOST_IDX [0..7] =============================================== */ 225 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX */ 226 MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX_MIN_VAL = 2, /*!< MIN_VAL : Minimum value of host index */ 227 } MEC_ESPI_VW_TCVW_HIRCS_HOST_IDX_Enum; 228 229 /* =============================================== TCVW HIRCS RST_SRC [8..9] =============================================== */ 230 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_RST_SRC */ 231 MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_RST_ESPI = 0, /*!< RST_ESPI : VW group reset value loaded on rising edge of ESPI_nRESET */ 232 MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_RST_SYS = 1, /*!< RST_SYS : VW group reset value loaded on rising edge of RESET_SYS */ 233 MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_RST_SIO = 2, /*!< RST_SIO : VW group reset value loaded on rising edge of RESET_SIO */ 234 MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_PLTRST = 3, /*!< PLTRST : VW group reset value loaded on rising edge of PLTRST */ 235 } MEC_ESPI_VW_TCVW_HIRCS_RST_SRC_Enum; 236 237 /* ============================================= TCVW HIRCS RST_STATE [12..15] ============================================= */ 238 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_RST_STATE */ 239 MEC_ESPI_VW_TCVW_HIRCS_RST_STATE_ALL_ZERO = 0,/*!< ALL_ZERO : All 4 VWires reset to 0 */ 240 MEC_ESPI_VW_TCVW_HIRCS_RST_STATE_ALL_ONE = 15,/*!< ALL_ONE : All 4 VWires reset to 1 */ 241 } MEC_ESPI_VW_TCVW_HIRCS_RST_STATE_Enum; 242 243 /* ============================================== TCVW HIRCS CHANGE0 [16..16] ============================================== */ 244 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_CHANGE0 */ 245 MEC_ESPI_VW_TCVW_HIRCS_CHANGE0_ACTIVE = 1, /*!< ACTIVE : VW group Source 0 changed state */ 246 } MEC_ESPI_VW_TCVW_HIRCS_CHANGE0_Enum; 247 248 /* ============================================== TCVW HIRCS CHANGE1 [17..17] ============================================== */ 249 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_CHANGE1 */ 250 MEC_ESPI_VW_TCVW_HIRCS_CHANGE1_ACTIVE = 1, /*!< ACTIVE : VW group Source 1 changed state */ 251 } MEC_ESPI_VW_TCVW_HIRCS_CHANGE1_Enum; 252 253 /* ============================================== TCVW HIRCS CHANGE2 [18..18] ============================================== */ 254 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_CHANGE2 */ 255 MEC_ESPI_VW_TCVW_HIRCS_CHANGE2_ACTIVE = 1, /*!< ACTIVE : VW group Source 2 changed state */ 256 } MEC_ESPI_VW_TCVW_HIRCS_CHANGE2_Enum; 257 258 /* ============================================== TCVW HIRCS CHANGE3 [19..19] ============================================== */ 259 typedef enum { /*!< MEC_ESPI_VW_TCVW_HIRCS_CHANGE3 */ 260 MEC_ESPI_VW_TCVW_HIRCS_CHANGE3_ACTIVE = 1, /*!< ACTIVE : VW group Source 3 changed state */ 261 } MEC_ESPI_VW_TCVW_HIRCS_CHANGE3_Enum; 262 263 /* ======================================================== STATES ========================================================= */ 264 /* ================================================ TCVW STATES SRC0 [0..0] ================================================ */ 265 typedef enum { /*!< MEC_ESPI_VW_TCVW_STATES_SRC0 */ 266 MEC_ESPI_VW_TCVW_STATES_SRC0_HIGH = 1, /*!< HIGH : VW group Source 0 is one */ 267 } MEC_ESPI_VW_TCVW_STATES_SRC0_Enum; 268 269 /* ================================================ TCVW STATES SRC1 [8..8] ================================================ */ 270 typedef enum { /*!< MEC_ESPI_VW_TCVW_STATES_SRC1 */ 271 MEC_ESPI_VW_TCVW_STATES_SRC1_HIGH = 1, /*!< HIGH : VW group Source 1 is one */ 272 } MEC_ESPI_VW_TCVW_STATES_SRC1_Enum; 273 274 /* =============================================== TCVW STATES SRC2 [16..16] =============================================== */ 275 typedef enum { /*!< MEC_ESPI_VW_TCVW_STATES_SRC2 */ 276 MEC_ESPI_VW_TCVW_STATES_SRC2_HIGH = 1, /*!< HIGH : VW group Source 2 is one */ 277 } MEC_ESPI_VW_TCVW_STATES_SRC2_Enum; 278 279 /* =============================================== TCVW STATES SRC3 [24..24] =============================================== */ 280 typedef enum { /*!< MEC_ESPI_VW_TCVW_STATES_SRC3 */ 281 MEC_ESPI_VW_TCVW_STATES_SRC3_HIGH = 1, /*!< HIGH : VW group Source 3 is one */ 282 } MEC_ESPI_VW_TCVW_STATES_SRC3_Enum; 283 284 /** @} */ /* End of group EnumValue_clusters */ 285 286 #endif /* _MEC5_ESPI_VW_V1_5_H */ 287
