1 /* 2 * ARM Limited (ARM) is supplying this software for use with Cortex-M 3 * processor based microcontroller, but can be equally used for other 4 * suitable processor architectures. This file can be freely distributed. 5 * Modifications to this file shall be clearly marked. 6 * 7 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 8 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 10 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 11 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 12 * 13 * @file output/MEC1753_QSZ.h 14 * @brief CMSIS HeaderFile 15 * @version 1.2 16 * @date 19. May 2024 17 * @note Generated by SVDConv V3.3.42 on Sunday, 19.05.2024 10:19:58 18 * from File 'output/MEC1753_QSZ.svd', 19 * 20 * MEC1753 information 21 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 22 */ 23 24 25 26 /** @addtogroup Microchip Technolgy Inc. 27 * @{ 28 */ 29 30 31 /** @addtogroup MEC1753_QSZ 32 * @{ 33 */ 34 35 36 #ifndef MEC1753_QSZ_H 37 #define MEC1753_QSZ_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /** @addtogroup Configuration_of_CMSIS 45 * @{ 46 */ 47 48 49 50 /* =========================================================================================================================== */ 51 /* ================ Interrupt Number Definition ================ */ 52 /* =========================================================================================================================== */ 53 54 typedef enum { 55 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 56 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 57 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 58 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 59 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 60 and No Match */ 61 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 62 related Fault */ 63 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 64 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 65 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 66 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 67 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 68 /* ======================================== MEC1753_QSZ Specific Interrupt Numbers ========================================= */ 69 MEC_GIRQ08_IRQn = 0, /*!< 0 ECIA Aggregated GIRQ 08 */ 70 MEC_GIRQ09_IRQn = 1, /*!< 1 ECIA Aggregated GIRQ 09 */ 71 MEC_GIRQ10_IRQn = 2, /*!< 2 ECIA Aggregated GIRQ 10 */ 72 MEC_GIRQ11_IRQn = 3, /*!< 3 ECIA Aggregated GIRQ 11 */ 73 MEC_GIRQ12_IRQn = 4, /*!< 4 ECIA Aggregated GIRQ 12 */ 74 MEC_GIRQ13_IRQn = 5, /*!< 5 ECIA Aggregated GIRQ 13 */ 75 MEC_GIRQ14_IRQn = 6, /*!< 6 ECIA Aggregated GIRQ 14 */ 76 MEC_GIRQ15_IRQn = 7, /*!< 7 ECIA Aggregated GIRQ 15 */ 77 MEC_GIRQ16_IRQn = 8, /*!< 8 ECIA Aggregated GIRQ 16 */ 78 MEC_GIRQ17_IRQn = 9, /*!< 9 ECIA Aggregated GIRQ 17 */ 79 MEC_GIRQ18_IRQn = 10, /*!< 10 ECIA Aggregated GIRQ 18 */ 80 MEC_GIRQ19_IRQn = 11, /*!< 11 ECIA Aggregated GIRQ 19 */ 81 MEC_GIRQ20_IRQn = 12, /*!< 12 ECIA Aggregated GIRQ 20 */ 82 MEC_GIRQ21_IRQn = 13, /*!< 13 ECIA Aggregated GIRQ 21 */ 83 MEC_GIRQ23_IRQn = 14, /*!< 14 ECIA Aggregated GIRQ 23 */ 84 MEC_GIRQ24_IRQn = 15, /*!< 15 ECIA Aggregated GIRQ 24 */ 85 MEC_GIRQ25_IRQn = 16, /*!< 16 ECIA Aggregated GIRQ 25 */ 86 MEC_GIRQ26_IRQn = 17, /*!< 17 ECIA Aggregated GIRQ 26 */ 87 MEC_I2C_SMB0_IRQn = 20, /*!< 20 I2C_SMB0 interrupt */ 88 MEC_I2C_SMB1_IRQn = 21, /*!< 21 I2C_SMB1 interrupt */ 89 MEC_I2C_SMB2_IRQn = 22, /*!< 22 I2C_SMB2 interrupt */ 90 MEC_I2C_SMB3_IRQn = 23, /*!< 23 I2C_SMB3 interrupt */ 91 MEC_DMA_CH00_IRQn = 24, /*!< 24 DMA Channel 0 interrupt */ 92 MEC_DMA_CH01_IRQn = 25, /*!< 25 DMA Channel 1 interrupt */ 93 MEC_DMA_CH02_IRQn = 26, /*!< 26 DMA Channel 2 interrupt */ 94 MEC_DMA_CH03_IRQn = 27, /*!< 27 DMA Channel 3 interrupt */ 95 MEC_DMA_CH04_IRQn = 28, /*!< 28 DMA Channel 4 interrupt */ 96 MEC_DMA_CH05_IRQn = 29, /*!< 29 DMA Channel 5 interrupt */ 97 MEC_DMA_CH06_IRQn = 30, /*!< 30 DMA Channel 6 interrupt */ 98 MEC_DMA_CH07_IRQn = 31, /*!< 31 DMA Channel 7 interrupt */ 99 MEC_DMA_CH08_IRQn = 32, /*!< 32 DMA Channel 8 interrupt */ 100 MEC_DMA_CH09_IRQn = 33, /*!< 33 DMA Channel 9 interrupt */ 101 MEC_DMA_CH10_IRQn = 34, /*!< 34 DMA Channel 10 interrupt */ 102 MEC_DMA_CH11_IRQn = 35, /*!< 35 DMA Channel 11 interrupt */ 103 MEC_DMA_CH12_IRQn = 36, /*!< 36 DMA Channel 12 interrupt */ 104 MEC_DMA_CH13_IRQn = 37, /*!< 37 DMA Channel 13 interrupt */ 105 MEC_DMA_CH14_IRQn = 38, /*!< 38 DMA Channel 14 interrupt */ 106 MEC_DMA_CH15_IRQn = 39, /*!< 39 DMA Channel 15 interrupt */ 107 MEC_UART0_IRQn = 40, /*!< 40 UART 0 interrupt */ 108 MEC_UART1_IRQn = 41, /*!< 41 UART 1 interrupt */ 109 MEC_EMI0_IRQn = 42, /*!< 42 EMI 0 interrupt */ 110 MEC_EMI1_IRQn = 43, /*!< 43 EMI 1 interrupt */ 111 MEC_EMI2_IRQn = 44, /*!< 44 EMI 2 interrupt */ 112 MEC_ACPI_EC0_IBF_IRQn = 45, /*!< 45 ACPI EC 0 IBF interrupt */ 113 MEC_ACPI_EC0_OBE_IRQn = 46, /*!< 46 ACPI EC 0 OBE interrupt */ 114 MEC_ACPI_EC1_IBF_IRQn = 47, /*!< 47 ACPI EC 1 IBF interrupt */ 115 MEC_ACPI_EC1_OBE_IRQn = 48, /*!< 48 ACPI EC 1 OBE interrupt */ 116 MEC_ACPI_EC2_IBF_IRQn = 49, /*!< 49 ACPI EC 2 IBF interrupt */ 117 MEC_ACPI_EC2_OBE_IRQn = 50, /*!< 50 ACPI EC 2 OBE interrupt */ 118 MEC_ACPI_EC3_IBF_IRQn = 51, /*!< 51 ACPI EC 3 IBF interrupt */ 119 MEC_ACPI_EC3_OBE_IRQn = 52, /*!< 52 ACPI EC 3 OBE interrupt */ 120 MEC_ACPI_EC4_IBF_IRQn = 53, /*!< 53 ACPI EC 4 IBF interrupt */ 121 MEC_ACPI_EC4_OBE_IRQn = 54, /*!< 54 ACPI EC 4 OBE interrupt */ 122 MEC_ACPI_PM1_CTL_IRQn = 55, /*!< 55 ACPI PM1 0 control interrupt */ 123 MEC_ACPI_PM1_EN_IRQn = 56, /*!< 56 ACPI PM1 0 enable interrupt */ 124 MEC_ACPI_PM1_STS_IRQn = 57, /*!< 57 ACPI PM1 0 status interrupt */ 125 MEC_KBC0_OBE_IRQn = 58, /*!< 58 KBC 0 output buffer empty interrupt */ 126 MEC_KBC0_IBF_IRQn = 59, /*!< 59 KBC 0 input buffer full interrupt */ 127 MEC_MBOX0_IRQn = 60, /*!< 60 Mailbox 0 interrupt */ 128 MEC_BDP0_IRQn = 62, /*!< 62 BDP 0 interrupt */ 129 MEC_PECI0_IRQn = 70, /*!< 70 PECI0 interrupt */ 130 MEC_TACH0_IRQn = 71, /*!< 71 TACH 0 interrupt */ 131 MEC_TACH1_IRQn = 72, /*!< 72 TACH 1 interrupt */ 132 MEC_TACH2_IRQn = 73, /*!< 73 TACH 2 interrupt */ 133 MEC_RPMFAN0_FAIL_IRQn = 74, /*!< 74 RPMFAN 0 fail interrupt */ 134 MEC_RPMFAN0_STALL_IRQn = 75, /*!< 75 RPMFAN 0 stall interrupt */ 135 MEC_RPMFAN1_FAIL_IRQn = 76, /*!< 76 RPMFAN 1 fail interrupt */ 136 MEC_RPMFAN1_STALL_IRQn = 77, /*!< 77 RPMFAN 1 stall interrupt */ 137 MEC_ADC0_SGL_IRQn = 78, /*!< 78 ADC Single(one-shot) conversion done interrupt */ 138 MEC_ADC0_RPT_IRQn = 79, /*!< 79 ADC Repeat conversion done interrupt */ 139 MEC_RCID0_IRQn = 80, /*!< 80 RC-ID 0 interrupt */ 140 MEC_RCID1_IRQn = 81, /*!< 81 RC-ID 1 interrupt */ 141 MEC_RCID2_IRQn = 82, /*!< 82 RC-ID 2 interrupt */ 142 MEC_BBLED0_IRQn = 83, /*!< 83 LED0 interrupt */ 143 MEC_BBLED1_IRQn = 84, /*!< 84 LED1 interrupt */ 144 MEC_BBLED2_IRQn = 85, /*!< 85 LED2 interrupt */ 145 MEC_BBLED3_IRQn = 86, /*!< 86 LED3 interrupt */ 146 MEC_PHOT_IRQn = 87, /*!< 87 PROCHOT interrupt */ 147 MEC_QSPI0_IRQn = 91, /*!< 91 QSPI0 controller interrupt */ 148 MEC_GSPI0_IRQn = 92, /*!< 92 GSPI v2 instance 0 interrupt */ 149 MEC_GSPI1_IRQn = 94, /*!< 94 GSPI v2 instance 1 interrupt */ 150 MEC_BCL0_ERR_IRQn = 96, /*!< 96 BC-Link 0 error interrupt */ 151 MEC_BCL0_BCLR_IRQn = 97, /*!< 97 BC-Link 0 busy clear interrupt */ 152 MEC_PS2CTL0_ACT_IRQn = 100, /*!< 100 PS2 Controller 0 Active interrupt */ 153 MEC_PS2CTL1_ACT_IRQn = 101, /*!< 101 PS2 Controller 1 Active interrupt */ 154 MEC_ESPI_PC_IRQn = 103, /*!< 103 eSPI IO Peripheral Channel interrupt */ 155 MEC_ESPI_BM1_IRQn = 104, /*!< 104 eSPI IO Bus Master 1 interrupt */ 156 MEC_ESPI_BM2_IRQn = 105, /*!< 105 eSPI IO Bus Master 2 interrupt */ 157 MEC_ESPI_LTR_IRQn = 106, /*!< 106 eSPI IO LTR interrupt */ 158 MEC_ESPI_OOB_UP_IRQn = 107, /*!< 107 eSPI IO OOB channel upstream transfer interrupt */ 159 MEC_ESPI_OOB_DN_IRQn = 108, /*!< 108 eSPI IO OOB channel downstream transfer interrupt */ 160 MEC_ESPI_FC_IRQn = 109, /*!< 109 eSPI IO Flash channel interrupt */ 161 MEC_ESPI_RST_IRQn = 110, /*!< 110 eSPI IO Edge detected on ESPI_RESET signal */ 162 MEC_RTMR0_IRQn = 111, /*!< 111 RTOS Timer 0 interrupt */ 163 MEC_HTMR0_IRQn = 112, /*!< 112 Hibernation timer 0 interrupt */ 164 MEC_HTMR1_IRQn = 113, /*!< 113 Hibernation timer 1 interrupt */ 165 MEC_WKTMR0_ALARM_IRQn = 114, /*!< 114 Week timer 0 alarm interrupt */ 166 MEC_WKTMR0_SUBWK_IRQn = 115, /*!< 115 Week timer 0 sub-week alarm interrupt */ 167 MEC_WKTMR0_ONESEC_IRQn = 116, /*!< 116 Week timer 0 one second alarm interrupt */ 168 MEC_WKTMR0_SUBSEC_IRQn = 117, /*!< 117 Week timer 0 sub-second alarm interrupt */ 169 MEC_WKTMR0_PWR_IRQn = 118, /*!< 118 Week timer 0 sys power present interrupt */ 170 MEC_RTC0_CLK_IRQn = 119, /*!< 119 RTC 0 clock interrupt */ 171 MEC_RTC0_ALARM_IRQn = 120, /*!< 120 RTC 0 alarm interrupt */ 172 MEC_VCI_OVRD_IN_IRQn = 121, /*!< 121 VCI0 override in interrupt */ 173 MEC_VCI_IN0_IRQn = 122, /*!< 122 VCI0 IN0 interrupt */ 174 MEC_VCI_IN1_IRQn = 123, /*!< 123 VCI0 IN1 interrupt */ 175 MEC_VCI_IN2_IRQn = 124, /*!< 124 VCI0 IN2 interrupt */ 176 MEC_VCI_IN3_IRQn = 125, /*!< 125 VCI0 IN3 interrupt */ 177 MEC_PS2CTL0_WK0A_IRQn = 129, /*!< 129 PS2 Controller 0 Wake 0A start bit detected interrupt */ 178 MEC_PS2CTL0_WK0B_IRQn = 130, /*!< 130 PS2 Controller Wake 0B start bit detected interrupt */ 179 MEC_PS2CTL1_WK1B_IRQn = 132, /*!< 132 PS2 Controller 1 Wake 0B start bit detected interrupt */ 180 MEC_KSCAN0_INT_IRQn = 135, /*!< 135 KSCAN interrupt */ 181 MEC_BTMR0_IRQn = 136, /*!< 136 Basic Timer 0 interrupt */ 182 MEC_BTMR1_IRQn = 137, /*!< 137 Basic Timer 1 interrupt */ 183 MEC_BTMR2_IRQn = 138, /*!< 138 Basic Timer 2 interrupt */ 184 MEC_BTMR3_IRQn = 139, /*!< 139 Basic Timer 3 interrupt */ 185 MEC_BTMR4_IRQn = 140, /*!< 140 Basic Timer 4 interrupt */ 186 MEC_BTMR5_IRQn = 141, /*!< 141 Basic Timer 5 interrupt */ 187 MEC_CTMR0_IRQn = 142, /*!< 142 Counter-Timer 0 interrupt */ 188 MEC_CTMR1_IRQn = 143, /*!< 143 16-bit Event Counter/Timer 1 interrupt */ 189 MEC_CTMR2_IRQn = 144, /*!< 144 16-bit Event Counter/Timer 2 interrupt */ 190 MEC_CTMR3_IRQn = 145, /*!< 145 16-bit Event Counter/Timer 3 interrupt */ 191 MEC_CCT0_TMR_IRQn = 146, /*!< 146 Capture and compare timer interrupt */ 192 MEC_CCT0_CAP0_IRQn = 147, /*!< 147 Capture and compare timer capture 0 interrupt */ 193 MEC_CCT0_CAP1_IRQn = 148, /*!< 148 Capture and compare timer capture 1 interrupt */ 194 MEC_CCT0_CAP2_IRQn = 149, /*!< 149 Capture and compare timer capture 2 interrupt */ 195 MEC_CCT0_CAP3_IRQn = 150, /*!< 150 Capture and compare timer capture 3 interrupt */ 196 MEC_CCT0_CAP4_IRQn = 151, /*!< 151 Capture and compare timer capture 4 interrupt */ 197 MEC_CCT0_CAP5_IRQn = 152, /*!< 152 Capture and compare timer capture 5 interrupt */ 198 MEC_CCT0_CMP0_IRQn = 153, /*!< 153 Capture and compare timer compare 0 interrupt */ 199 MEC_CCT0_CMP1_IRQn = 154, /*!< 154 Capture and compare timer compare 1 interrupt */ 200 MEC_EEPROM_CTRL0_IRQn = 155, /*!< 155 EEPROM Controller 0 interrupt */ 201 MEC_ESPI_VWEN_IRQn = 156, /*!< 156 eSPI IO Virtual Wire channel enable change interrupt */ 202 MEC_I2C_SMB4_IRQn = 158, /*!< 158 I2C_SMB4 interrupt */ 203 MEC_TACH3_IRQn = 159, /*!< 159 TACH 3 interrupt */ 204 MEC_ESPI_TAF_DONE_IRQn = 166, /*!< 166 eSPI TAF Done interrupt */ 205 MEC_ESPI_TAF_ERR_IRQn = 167, /*!< 167 eSPI TAF Error interrupt */ 206 MEC_WDT0_IRQn = 171, /*!< 171 Watch Dog timer 0 interrupt */ 207 MEC_GLUE_IRQn = 172, /*!< 172 Glue logic interrupt */ 208 MEC_PCR_CLKMON_IRQn = 174, /*!< 174 PCR 32KHz clock monitor */ 209 MEC_ACPI_EC0_IRQn = 175, /*!< 175 ACPI EC 0 combined interrupt. No GIRQ */ 210 MEC_ACPI_EC1_IRQn = 176, /*!< 176 ACPI EC 1 combined interrupt. No GIRQ */ 211 MEC_ACPI_EC2_IRQn = 177, /*!< 177 ACPI EC 2 combined interrupt. No GIRQ */ 212 MEC_ACPI_EC3_IRQn = 178, /*!< 178 ACPI EC 3 combined interrupt. No GIRQ */ 213 MEC_ACPI_EC4_IRQn = 179, /*!< 179 ACPI EC 4 combined interrupt. No GIRQ */ 214 MEC_ACPI_PM1_IRQn = 180, /*!< 180 ACPI PM1 combined interrupt. No GIRQ */ 215 MEC_I3C_HOST0_IRQn = 181, /*!< 181 I3C_HOST0 interrupt */ 216 MEC_I3C_SEC0_IRQn = 182, /*!< 182 I3C_SEC0 interrupt */ 217 MEC_UART2_IRQn = 183, /*!< 183 UART 2 interrupt */ 218 MEC_UART3_IRQn = 184, /*!< 184 UART 3 interrupt */ 219 MEC_USB_EP0_IRQn = 192, /*!< 192 USB Endpoint 0 interrupt */ 220 MEC_BRT0_IRQn = 193, /*!< 193 Boot-ROM Watch Dog timer 0 interrupt */ 221 MEC_DMA_CH16_IRQn = 194, /*!< 194 DMA Channel 16 interrupt */ 222 MEC_DMA_CH17_IRQn = 195, /*!< 195 DMA Channel 17 interrupt */ 223 MEC_DMA_CH18_IRQn = 196, /*!< 196 DMA Channel 18 interrupt */ 224 MEC_DMA_CH19_IRQn = 197 /*!< 197 DMA Channel 19 interrupt */ 225 } IRQn_Type; 226 227 228 229 /* =========================================================================================================================== */ 230 /* ================ Processor and Core Peripheral Section ================ */ 231 /* =========================================================================================================================== */ 232 233 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 234 #define __CM4_REV 0x0201U /*!< CM4 Core Revision */ 235 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 236 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 237 #define __MPU_PRESENT 1 /*!< MPU present */ 238 #define __FPU_PRESENT 1 /*!< FPU present */ 239 240 241 /** @} */ /* End of group Configuration_of_CMSIS */ 242 243 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 244 245 #ifndef __IM /*!< Fallback for older CMSIS versions */ 246 #define __IM __I 247 #endif 248 #ifndef __OM /*!< Fallback for older CMSIS versions */ 249 #define __OM __O 250 #endif 251 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 252 #define __IOM __IO 253 #endif 254 255 256 /* ======================================== Start of section using anonymous unions ======================================== */ 257 #if defined (__CC_ARM) 258 #pragma push 259 #pragma anon_unions 260 #elif defined (__ICCARM__) 261 #pragma language=extended 262 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 263 #pragma clang diagnostic push 264 #pragma clang diagnostic ignored "-Wc11-extensions" 265 #pragma clang diagnostic ignored "-Wreserved-id-macro" 266 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 267 #pragma clang diagnostic ignored "-Wnested-anon-types" 268 #elif defined (__GNUC__) 269 /* anonymous unions are enabled by default */ 270 #elif defined (__TMS470__) 271 /* anonymous unions are enabled by default */ 272 #elif defined (__TASKING__) 273 #pragma warning 586 274 #elif defined (__CSMC__) 275 /* anonymous unions are enabled by default */ 276 #else 277 #warning Not supported compiler type 278 #endif 279 280 #include <common/mec5_acpi_ec_v1.h> 281 #include <common/mec5_acpi_pm1_v1.h> 282 #include <common/mec5_adc_v2.h> 283 #include <common/mec5_bbled_v1.h> 284 #include <common/mec5_bcl_v1.h> 285 #include <common/mec5_bdp_v1.h> 286 #include <common/mec5_btmr_v1.h> 287 #include <common/mec5_cct_v1_1.h> 288 #include <common/mec5_chip_cfg_v1_2.h> 289 #include <common/mec5_cpu_stall_v1.h> 290 #include <common/mec5_ctmr_v1.h> 291 #include <common/mec5_dmac_ch20_v2.h> 292 #include <common/mec5_ecia_v1_5.h> 293 #include <common/mec5_ecs_v2_5.h> 294 #include <common/mec5_eeprom_ctrl_v1.h> 295 #include <common/mec5_emi_v2.h> 296 #include <common/mec5_espi_io_v1_5.h> 297 #include <common/mec5_espi_mem_v1_5.h> 298 #include <common/mec5_espi_taf_v1_5.h> 299 #include <common/mec5_espi_vw_v1_5.h> 300 #include <common/mec5_gluelog_v1.h> 301 #include <common/mec5_gpio_8f_6port_v1_5.h> 302 #include <common/mec5_gspi_v2.h> 303 #include <common/mec5_htmr_v1.h> 304 #include <common/mec5_i2c_smb_v3_8.h> 305 #include <common/mec5_i3c_host_v2.h> 306 #include <common/mec5_i3c_sec_v2.h> 307 #include <common/mec5_kbc_v1.h> 308 #include <common/mec5_kscan_v1.h> 309 #include <common/mec5_mbox_v1.h> 310 #include <common/mec5_pcr_v2_1.h> 311 #include <common/mec5_peci_v1.h> 312 #include <common/mec5_port92_v1.h> 313 #include <common/mec5_prochot_v1.h> 314 #include <common/mec5_ps2_v1.h> 315 #include <common/mec5_pwm_v1.h> 316 #include <common/mec5_qspi_v2_1.h> 317 #include <common/mec5_rcid_v1.h> 318 #include <common/mec5_rpmfan_v1.h> 319 #include <common/mec5_rtc_v1.h> 320 #include <common/mec5_rtmr_v1.h> 321 #include <common/mec5_tach_v1.h> 322 #include <common/mec5_tfdp_v1.h> 323 #include <common/mec5_uart_v1_5.h> 324 #include <common/mec5_usb_ep_v2.h> 325 #include <common/mec5_vbat_mem_128b_v1.h> 326 #include <common/mec5_vbatr_v1_5.h> 327 #include <common/mec5_vci_v1_5.h> 328 #include <common/mec5_wdt_v2.h> 329 #include <common/mec5_wktmr_bgpo_v1.h> 330 331 /* =========================================================================================================================== */ 332 /* ================ Device Specific Peripheral Address Map ================ */ 333 /* =========================================================================================================================== */ 334 335 336 /** @addtogroup Device_Peripheral_peripheralAddr 337 * @{ 338 */ 339 340 #define MEC_CPU_STALL_BASE 0x08000000UL 341 #define MEC_WDT0_BASE 0x40000400UL 342 #define MEC_BRT0_BASE 0x40000420UL 343 #define MEC_BTMR0_BASE 0x40000C00UL 344 #define MEC_BTMR1_BASE 0x40000C20UL 345 #define MEC_BTMR2_BASE 0x40000C40UL 346 #define MEC_BTMR3_BASE 0x40000C60UL 347 #define MEC_BTMR4_BASE 0x40000C80UL 348 #define MEC_BTMR5_BASE 0x40000CA0UL 349 #define MEC_CTMR0_BASE 0x40000D00UL 350 #define MEC_CTMR1_BASE 0x40000D20UL 351 #define MEC_CTMR2_BASE 0x40000D40UL 352 #define MEC_CTMR3_BASE 0x40000D60UL 353 #define MEC_CCT0_BASE 0x40001000UL 354 #define MEC_RCID0_BASE 0x40001400UL 355 #define MEC_RCID1_BASE 0x40001480UL 356 #define MEC_RCID2_BASE 0x40001500UL 357 #define MEC_DMAC_BASE 0x40002400UL 358 #define MEC_EEPROM_CTRL0_BASE 0x40002C00UL 359 #define MEC_PROCHOT_BASE 0x40003400UL 360 #define MEC_I2C_SMB0_BASE 0x40004000UL 361 #define MEC_I2C_SMB1_BASE 0x40004400UL 362 #define MEC_I2C_SMB2_BASE 0x40004800UL 363 #define MEC_I2C_SMB3_BASE 0x40004C00UL 364 #define MEC_I2C_SMB4_BASE 0x40005000UL 365 #define MEC_PWM0_BASE 0x40005800UL 366 #define MEC_PWM1_BASE 0x40005810UL 367 #define MEC_PWM2_BASE 0x40005820UL 368 #define MEC_PWM3_BASE 0x40005830UL 369 #define MEC_PWM4_BASE 0x40005840UL 370 #define MEC_PWM5_BASE 0x40005850UL 371 #define MEC_PWM6_BASE 0x40005860UL 372 #define MEC_PWM7_BASE 0x40005870UL 373 #define MEC_PWM8_BASE 0x40005880UL 374 #define MEC_TACH0_BASE 0x40006000UL 375 #define MEC_TACH1_BASE 0x40006010UL 376 #define MEC_TACH2_BASE 0x40006020UL 377 #define MEC_TACH3_BASE 0x40006030UL 378 #define MEC_PECI0_BASE 0x40006400UL 379 #define MEC_RTMR0_BASE 0x40007400UL 380 #define MEC_USB_EP0_BASE 0x40007800UL 381 #define MEC_ADC0_BASE 0x40007C00UL 382 #define MEC_ESPI_TAF_COMM_BASE 0x40071000UL 383 #define MEC_ESPI_TAF_BASE 0x40008000UL 384 #define MEC_TFDP0_BASE 0x40008C00UL 385 #define MEC_PS2CTL0_BASE 0x40009000UL 386 #define MEC_PS2CTL1_BASE 0x40009040UL 387 #define MEC_GSPI0_BASE 0x40009400UL 388 #define MEC_GSPI1_BASE 0x40009480UL 389 #define MEC_HTMR0_BASE 0x40009800UL 390 #define MEC_HTMR1_BASE 0x40009820UL 391 #define MEC_KSCAN0_BASE 0x40009C00UL 392 #define MEC_RPMFAN0_BASE 0x4000A000UL 393 #define MEC_RPMFAN1_BASE 0x4000A080UL 394 #define MEC_VBATR_BASE 0x4000A400UL 395 #define MEC_VBATM_BASE 0x4000A800UL 396 #define MEC_WKTMR0_BASE 0x4000AC80UL 397 #define MEC_VCI_BASE 0x4000AE00UL 398 #define MEC_BBLED0_BASE 0x4000B800UL 399 #define MEC_BBLED1_BASE 0x4000B900UL 400 #define MEC_BBLED2_BASE 0x4000BA00UL 401 #define MEC_BBLED3_BASE 0x4000BB00UL 402 #define MEC_BCL0_BASE 0x4000CD00UL 403 #define MEC_ECIA0_BASE 0x4000E000UL 404 #define MEC_ECS_BASE 0x4000FC00UL 405 #define MEC_I3C_SEC0_BASE 0x40010000UL 406 #define MEC_I3C_HOST0_BASE 0x40010800UL 407 #define MEC_QSPI0_BASE 0x40070000UL 408 #define MEC_PCR_BASE 0x40080100UL 409 #define MEC_GPIO_BASE 0x40081000UL 410 #define MEC_MBOX0_BASE 0x400F0000UL 411 #define MEC_KBC0_BASE 0x400F0400UL 412 #define MEC_ACPI_EC0_BASE 0x400F0800UL 413 #define MEC_ACPI_EC1_BASE 0x400F0C00UL 414 #define MEC_ACPI_EC2_BASE 0x400F1000UL 415 #define MEC_ACPI_EC3_BASE 0x400F1400UL 416 #define MEC_ACPI_EC4_BASE 0x400F1800UL 417 #define MEC_ACPI_PM1_BASE 0x400F1C00UL 418 #define MEC_PORT92_BASE 0x400F2000UL 419 #define MEC_UART0_BASE 0x400F2400UL 420 #define MEC_UART1_BASE 0x400F2800UL 421 #define MEC_UART2_BASE 0x400F2C00UL 422 #define MEC_UART3_BASE 0x400F3000UL 423 #define MEC_GLUE_BASE 0x400F3C00UL 424 #define MEC_EMI0_BASE 0x400F4000UL 425 #define MEC_EMI1_BASE 0x400F4400UL 426 #define MEC_EMI2_BASE 0x400F4800UL 427 #define MEC_RTC0_BASE 0x400F5000UL 428 #define MEC_BDP0_BASE 0x400F8000UL 429 #define MEC_CHIP_CFG_BASE 0x400FFF00UL 430 #define MEC_ESPI_IO_BASE 0x400F3400UL 431 #define MEC_ESPI_MEM_BASE 0x400F3800UL 432 #define MEC_ESPI_VW_BASE 0x400F9C00UL 433 434 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 435 436 437 /* =========================================================================================================================== */ 438 /* ================ Peripheral declaration ================ */ 439 /* =========================================================================================================================== */ 440 441 442 /** @addtogroup Device_Peripheral_declaration 443 * @{ 444 */ 445 446 #define MEC_CPU_STALL ((MEC_CPU_STALL_Type*) MEC_CPU_STALL_BASE) 447 #define MEC_WDT0 ((MEC_WDT_Type*) MEC_WDT0_BASE) 448 #define MEC_BRT0 ((MEC_BRT_Type*) MEC_BRT0_BASE) 449 #define MEC_BTMR0 ((MEC_BTMR_Type*) MEC_BTMR0_BASE) 450 #define MEC_BTMR1 ((MEC_BTMR_Type*) MEC_BTMR1_BASE) 451 #define MEC_BTMR2 ((MEC_BTMR_Type*) MEC_BTMR2_BASE) 452 #define MEC_BTMR3 ((MEC_BTMR_Type*) MEC_BTMR3_BASE) 453 #define MEC_BTMR4 ((MEC_BTMR_Type*) MEC_BTMR4_BASE) 454 #define MEC_BTMR5 ((MEC_BTMR_Type*) MEC_BTMR5_BASE) 455 #define MEC_CTMR0 ((MEC_CTMR_Type*) MEC_CTMR0_BASE) 456 #define MEC_CTMR1 ((MEC_CTMR_Type*) MEC_CTMR1_BASE) 457 #define MEC_CTMR2 ((MEC_CTMR_Type*) MEC_CTMR2_BASE) 458 #define MEC_CTMR3 ((MEC_CTMR_Type*) MEC_CTMR3_BASE) 459 #define MEC_CCT0 ((MEC_CCT_Type*) MEC_CCT0_BASE) 460 #define MEC_RCID0 ((MEC_RCID_Type*) MEC_RCID0_BASE) 461 #define MEC_RCID1 ((MEC_RCID_Type*) MEC_RCID1_BASE) 462 #define MEC_RCID2 ((MEC_RCID_Type*) MEC_RCID2_BASE) 463 #define MEC_DMAC ((MEC_DMAC_Type*) MEC_DMAC_BASE) 464 #define MEC_EEPROM_CTRL0 ((MEC_EEPROM_CTRL_Type*) MEC_EEPROM_CTRL0_BASE) 465 #define MEC_PROCHOT ((MEC_PHOT_Type*) MEC_PROCHOT_BASE) 466 #define MEC_I2C_SMB0 ((MEC_I2C_SMB_Type*) MEC_I2C_SMB0_BASE) 467 #define MEC_I2C_SMB1 ((MEC_I2C_SMB_Type*) MEC_I2C_SMB1_BASE) 468 #define MEC_I2C_SMB2 ((MEC_I2C_SMB_Type*) MEC_I2C_SMB2_BASE) 469 #define MEC_I2C_SMB3 ((MEC_I2C_SMB_Type*) MEC_I2C_SMB3_BASE) 470 #define MEC_I2C_SMB4 ((MEC_I2C_SMB_Type*) MEC_I2C_SMB4_BASE) 471 #define MEC_PWM0 ((MEC_PWM_Type*) MEC_PWM0_BASE) 472 #define MEC_PWM1 ((MEC_PWM_Type*) MEC_PWM1_BASE) 473 #define MEC_PWM2 ((MEC_PWM_Type*) MEC_PWM2_BASE) 474 #define MEC_PWM3 ((MEC_PWM_Type*) MEC_PWM3_BASE) 475 #define MEC_PWM4 ((MEC_PWM_Type*) MEC_PWM4_BASE) 476 #define MEC_PWM5 ((MEC_PWM_Type*) MEC_PWM5_BASE) 477 #define MEC_PWM6 ((MEC_PWM_Type*) MEC_PWM6_BASE) 478 #define MEC_PWM7 ((MEC_PWM_Type*) MEC_PWM7_BASE) 479 #define MEC_PWM8 ((MEC_PWM_Type*) MEC_PWM8_BASE) 480 #define MEC_TACH0 ((MEC_TACH_Type*) MEC_TACH0_BASE) 481 #define MEC_TACH1 ((MEC_TACH_Type*) MEC_TACH1_BASE) 482 #define MEC_TACH2 ((MEC_TACH_Type*) MEC_TACH2_BASE) 483 #define MEC_TACH3 ((MEC_TACH_Type*) MEC_TACH3_BASE) 484 #define MEC_PECI0 ((MEC_PECI_Type*) MEC_PECI0_BASE) 485 #define MEC_RTMR0 ((MEC_RTMR_Type*) MEC_RTMR0_BASE) 486 #define MEC_USB_EP0 ((MEC_USB_EP_Type*) MEC_USB_EP0_BASE) 487 #define MEC_ADC0 ((MEC_ADC_Type*) MEC_ADC0_BASE) 488 #define MEC_ESPI_TAF_COMM ((MEC_ESPI_TAF_COMM_Type*) MEC_ESPI_TAF_COMM_BASE) 489 #define MEC_ESPI_TAF ((MEC_ESPI_TAF_Type*) MEC_ESPI_TAF_BASE) 490 #define MEC_TFDP0 ((MEC_TFDP_Type*) MEC_TFDP0_BASE) 491 #define MEC_PS2CTL0 ((MEC_PS2_Type*) MEC_PS2CTL0_BASE) 492 #define MEC_PS2CTL1 ((MEC_PS2_Type*) MEC_PS2CTL1_BASE) 493 #define MEC_GSPI0 ((MEC_GSPI_Type*) MEC_GSPI0_BASE) 494 #define MEC_GSPI1 ((MEC_GSPI_Type*) MEC_GSPI1_BASE) 495 #define MEC_HTMR0 ((MEC_HTMR_Type*) MEC_HTMR0_BASE) 496 #define MEC_HTMR1 ((MEC_HTMR_Type*) MEC_HTMR1_BASE) 497 #define MEC_KSCAN0 ((MEC_KSCAN_Type*) MEC_KSCAN0_BASE) 498 #define MEC_RPMFAN0 ((MEC_RPMFAN_Type*) MEC_RPMFAN0_BASE) 499 #define MEC_RPMFAN1 ((MEC_RPMFAN_Type*) MEC_RPMFAN1_BASE) 500 #define MEC_VBATR ((MEC_VBATR_Type*) MEC_VBATR_BASE) 501 #define MEC_VBATM ((MEC_VBATM_Type*) MEC_VBATM_BASE) 502 #define MEC_WKTMR0 ((MEC_WKTMR_Type*) MEC_WKTMR0_BASE) 503 #define MEC_VCI ((MEC_VCI_Type*) MEC_VCI_BASE) 504 #define MEC_BBLED0 ((MEC_BBLED_Type*) MEC_BBLED0_BASE) 505 #define MEC_BBLED1 ((MEC_BBLED_Type*) MEC_BBLED1_BASE) 506 #define MEC_BBLED2 ((MEC_BBLED_Type*) MEC_BBLED2_BASE) 507 #define MEC_BBLED3 ((MEC_BBLED_Type*) MEC_BBLED3_BASE) 508 #define MEC_BCL0 ((MEC_BCL_Type*) MEC_BCL0_BASE) 509 #define MEC_ECIA0 ((MEC_ECIA_Type*) MEC_ECIA0_BASE) 510 #define MEC_ECS ((MEC_ECS_Type*) MEC_ECS_BASE) 511 #define MEC_I3C_SEC0 ((MEC_I3C_SEC_Type*) MEC_I3C_SEC0_BASE) 512 #define MEC_I3C_HOST0 ((MEC_I3C_HOST_Type*) MEC_I3C_HOST0_BASE) 513 #define MEC_QSPI0 ((MEC_QSPI_Type*) MEC_QSPI0_BASE) 514 #define MEC_PCR ((MEC_PCR_Type*) MEC_PCR_BASE) 515 #define MEC_GPIO ((MEC_GPIO_Type*) MEC_GPIO_BASE) 516 #define MEC_MBOX0 ((MEC_MBOX_Type*) MEC_MBOX0_BASE) 517 #define MEC_KBC0 ((MEC_KBC_Type*) MEC_KBC0_BASE) 518 #define MEC_ACPI_EC0 ((MEC_ACPI_EC_Type*) MEC_ACPI_EC0_BASE) 519 #define MEC_ACPI_EC1 ((MEC_ACPI_EC_Type*) MEC_ACPI_EC1_BASE) 520 #define MEC_ACPI_EC2 ((MEC_ACPI_EC_Type*) MEC_ACPI_EC2_BASE) 521 #define MEC_ACPI_EC3 ((MEC_ACPI_EC_Type*) MEC_ACPI_EC3_BASE) 522 #define MEC_ACPI_EC4 ((MEC_ACPI_EC_Type*) MEC_ACPI_EC4_BASE) 523 #define MEC_ACPI_PM1 ((MEC_ACPI_PM1_Type*) MEC_ACPI_PM1_BASE) 524 #define MEC_PORT92 ((MEC_PORT92_Type*) MEC_PORT92_BASE) 525 #define MEC_UART0 ((MEC_UART_Type*) MEC_UART0_BASE) 526 #define MEC_UART1 ((MEC_UART_Type*) MEC_UART1_BASE) 527 #define MEC_UART2 ((MEC_UART_Type*) MEC_UART2_BASE) 528 #define MEC_UART3 ((MEC_UART_Type*) MEC_UART3_BASE) 529 #define MEC_GLUE ((MEC_GLUE_Type*) MEC_GLUE_BASE) 530 #define MEC_EMI0 ((MEC_EMI_Type*) MEC_EMI0_BASE) 531 #define MEC_EMI1 ((MEC_EMI_Type*) MEC_EMI1_BASE) 532 #define MEC_EMI2 ((MEC_EMI_Type*) MEC_EMI2_BASE) 533 #define MEC_RTC0 ((MEC_RTC_Type*) MEC_RTC0_BASE) 534 #define MEC_BDP0 ((MEC_BDP_Type*) MEC_BDP0_BASE) 535 #define MEC_CHIP_CFG ((MEC_CHIP_CFG_Type*) MEC_CHIP_CFG_BASE) 536 #define MEC_ESPI_IO ((MEC_ESPI_IO_Type*) MEC_ESPI_IO_BASE) 537 #define MEC_ESPI_MEM ((MEC_ESPI_MEM_Type*) MEC_ESPI_MEM_BASE) 538 #define MEC_ESPI_VW ((MEC_ESPI_VW_Type*) MEC_ESPI_VW_BASE) 539 540 /** @} */ /* End of group Device_Peripheral_declaration */ 541 542 543 /* ========================================= End of section using anonymous unions ========================================= */ 544 #if defined (__CC_ARM) 545 #pragma pop 546 #elif defined (__ICCARM__) 547 /* leave anonymous unions enabled */ 548 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 549 #pragma clang diagnostic pop 550 #elif defined (__GNUC__) 551 /* anonymous unions are enabled by default */ 552 #elif defined (__TMS470__) 553 /* anonymous unions are enabled by default */ 554 #elif defined (__TASKING__) 555 #pragma warning restore 556 #elif defined (__CSMC__) 557 /* anonymous unions are enabled by default */ 558 #endif 559 560 #ifdef __cplusplus 561 } 562 #endif 563 564 #endif /* MEC1753_QSZ_H */ 565 566 567 /** @} */ /* End of group MEC1753_QSZ */ 568 569 /** @} */ /* End of group Microchip Technolgy Inc. */ 570
