1 /*******************************************************************************
2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * MPFS HAL Embedded Software
7 *
8 */
9
10 /*******************************************************************************
11 *
12 * @file mss_plic.h
13 * @author Microchip-FPGA Embedded Systems Solutions
14 * @brief PolarFire SoC MSS PLIC and PRCI access data structures and functions.
15 *
16 * Definitions and functions associated with PLIC interrupts.
17 *
18 */
19 #ifndef MSS_PLIC_H
20 #define MSS_PLIC_H
21
22 #include <stdint.h>
23 #ifndef CONFIG_OPENSBI
24 #include "encoding.h"
25 #endif
26
27 #include "mss_assert.h"
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /*
34 *Return value from External IRQ handler. This will be used to disable the
35 *Return External interrupt.
36 */
37 #define EXT_IRQ_KEEP_ENABLED 0U
38 #define EXT_IRQ_DISABLE 1U
39
40 /*------------------------------------------------------------------------------
41 *
42 */
43 #ifndef SIFIVE_HIFIVE_UNLEASHED
44 uint8_t Invalid_IRQHandler(void);
45 uint8_t l2_metadata_corr_IRQHandler(void);
46 uint8_t l2_metadata_uncorr_IRQHandler(void);
47 uint8_t l2_data_corr_IRQHandler(void);
48 uint8_t l2_data_uncorr_IRQHandler(void);
49 uint8_t dma_ch0_DONE_IRQHandler(void);
50 uint8_t dma_ch0_ERR_IRQHandler(void);
51 uint8_t dma_ch1_DONE_IRQHandler(void);
52 uint8_t dma_ch1_ERR_IRQHandler(void);
53 uint8_t dma_ch2_DONE_IRQHandler(void);
54 uint8_t dma_ch2_ERR_IRQHandler(void);
55 uint8_t dma_ch3_DONE_IRQHandler(void);
56 uint8_t dma_ch3_ERR_IRQHandler(void);
57 uint8_t gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler(void);
58 uint8_t gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler(void);
59 uint8_t gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler(void);
60 uint8_t gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler(void);
61 uint8_t gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler(void);
62 uint8_t gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler(void);
63 uint8_t gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler(void);
64 uint8_t gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler(void);
65 uint8_t gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler(void);
66 uint8_t gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler(void);
67 uint8_t gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler(void);
68 uint8_t gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler(void);
69 uint8_t gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler(void);
70
71 uint8_t gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler(void);
72 uint8_t gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler(void);
73 uint8_t gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler(void);
74 uint8_t gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler(void);
75 uint8_t gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler(void);
76 uint8_t gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler(void);
77 uint8_t gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler(void);
78 uint8_t gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler(void);
79 uint8_t gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler(void);
80 uint8_t gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler(void);
81 uint8_t gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler(void);
82 uint8_t gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler(void);
83 uint8_t gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler(void);
84 uint8_t gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler(void);
85 uint8_t gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler(void);
86
87 uint8_t gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler(void);
88 uint8_t gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler(void);
89 uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void);
90 uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void);
91
92 uint8_t gpio1_bit18_plic_32_IRQHandler(void);
93 uint8_t gpio1_bit19_plic_33_IRQHandler(void);
94 uint8_t gpio1_bit20_plic_34_IRQHandler(void);
95 uint8_t gpio1_bit21_plic_35_IRQHandler(void);
96 uint8_t gpio1_bit22_plic_36_IRQHandler(void);
97 uint8_t gpio1_bit23_plic_37_IRQHandler(void);
98
99 uint8_t gpio0_non_direct_plic_IRQHandler(void);
100 uint8_t gpio1_non_direct_plic_IRQHandler(void);
101 uint8_t gpio2_non_direct_plic_IRQHandler(void);
102
103 uint8_t spi0_plic_IRQHandler(void);
104 uint8_t spi1_plic_IRQHandler(void);
105 uint8_t external_can0_plic_IRQHandler(void);
106 uint8_t can1_IRQHandler(void);
107 uint8_t External_i2c0_main_plic_IRQHandler(void);
108 uint8_t External_i2c0_alert_plic_IRQHandler(void);
109 uint8_t i2c0_sus_plic_IRQHandler(void);
110 uint8_t i2c1_main_plic_IRQHandler(void);
111 uint8_t i2c1_alert_plic_IRQHandler(void);
112 uint8_t i2c1_sus_plic_IRQHandler(void);
113 uint8_t mac0_int_plic_IRQHandler(void);
114 uint8_t mac0_queue1_plic_IRQHandler(void);
115 uint8_t mac0_queue2_plic_IRQHandler(void);
116 uint8_t mac0_queue3_plic_IRQHandler(void);
117 uint8_t mac0_emac_plic_IRQHandler(void);
118 uint8_t mac0_mmsl_plic_IRQHandler(void);
119 uint8_t mac1_int_plic_IRQHandler(void);
120 uint8_t mac1_queue1_plic_IRQHandler(void);
121 uint8_t mac1_queue2_plic_IRQHandler(void);
122 uint8_t mac1_queue3_plic_IRQHandler(void);
123 uint8_t mac1_emac_plic_IRQHandler(void);
124 uint8_t mac1_mmsl_plic_IRQHandler(void);
125 uint8_t ddrc_train_plic_IRQHandler(void);
126 uint8_t scb_interrupt_plic_IRQHandler(void);
127 uint8_t ecc_error_plic_IRQHandler(void);
128 uint8_t ecc_correct_plic_IRQHandler(void);
129 uint8_t rtc_wakeup_plic_IRQHandler(void);
130 uint8_t rtc_match_plic_IRQHandler(void);
131 uint8_t timer1_plic_IRQHandler(void);
132 uint8_t timer2_plic_IRQHandler(void);
133 uint8_t envm_plic_IRQHandler(void);
134 uint8_t qspi_plic_IRQHandler(void);
135 uint8_t usb_dma_plic_IRQHandler(void);
136 uint8_t usb_mc_plic_IRQHandler(void);
137 uint8_t mmc_main_plic_IRQHandler(void);
138 uint8_t mmc_wakeup_plic_IRQHandler(void);
139 uint8_t mmuart0_plic_77_IRQHandler(void);
140 uint8_t mmuart1_plic_IRQHandler(void);
141 uint8_t mmuart2_plic_IRQHandler(void);
142 uint8_t mmuart3_plic_IRQHandler(void);
143 uint8_t mmuart4_plic_IRQHandler(void);
144 uint8_t g5c_devrst_plic_IRQHandler(void);
145 uint8_t g5c_message_plic_IRQHandler(void);
146 uint8_t usoc_vc_interrupt_plic_IRQHandler(void);
147 uint8_t usoc_smb_interrupt_plic_IRQHandler(void);
148 uint8_t e51_0_Maintence_plic_IRQHandler(void);
149
150 uint8_t wdog0_mvrp_plic_IRQHandler(void);
151 uint8_t wdog1_mvrp_plic_IRQHandler(void);
152 uint8_t wdog2_mvrp_plic_IRQHandler(void);
153 uint8_t wdog3_mvrp_plic_IRQHandler(void);
154 uint8_t wdog4_mvrp_plic_IRQHandler(void);
155 uint8_t wdog0_tout_plic_IRQHandler(void);
156 uint8_t wdog1_tout_plic_IRQHandler(void);
157 uint8_t wdog2_tout_plic_IRQHandler(void);
158 uint8_t wdog3_tout_plic_IRQHandler(void);
159 uint8_t wdog4_tout_plic_IRQHandler(void);
160 uint8_t g5c_mss_spi_plic_IRQHandler(void);
161 uint8_t volt_temp_alarm_plic_IRQHandler(void);
162
163 uint8_t athena_complete_plic_IRQHandler(void);
164 uint8_t athena_alarm_plic_IRQHandler(void);
165 uint8_t athena_bus_error_plic_IRQHandler(void);
166 uint8_t usoc_axic_us_plic_IRQHandler(void);
167 uint8_t usoc_axic_ds_plic_IRQHandler(void);
168
169 uint8_t reserved_104_plic_IRQHandler(void);
170
171 uint8_t fabric_f2h_0_plic_IRQHandler(void);
172 uint8_t fabric_f2h_1_plic_IRQHandler(void);
173 uint8_t fabric_f2h_2_plic_IRQHandler(void);
174 uint8_t fabric_f2h_3_plic_IRQHandler(void);
175 uint8_t fabric_f2h_4_plic_IRQHandler(void);
176 uint8_t fabric_f2h_5_plic_IRQHandler(void);
177 uint8_t fabric_f2h_6_plic_IRQHandler(void);
178 uint8_t fabric_f2h_7_plic_IRQHandler(void);
179 uint8_t fabric_f2h_8_plic_IRQHandler(void);
180 uint8_t fabric_f2h_9_plic_IRQHandler(void);
181
182 uint8_t fabric_f2h_10_plic_IRQHandler(void);
183 uint8_t fabric_f2h_11_plic_IRQHandler(void);
184 uint8_t fabric_f2h_12_plic_IRQHandler(void);
185 uint8_t fabric_f2h_13_plic_IRQHandler(void);
186 uint8_t fabric_f2h_14_plic_IRQHandler(void);
187 uint8_t fabric_f2h_15_plic_IRQHandler(void);
188 uint8_t fabric_f2h_16_plic_IRQHandler(void);
189 uint8_t fabric_f2h_17_plic_IRQHandler(void);
190 uint8_t fabric_f2h_18_plic_IRQHandler(void);
191 uint8_t fabric_f2h_19_plic_IRQHandler(void);
192
193 uint8_t fabric_f2h_20_plic_IRQHandler(void);
194 uint8_t fabric_f2h_21_plic_IRQHandler(void);
195 uint8_t fabric_f2h_22_plic_IRQHandler(void);
196 uint8_t fabric_f2h_23_plic_IRQHandler(void);
197 uint8_t fabric_f2h_24_plic_IRQHandler(void);
198 uint8_t fabric_f2h_25_plic_IRQHandler(void);
199 uint8_t fabric_f2h_26_plic_IRQHandler(void);
200 uint8_t fabric_f2h_27_plic_IRQHandler(void);
201 uint8_t fabric_f2h_28_plic_IRQHandler(void);
202 uint8_t fabric_f2h_29_plic_IRQHandler(void);
203
204 uint8_t fabric_f2h_30_plic_IRQHandler(void);
205 uint8_t fabric_f2h_31_plic_IRQHandler(void);
206
207 uint8_t fabric_f2h_32_plic_IRQHandler(void);
208 uint8_t fabric_f2h_33_plic_IRQHandler(void);
209 uint8_t fabric_f2h_34_plic_IRQHandler(void);
210 uint8_t fabric_f2h_35_plic_IRQHandler(void);
211 uint8_t fabric_f2h_36_plic_IRQHandler(void);
212 uint8_t fabric_f2h_37_plic_IRQHandler(void);
213 uint8_t fabric_f2h_38_plic_IRQHandler(void);
214 uint8_t fabric_f2h_39_plic_IRQHandler(void);
215 uint8_t fabric_f2h_40_plic_IRQHandler(void);
216 uint8_t fabric_f2h_41_plic_IRQHandler(void);
217
218 uint8_t fabric_f2h_42_plic_IRQHandler(void);
219 uint8_t fabric_f2h_43_plic_IRQHandler(void);
220 uint8_t fabric_f2h_44_plic_IRQHandler(void);
221 uint8_t fabric_f2h_45_plic_IRQHandler(void);
222 uint8_t fabric_f2h_46_plic_IRQHandler(void);
223 uint8_t fabric_f2h_47_plic_IRQHandler(void);
224 uint8_t fabric_f2h_48_plic_IRQHandler(void);
225 uint8_t fabric_f2h_49_plic_IRQHandler(void);
226 uint8_t fabric_f2h_50_plic_IRQHandler(void);
227 uint8_t fabric_f2h_51_plic_IRQHandler(void);
228
229 uint8_t fabric_f2h_52_plic_IRQHandler(void);
230 uint8_t fabric_f2h_53_plic_IRQHandler(void);
231 uint8_t fabric_f2h_54_plic_IRQHandler(void);
232 uint8_t fabric_f2h_55_plic_IRQHandler(void);
233 uint8_t fabric_f2h_56_plic_IRQHandler(void);
234 uint8_t fabric_f2h_57_plic_IRQHandler(void);
235 uint8_t fabric_f2h_58_plic_IRQHandler(void);
236 uint8_t fabric_f2h_59_plic_IRQHandler(void);
237 uint8_t fabric_f2h_60_plic_IRQHandler(void);
238 uint8_t fabric_f2h_61_plic_IRQHandler(void);
239
240 uint8_t fabric_f2h_62_plic_IRQHandler(void);
241 uint8_t fabric_f2h_63_plic_IRQHandler(void);
242
243 uint8_t bus_error_unit_hart_0_plic_IRQHandler(void);
244 uint8_t bus_error_unit_hart_1_plic_IRQHandler(void);
245 uint8_t bus_error_unit_hart_2_plic_IRQHandler(void);
246 uint8_t bus_error_unit_hart_3_plic_IRQHandler(void);
247 uint8_t bus_error_unit_hart_4_plic_IRQHandler(void);
248
249
250 #else
251 uint8_t Invalid_IRQHandler(void);
252 uint8_t External_1_IRQHandler(void);
253 uint8_t External_2_IRQHandler(void);
254 uint8_t External_3_IRQHandler(void);
255 uint8_t USART0_plic_4_IRQHandler(void);
256 uint8_t External_5_IRQHandler(void);
257 uint8_t External_6_IRQHandler(void);
258 uint8_t External_7_IRQHandler(void);
259 uint8_t External_8_IRQHandler(void);
260 uint8_t External_9_IRQHandler(void);
261 uint8_t External_10_IRQHandler(void);
262 uint8_t External_11_IRQHandler(void);
263 uint8_t External_12_IRQHandler(void);
264 uint8_t External_13_IRQHandler(void);
265 uint8_t External_14_IRQHandler(void);
266 uint8_t External_15_IRQHandler(void);
267 uint8_t External_16_IRQHandler(void);
268 uint8_t External_17_IRQHandler(void);
269 uint8_t External_18_IRQHandler(void);
270 uint8_t External_19_IRQHandler(void);
271 uint8_t External_20_IRQHandler(void);
272 uint8_t External_21_IRQHandler(void);
273 uint8_t External_22_IRQHandler(void);
274 uint8_t dma_ch0_DONE_IRQHandler(void);
275 uint8_t dma_ch0_ERR_IRQHandler(void);
276 uint8_t dma_ch1_DONE_IRQHandler(void);
277 uint8_t dma_ch1_ERR_IRQHandler(void);
278 uint8_t dma_ch2_DONE_IRQHandler(void);
279 uint8_t dma_ch2_ERR_IRQHandler(void);
280 uint8_t dma_ch3_DONE_IRQHandler(void);
281 uint8_t dma_ch3_ERR_IRQHandler(void);
282 uint8_t External_31_IRQHandler(void);
283 uint8_t External_32_IRQHandler(void);
284 uint8_t External_33_IRQHandler(void);
285 uint8_t External_34_IRQHandler(void);
286 uint8_t External_35_IRQHandler(void);
287 uint8_t External_36_IRQHandler(void);
288 uint8_t External_37_IRQHandler(void);
289 uint8_t External_38_IRQHandler(void);
290 uint8_t External_39_IRQHandler(void);
291 uint8_t External_40_IRQHandler(void);
292 uint8_t External_41_IRQHandler(void);
293 uint8_t External_42_IRQHandler(void);
294 uint8_t External_43_IRQHandler(void);
295 uint8_t External_44_IRQHandler(void);
296 uint8_t External_45_IRQHandler(void);
297 uint8_t External_46_IRQHandler(void);
298 uint8_t External_47_IRQHandler(void);
299 uint8_t External_48_IRQHandler(void);
300 uint8_t External_49_IRQHandler(void);
301 uint8_t External_50_IRQHandler(void);
302 uint8_t External_51_IRQHandler(void);
303 uint8_t External_52_IRQHandler(void);
304 uint8_t MAC0_plic_53_IRQHandler(void);
305
306 #endif
307
308 /***************************************************************************//**
309 * PLIC source Interrupt numbers:
310 */
311 /* See section on PLIC Interrupt Sources in User Guide */
312 #define OFFSET_TO_MSS_GLOBAL_INTS 13U
313 typedef enum
314 {
315 #ifndef SIFIVE_HIFIVE_UNLEASHED
316 INVALID_IRQn = 0,
317 L2_METADATA_CORR_IRQn = 1,
318 L2_METADAT_UNCORR_IRQn = 2,
319 L2_DATA_CORR_IRQn = 3,
320 L2_DATA_UNCORR_IRQn = 4,
321 DMA_CH0_DONE_IRQn = 5,
322 DMA_CH0_ERR_IRQn = 6,
323 DMA_CH1_DONE_IRQn = 7,
324 DMA_CH1_ERR_IRQn = 8,
325 DMA_CH2_DONE_IRQn = 9,
326 DMA_CH2_ERR_IRQn = 10,
327 DMA_CH3_DONE_IRQn = 11,
328 DMA_CH3_ERR_IRQn = 12,
329 /* see GPIO Interrupt Multiplexing in the User Guide */
330 GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 = 0 + OFFSET_TO_MSS_GLOBAL_INTS,
331 GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1 = 1 + OFFSET_TO_MSS_GLOBAL_INTS,
332 GPIO0_BIT2_or_GPIO2_BIT2_PLIC_2 = 2 + OFFSET_TO_MSS_GLOBAL_INTS,
333 GPIO0_BIT3_or_GPIO2_BIT3_PLIC_3 = 3 + OFFSET_TO_MSS_GLOBAL_INTS,
334 GPIO0_BIT4_or_GPIO2_BIT4_PLIC_4 = 4 + OFFSET_TO_MSS_GLOBAL_INTS,
335 GPIO0_BIT5_or_GPIO2_BIT5_PLIC_5 = 5 + OFFSET_TO_MSS_GLOBAL_INTS,
336 GPIO0_BIT6_or_GPIO2_BIT6_PLIC_6 = 6 + OFFSET_TO_MSS_GLOBAL_INTS,
337 GPIO0_BIT7_or_GPIO2_BIT7_PLIC_7 = 7 + OFFSET_TO_MSS_GLOBAL_INTS,
338 GPIO0_BIT8_or_GPIO2_BIT8_PLIC_8 = 8 + OFFSET_TO_MSS_GLOBAL_INTS,
339 GPIO0_BIT9_or_GPIO2_BIT9_PLIC_9 = 9 + OFFSET_TO_MSS_GLOBAL_INTS,
340 GPIO0_BIT10_or_GPIO2_BIT10_PLIC_10 = 10 + OFFSET_TO_MSS_GLOBAL_INTS,
341 GPIO0_BIT11_or_GPIO2_BIT11_PLIC_11 = 11 + OFFSET_TO_MSS_GLOBAL_INTS,
342 GPIO0_BIT12_or_GPIO2_BIT12_PLIC_12 = 12 + OFFSET_TO_MSS_GLOBAL_INTS,
343
344 GPIO0_BIT13_or_GPIO2_BIT13_PLIC_13 = 13 + OFFSET_TO_MSS_GLOBAL_INTS,
345 GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14 = 14 + OFFSET_TO_MSS_GLOBAL_INTS,
346 GPIO1_BIT1_or_GPIO2_BIT15_PLIC_15 = 15 + OFFSET_TO_MSS_GLOBAL_INTS,
347 GPIO1_BIT2_or_GPIO2_BIT16_PLIC_16 = 16 + OFFSET_TO_MSS_GLOBAL_INTS,
348 GPIO1_BIT3_or_GPIO2_BIT17_PLIC_17 = 17 + OFFSET_TO_MSS_GLOBAL_INTS,
349 GPIO1_BIT4_or_GPIO2_BIT18_PLIC_18 = 18 + OFFSET_TO_MSS_GLOBAL_INTS,
350 GPIO1_BIT5_or_GPIO2_BIT19_PLIC_19 = 19 + OFFSET_TO_MSS_GLOBAL_INTS,
351 GPIO1_BIT6_or_GPIO2_BIT20_PLIC_20 = 20 + OFFSET_TO_MSS_GLOBAL_INTS,
352 GPIO1_BIT7_or_GPIO2_BIT21_PLIC_21 = 21 + OFFSET_TO_MSS_GLOBAL_INTS,
353 GPIO1_BIT8_or_GPIO2_BIT22_PLIC_22 = 22 + OFFSET_TO_MSS_GLOBAL_INTS,
354 GPIO1_BIT9_or_GPIO2_BIT23_PLIC_23 = 23 + OFFSET_TO_MSS_GLOBAL_INTS,
355 GPIO1_BIT10_or_GPIO2_BIT24_PLIC_24 = 24 + OFFSET_TO_MSS_GLOBAL_INTS,
356 GPIO1_BIT11_or_GPIO2_BIT25_PLIC_25 = 25 + OFFSET_TO_MSS_GLOBAL_INTS,
357 GPIO1_BIT12_or_GPIO2_BIT26_PLIC_26 = 26 + OFFSET_TO_MSS_GLOBAL_INTS,
358 GPIO1_BIT13_or_GPIO2_BIT27_PLIC_27 = 27 + OFFSET_TO_MSS_GLOBAL_INTS,
359
360 GPIO1_BIT14_or_GPIO2_BIT28_PLIC_28 = 28 + OFFSET_TO_MSS_GLOBAL_INTS,
361 GPIO1_BIT15_or_GPIO2_BIT29_PLIC_29 = 29 + OFFSET_TO_MSS_GLOBAL_INTS,
362 GPIO1_BIT16_or_GPIO2_BIT30_PLIC_30 = 30 + OFFSET_TO_MSS_GLOBAL_INTS,
363 GPIO1_BIT17_or_GPIO2_BIT31_PLIC_31 = 31 + OFFSET_TO_MSS_GLOBAL_INTS,
364
365 GPIO1_BIT18_PLIC_32 = 32 + OFFSET_TO_MSS_GLOBAL_INTS,
366 GPIO1_BIT19_PLIC_33 = 33 + OFFSET_TO_MSS_GLOBAL_INTS,
367 GPIO1_BIT20_PLIC_34 = 34 + OFFSET_TO_MSS_GLOBAL_INTS,
368 GPIO1_BIT21_PLIC_35 = 35 + OFFSET_TO_MSS_GLOBAL_INTS,
369 GPIO1_BIT22_PLIC_36 = 36 + OFFSET_TO_MSS_GLOBAL_INTS,
370 GPIO1_BIT23_PLIC_37 = 37 + OFFSET_TO_MSS_GLOBAL_INTS,
371
372 GPIO0_NON_DIRECT_PLIC = 38 + OFFSET_TO_MSS_GLOBAL_INTS,
373 GPIO1_NON_DIRECT_PLIC = 39 + OFFSET_TO_MSS_GLOBAL_INTS,
374 GPIO2_NON_DIRECT_PLIC = 40 + OFFSET_TO_MSS_GLOBAL_INTS,
375
376 SPI0_PLIC = 41 + OFFSET_TO_MSS_GLOBAL_INTS,
377 SPI1_PLIC = 42 + OFFSET_TO_MSS_GLOBAL_INTS,
378 CAN0_PLIC = 43 + OFFSET_TO_MSS_GLOBAL_INTS,
379 CAN1_PLIC = 44 + OFFSET_TO_MSS_GLOBAL_INTS,
380 I2C0_MAIN_PLIC = 45 + OFFSET_TO_MSS_GLOBAL_INTS,
381 I2C0_ALERT_PLIC = 46 + OFFSET_TO_MSS_GLOBAL_INTS,
382 I2C0_SUS_PLIC = 47 + OFFSET_TO_MSS_GLOBAL_INTS,
383 I2C1_MAIN_PLIC = 48 + OFFSET_TO_MSS_GLOBAL_INTS,
384 I2C1_ALERT_PLIC = 49 + OFFSET_TO_MSS_GLOBAL_INTS,
385 I2C1_SUS_PLIC = 50 + OFFSET_TO_MSS_GLOBAL_INTS,
386 MAC0_INT_PLIC = 51 + OFFSET_TO_MSS_GLOBAL_INTS,
387 MAC0_QUEUE1_PLIC = 52 + OFFSET_TO_MSS_GLOBAL_INTS,
388 MAC0_QUEUE2_PLIC = 53 + OFFSET_TO_MSS_GLOBAL_INTS,
389 MAC0_QUEUE3_PLIC = 54 + OFFSET_TO_MSS_GLOBAL_INTS,
390 MAC0_EMAC_PLIC = 55 + OFFSET_TO_MSS_GLOBAL_INTS,
391 MAC0_MMSL_PLIC = 56 + OFFSET_TO_MSS_GLOBAL_INTS,
392 MAC1_INT_PLIC = 57 + OFFSET_TO_MSS_GLOBAL_INTS,
393 MAC1_QUEUE1_PLIC = 58 + OFFSET_TO_MSS_GLOBAL_INTS,
394 MAC1_QUEUE2_PLIC = 59 + OFFSET_TO_MSS_GLOBAL_INTS,
395 MAC1_QUEUE3_PLIC = 60 + OFFSET_TO_MSS_GLOBAL_INTS,
396 MAC1_EMAC_PLIC = 61 + OFFSET_TO_MSS_GLOBAL_INTS,
397 MAC1_MMSL_PLIC = 62 + OFFSET_TO_MSS_GLOBAL_INTS,
398 DDRC_TRAIN_PLIC = 63 + OFFSET_TO_MSS_GLOBAL_INTS,
399 SCB_INTERRUPT_PLIC = 64 + OFFSET_TO_MSS_GLOBAL_INTS,
400 ECC_ERROR_PLIC = 65 + OFFSET_TO_MSS_GLOBAL_INTS,
401 ECC_CORRECT_PLIC = 66 + OFFSET_TO_MSS_GLOBAL_INTS,
402 RTC_WAKEUP_PLIC = 67 + OFFSET_TO_MSS_GLOBAL_INTS,
403 RTC_MATCH_PLIC = 68 + OFFSET_TO_MSS_GLOBAL_INTS,
404 TIMER1_PLIC = 69 + OFFSET_TO_MSS_GLOBAL_INTS,
405 TIMER2_PLIC = 70 + OFFSET_TO_MSS_GLOBAL_INTS,
406 ENVM_PLIC = 71 + OFFSET_TO_MSS_GLOBAL_INTS,
407 QSPI_PLIC = 72 + OFFSET_TO_MSS_GLOBAL_INTS,
408 USB_DMA_PLIC = 73 + OFFSET_TO_MSS_GLOBAL_INTS,
409 USB_MC_PLIC = 74 + OFFSET_TO_MSS_GLOBAL_INTS,
410 MMC_main_PLIC = 75 + OFFSET_TO_MSS_GLOBAL_INTS,
411 MMC_wakeup_PLIC = 76 + OFFSET_TO_MSS_GLOBAL_INTS,
412 MMUART0_PLIC_77 = 77 + OFFSET_TO_MSS_GLOBAL_INTS,
413 MMUART1_PLIC = 78 + OFFSET_TO_MSS_GLOBAL_INTS,
414 MMUART2_PLIC = 79 + OFFSET_TO_MSS_GLOBAL_INTS,
415 MMUART3_PLIC = 80 + OFFSET_TO_MSS_GLOBAL_INTS,
416 MMUART4_PLIC = 81 + OFFSET_TO_MSS_GLOBAL_INTS,
417
418 G5C_DEVRST_PLIC = 82 + OFFSET_TO_MSS_GLOBAL_INTS,
419 g5c_MESSAGE_PLIC = 83 + OFFSET_TO_MSS_GLOBAL_INTS,
420 USOC_VC_INTERRUPT_PLIC = 84 + OFFSET_TO_MSS_GLOBAL_INTS,
421 USOC_SMB_INTERRUPT_PLIC = 85 + OFFSET_TO_MSS_GLOBAL_INTS,
422 /* contains multiple interrupts- */
423 E51_0_MAINTENACE_PLIC = 86 + OFFSET_TO_MSS_GLOBAL_INTS,
424
425 WDOG0_MRVP_PLIC = 87 + OFFSET_TO_MSS_GLOBAL_INTS,
426 WDOG1_MRVP_PLIC = 88 + OFFSET_TO_MSS_GLOBAL_INTS,
427 WDOG2_MRVP_PLIC = 89 + OFFSET_TO_MSS_GLOBAL_INTS,
428 WDOG3_MRVP_PLIC = 90 + OFFSET_TO_MSS_GLOBAL_INTS,
429 WDOG4_MRVP_PLIC = 91 + OFFSET_TO_MSS_GLOBAL_INTS,
430 WDOG0_TOUT_PLIC = 92 + OFFSET_TO_MSS_GLOBAL_INTS,
431 WDOG1_TOUT_PLIC = 93 + OFFSET_TO_MSS_GLOBAL_INTS,
432 WDOG2_TOUT_PLIC = 94 + OFFSET_TO_MSS_GLOBAL_INTS,
433 WDOG3_TOUT_PLIC = 95 + OFFSET_TO_MSS_GLOBAL_INTS,
434 WDOG4_TOUT_PLIC = 96 + OFFSET_TO_MSS_GLOBAL_INTS,
435 G5C_MSS_SPI_PLIC = 97 + OFFSET_TO_MSS_GLOBAL_INTS,
436 VOLT_TEMP_ALARM_PLIC = 98 + OFFSET_TO_MSS_GLOBAL_INTS,
437 ATHENA_COMPLETE_PLIC = 99 + OFFSET_TO_MSS_GLOBAL_INTS,
438 ATHENA_ALARM_PLIC = 100 + OFFSET_TO_MSS_GLOBAL_INTS,
439 ATHENA_BUS_ERROR_PLIC = 101 + OFFSET_TO_MSS_GLOBAL_INTS,
440 USOC_AXIC_US_PLIC = 102 + OFFSET_TO_MSS_GLOBAL_INTS,
441 USOC_AXIC_DS_PLIC = 103 + OFFSET_TO_MSS_GLOBAL_INTS,
442
443 FABRIC_F2H_0_PLIC = 105 + OFFSET_TO_MSS_GLOBAL_INTS,
444 FABRIC_F2H_1_PLIC = 106 + OFFSET_TO_MSS_GLOBAL_INTS,
445 FABRIC_F2H_2_PLIC = 107 + OFFSET_TO_MSS_GLOBAL_INTS,
446 FABRIC_F2H_3_PLIC = 108 + OFFSET_TO_MSS_GLOBAL_INTS,
447 FABRIC_F2H_4_PLIC = 109 + OFFSET_TO_MSS_GLOBAL_INTS,
448 FABRIC_F2H_5_PLIC = 110 + OFFSET_TO_MSS_GLOBAL_INTS,
449 FABRIC_F2H_6_PLIC = 111 + OFFSET_TO_MSS_GLOBAL_INTS,
450 FABRIC_F2H_7_PLIC = 112 + OFFSET_TO_MSS_GLOBAL_INTS,
451 FABRIC_F2H_8_PLIC = 113 + OFFSET_TO_MSS_GLOBAL_INTS,
452 FABRIC_F2H_9_PLIC = 114 + OFFSET_TO_MSS_GLOBAL_INTS,
453
454 FABRIC_F2H_10_PLIC = 115 + OFFSET_TO_MSS_GLOBAL_INTS,
455 FABRIC_F2H_11_PLIC = 116 + OFFSET_TO_MSS_GLOBAL_INTS,
456 FABRIC_F2H_12_PLIC = 117 + OFFSET_TO_MSS_GLOBAL_INTS,
457 FABRIC_F2H_13_PLIC = 118 + OFFSET_TO_MSS_GLOBAL_INTS,
458 FABRIC_F2H_14_PLIC = 119 + OFFSET_TO_MSS_GLOBAL_INTS,
459 FABRIC_F2H_15_PLIC = 120 + OFFSET_TO_MSS_GLOBAL_INTS,
460 FABRIC_F2H_16_PLIC = 121 + OFFSET_TO_MSS_GLOBAL_INTS,
461 FABRIC_F2H_17_PLIC = 122 + OFFSET_TO_MSS_GLOBAL_INTS,
462 FABRIC_F2H_18_PLIC = 123 + OFFSET_TO_MSS_GLOBAL_INTS,
463 FABRIC_F2H_19_PLIC = 124 + OFFSET_TO_MSS_GLOBAL_INTS,
464
465 FABRIC_F2H_20_PLIC = 125 + OFFSET_TO_MSS_GLOBAL_INTS,
466 FABRIC_F2H_21_PLIC = 126 + OFFSET_TO_MSS_GLOBAL_INTS,
467 FABRIC_F2H_22_PLIC = 127 + OFFSET_TO_MSS_GLOBAL_INTS,
468 FABRIC_F2H_23_PLIC = 128 + OFFSET_TO_MSS_GLOBAL_INTS,
469 FABRIC_F2H_24_PLIC = 129 + OFFSET_TO_MSS_GLOBAL_INTS,
470 FABRIC_F2H_25_PLIC = 130 + OFFSET_TO_MSS_GLOBAL_INTS,
471 FABRIC_F2H_26_PLIC = 131 + OFFSET_TO_MSS_GLOBAL_INTS,
472 FABRIC_F2H_27_PLIC = 132 + OFFSET_TO_MSS_GLOBAL_INTS,
473 FABRIC_F2H_28_PLIC = 133 + OFFSET_TO_MSS_GLOBAL_INTS,
474 FABRIC_F2H_29_PLIC = 134 + OFFSET_TO_MSS_GLOBAL_INTS,
475
476 FABRIC_F2H_30_PLIC = 135 + OFFSET_TO_MSS_GLOBAL_INTS,
477 FABRIC_F2H_31_PLIC = 136 + OFFSET_TO_MSS_GLOBAL_INTS,
478
479 FABRIC_F2H_32_PLIC = 137 + OFFSET_TO_MSS_GLOBAL_INTS,
480 FABRIC_F2H_33_PLIC = 138 + OFFSET_TO_MSS_GLOBAL_INTS,
481 FABRIC_F2H_34_PLIC = 139 + OFFSET_TO_MSS_GLOBAL_INTS,
482 FABRIC_F2H_35_PLIC = 140 + OFFSET_TO_MSS_GLOBAL_INTS,
483 FABRIC_F2H_36_PLIC = 141 + OFFSET_TO_MSS_GLOBAL_INTS,
484 FABRIC_F2H_37_PLIC = 142 + OFFSET_TO_MSS_GLOBAL_INTS,
485 FABRIC_F2H_38_PLIC = 143 + OFFSET_TO_MSS_GLOBAL_INTS,
486 FABRIC_F2H_39_PLIC = 144 + OFFSET_TO_MSS_GLOBAL_INTS,
487 FABRIC_F2H_40_PLIC = 145 + OFFSET_TO_MSS_GLOBAL_INTS,
488 FABRIC_F2H_41_PLIC = 146 + OFFSET_TO_MSS_GLOBAL_INTS,
489
490 FABRIC_F2H_42_PLIC = 147 + OFFSET_TO_MSS_GLOBAL_INTS,
491 FABRIC_F2H_43_PLIC = 148 + OFFSET_TO_MSS_GLOBAL_INTS,
492 FABRIC_F2H_44_PLIC = 149 + OFFSET_TO_MSS_GLOBAL_INTS,
493 FABRIC_F2H_45_PLIC = 150 + OFFSET_TO_MSS_GLOBAL_INTS,
494 FABRIC_F2H_46_PLIC = 151 + OFFSET_TO_MSS_GLOBAL_INTS,
495 FABRIC_F2H_47_PLIC = 152 + OFFSET_TO_MSS_GLOBAL_INTS,
496 FABRIC_F2H_48_PLIC = 153 + OFFSET_TO_MSS_GLOBAL_INTS,
497 FABRIC_F2H_49_PLIC = 154 + OFFSET_TO_MSS_GLOBAL_INTS,
498 FABRIC_F2H_50_PLIC = 155 + OFFSET_TO_MSS_GLOBAL_INTS,
499 FABRIC_F2H_51_PLIC = 156 + OFFSET_TO_MSS_GLOBAL_INTS,
500
501 FABRIC_F2H_52_PLIC = 157 + OFFSET_TO_MSS_GLOBAL_INTS,
502 FABRIC_F2H_53_PLIC = 158 + OFFSET_TO_MSS_GLOBAL_INTS,
503 FABRIC_F2H_54_PLIC = 159 + OFFSET_TO_MSS_GLOBAL_INTS,
504 FABRIC_F2H_55_PLIC = 160 + OFFSET_TO_MSS_GLOBAL_INTS,
505 FABRIC_F2H_56_PLIC = 161 + OFFSET_TO_MSS_GLOBAL_INTS,
506 FABRIC_F2H_57_PLIC = 162 + OFFSET_TO_MSS_GLOBAL_INTS,
507 FABRIC_F2H_58_PLIC = 163 + OFFSET_TO_MSS_GLOBAL_INTS,
508 FABRIC_F2H_59_PLIC = 164 + OFFSET_TO_MSS_GLOBAL_INTS,
509 FABRIC_F2H_60_PLIC = 165 + OFFSET_TO_MSS_GLOBAL_INTS,
510 FABRIC_F2H_61_PLIC = 166 + OFFSET_TO_MSS_GLOBAL_INTS,
511
512 FABRIC_F2H_62_PLIC = 167 + OFFSET_TO_MSS_GLOBAL_INTS,
513 FABRIC_F2H_63_PLIC = 168 + OFFSET_TO_MSS_GLOBAL_INTS,
514
515 BUS_ERROR_UNIT_HART_0 = 182,
516 BUS_ERROR_UNIT_HART_1 = 183,
517 BUS_ERROR_UNIT_HART_2 = 184,
518 BUS_ERROR_UNIT_HART_3 = 185,
519 BUS_ERROR_UNIT_HART_4 = 186
520
521 #else
522 INVALID_IRQn = 0,
523 L2Cache_0_PLIC_1 = 1,
524 L2Cache_1_PLIC_2 = 2,
525 L2Cache_2__PLIC_3 = 3,
526 USART0_PLIC_4 = 4,
527 USART1_PLIC_5 = 5,
528 QSPI_12_PLIC_6 = 6,
529
530 gpio_PLIC_7 = 7,
531 gpio_PLIC_8 = 8,
532 gpio_PLIC_9 = 9,
533 gpio_10 = 10,
534 gpio_11 = 11,
535 gpio_12 = 12,
536 gpio_PLIC_13 = 13,
537 gpio_PLIC_14 = 14,
538 gpio_PLIC_15 = 15,
539 gpio_PLIC_16 = 16,
540 gpio_PLIC_17 = 17,
541 gpio_PLIC_18 = 18,
542 gpio_PLIC_19 = 19,
543 gpio_PLIC_20 = 20,
544 gpio_PLIC_21 = 21,
545 gpio_PLIC_22 = 22,
546
547 dma_PLIC_23 = 23,
548 dma_PLIC_24 = 24,
549 dma_PLIC_25 = 25,
550 dma_PLIC_26 = 26,
551 dma_PLIC_27 = 27,
552 dma_PLIC_28 = 28,
553 dma_PLIC_29 = 29,
554 dma_PLIC_30 = 30,
555
556 ddr_subsytem_PLIC_31 = 31,
557
558 chiplink_msi_PLIC_32 = 32,
559 chiplink_msi_PLIC_33 = 33,
560 chiplink_msi_PLIC_34 = 34,
561 chiplink_msi_PLIC_35 = 35,
562 chiplink_msi_PLIC_36 = 36,
563 chiplink_msi_PLIC_37 = 37,
564 chiplink_msi_PLIC_38 = 38,
565 chiplink_msi_PLIC_39 = 39,
566 chiplink_msi_PLIC_40 = 40,
567 chiplink_msi_PLIC_41 = 41,
568
569 pwm0_PLIC_42 = 42,
570 pwm0_PLIC_43 = 43,
571 pwm0_PLIC_44 = 44,
572 pwm0_PLIC_45 = 45,
573
574 pwm1_PLIC_46 = 46,
575 pwm1_PLIC_47 = 47,
576 pwm1_PLIC_48 = 48,
577 pwm1_PLIC_49 = 49,
578
579 i2c_PLIC_50 = 50,
580 QSPI0_PLIC_51 = 51,
581 QSPI1_PLIC_52 = 52,
582 ethernet_PLIC_53 = 53
583
584 #endif
585
586 } PLIC_IRQn_Type;
587
588 #ifndef SIFIVE_HIFIVE_UNLEASHED
589 #define MAX_PLIC_INT BUS_ERROR_UNIT_HART_4
590 #else
591 #define MAX_PLIC_INT ethernet_PLIC_53
592 #endif
593
594 /***************************************************************************//**
595 * E51-0 is Maintenance Interrupt, CPU needs to read status register to
596 * determine exact cause:
597 * This structure added here for clarity, need to replay with status register
598 * defines for determining interrupt cause
599 */
600 typedef enum
601 {
602 mpu_fail_plic =0,
603 lp_state_enter_plic =1,
604 lp_state_exit_plic =2,
605 ff_start_plic =3,
606 ff_end_plic =4,
607 fpga_on_plic =5,
608 fpga_off_plic =6,
609 scb_error_plic =7,
610 scb_fault_plic =8,
611 mesh_fail_plic =9
612 } PLIC_IRQ86_Type;
613
614 typedef struct
615 {
616 volatile uint32_t PRIORITY_THRESHOLD;
617 volatile uint32_t CLAIM_COMPLETE;
618 volatile uint32_t reserved[(0x1000/4)-2];
619 } IRQ_Target_Type;
620
621 typedef struct
622 {
623 volatile uint32_t ENABLES[32U];
624 } Target_Enables_Type;
625
626 #ifndef SIFIVE_HIFIVE_UNLEASHED
627 #define PLIC_SET_UP_REGISTERS 6U
628 #else
629 #define PLIC_SET_UP_REGISTERS 2U
630 #endif
631
632 #ifndef SIFIVE_HIFIVE_UNLEASHED
633 #define PLIC_NUM_SOURCES 187U
634 #else
635 #define PLIC_NUM_SOURCES 54U /* 53 actual, source 0 is not used */
636 #endif
637
638 #define PLIC_NUM_PRIORITIES 7U
639 #define NUM_CLAIM_REGS 9U
640
641
642 /* The FU540-C000 has 53 interrupt sources. */
643 typedef struct
644 {
645 volatile uint32_t RESERVED0;
646 /*-------------------- Source Priority --------------------*/
647 volatile uint32_t SOURCE_PRIORITY[PLIC_NUM_SOURCES];
648 volatile uint32_t RESERVED1[(0x1000 / 4) - (PLIC_NUM_SOURCES + 1)];
649 /*-------------------- Pending array --------------------*/
650 volatile const uint32_t PENDING_ARRAY[PLIC_SET_UP_REGISTERS];
651 volatile uint32_t RESERVED2[(0x1000/4) - PLIC_SET_UP_REGISTERS];
652
653 /*-----------------Hart0 Mode Enables--------------------*/
654 volatile uint32_t HART0_MMODE_ENA[PLIC_SET_UP_REGISTERS];
655 volatile uint32_t RESERVED3[(0x80/4) - PLIC_SET_UP_REGISTERS];
656
657 /*-----------------Hart1 Mode Enables--------------------*/
658 volatile uint32_t HART1_MMODE_ENA[PLIC_SET_UP_REGISTERS];
659 volatile uint32_t RESERVED4a[(0x80/4) - PLIC_SET_UP_REGISTERS];
660 volatile uint32_t HART1_SMODE_ENA[PLIC_SET_UP_REGISTERS];
661 volatile uint32_t RESERVED4[(0x80/4) - PLIC_SET_UP_REGISTERS];
662
663 /*-----------------Hart2 Mode Enables--------------------*/
664 volatile uint32_t HART2_MMODE_ENA[PLIC_SET_UP_REGISTERS];
665 volatile uint32_t RESERVED5a[(0x80/4) - PLIC_SET_UP_REGISTERS];
666 volatile uint32_t HART2_SMODE_ENA[PLIC_SET_UP_REGISTERS];
667 volatile uint32_t RESERVED5[(0x80/4) - PLIC_SET_UP_REGISTERS];
668
669 /*-----------------Hart3 Mode Enables--------------------*/
670 volatile uint32_t HART3_MMODE_ENA[PLIC_SET_UP_REGISTERS];
671 volatile uint32_t RESERVED6a[(0x80/4) - PLIC_SET_UP_REGISTERS];
672 volatile uint32_t HART3_SMODE_ENA[PLIC_SET_UP_REGISTERS];
673 volatile uint32_t RESERVED6[(0x80/4) - PLIC_SET_UP_REGISTERS];
674
675 /*-----------------Hart4 Mode Enables--------------------*/
676 volatile uint32_t HART4_MMODE_ENA[PLIC_SET_UP_REGISTERS];
677 volatile uint32_t RESERVED7a[(0x80/4) - PLIC_SET_UP_REGISTERS];
678 volatile uint32_t HART4_SMODE_ENA[PLIC_SET_UP_REGISTERS];
679 volatile uint32_t RESERVED7[(0x80/4) - PLIC_SET_UP_REGISTERS];
680
681 volatile uint32_t RESERVED8[(0x0C200000 - 0x0C002480)/4];
682
683 /*--- Target Priority threshold and claim/complete---------*/
684 IRQ_Target_Type TARGET[NUM_CLAIM_REGS]; /* See PLIC Register Map or
685 TARGET_OFFSET defines below
686 for offset details */
687
688 } PLIC_Type;
689
690 #define TARGET_OFFSET_HART0_M 0U
691 #define TARGET_OFFSET_HART1_M 1U
692 #define TARGET_OFFSET_HART1_S 2U
693 #define TARGET_OFFSET_HART2_M 3U
694 #define TARGET_OFFSET_HART2_S 4U
695 #define TARGET_OFFSET_HART3_M 5U
696 #define TARGET_OFFSET_HART3_S 6U
697 #define TARGET_OFFSET_HART4_M 7U
698 #define TARGET_OFFSET_HART4_S 8U
699
700 extern const unsigned long plic_hart_lookup[5U];
701
702 /***************************************************************************//**
703 * PLIC: Platform Level Interrupt Controller
704 */
705 #define PLIC_BASE_ADDR 0x0C000000UL
706
707 #define PLIC ((PLIC_Type * const)PLIC_BASE_ADDR)
708
709 /*-------------------------------------------------------------------------*//**
710 * The function PLIC_init() initializes the PLIC controller and enables the
711 * global external interrupt bit.
712 */
713
714 /*-----------------Hart Mode Enables--------------------*/
715
PLIC_init(void)716 static inline void PLIC_init(void)
717 {
718 uint32_t inc;
719 uint64_t hart_id = read_csr(mhartid);
720
721 /* Disable all interrupts for the current hart. */
722 switch(hart_id)
723 {
724 case 0:
725 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
726 {
727 PLIC->HART0_MMODE_ENA[inc] = 0U;
728 }
729
730 /* Set the threshold to zero.
731 * PLIC provides context based threshold register for the settings of a
732 * interrupt priority threshold of each context. The threshold register
733 * is a WARL field. The PLIC will mask all PLIC interrupts of a priority
734 * less than or equal to threshold. For example, a threshold value of zero
735 * permits all interrupts with non-zero priority.*/
736
737 PLIC->TARGET[TARGET_OFFSET_HART0_M].PRIORITY_THRESHOLD = 0U;
738 break;
739 case 1:
740 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
741 {
742 PLIC->HART1_MMODE_ENA[inc] = 0U;
743 PLIC->HART1_SMODE_ENA[inc] = 0U;
744 }
745
746 PLIC->TARGET[TARGET_OFFSET_HART1_M].PRIORITY_THRESHOLD = 0U;
747 /* Disable supervisor level */
748 PLIC->TARGET[TARGET_OFFSET_HART1_S].PRIORITY_THRESHOLD = 7U;
749 break;
750 case 2:
751 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
752 {
753 PLIC->HART2_MMODE_ENA[inc] = 0U;
754 PLIC->HART2_SMODE_ENA[inc] = 0U;
755 }
756
757 PLIC->TARGET[TARGET_OFFSET_HART2_M].PRIORITY_THRESHOLD = 0U;
758 /* Disable supervisor level */
759 PLIC->TARGET[TARGET_OFFSET_HART2_S].PRIORITY_THRESHOLD = 7U;
760 break;
761 case 3:
762 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
763 {
764 PLIC->HART3_MMODE_ENA[inc] = 0U;
765 PLIC->HART3_SMODE_ENA[inc] = 0U;
766 }
767
768 PLIC->TARGET[TARGET_OFFSET_HART3_M].PRIORITY_THRESHOLD = 0U;
769 /* Disable supervisor level */
770 PLIC->TARGET[TARGET_OFFSET_HART3_S].PRIORITY_THRESHOLD = 7U;
771 break;
772 case 4:
773 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
774 {
775 PLIC->HART4_MMODE_ENA[inc] = 0U;
776 PLIC->HART4_SMODE_ENA[inc] = 0U;
777 }
778
779 PLIC->TARGET[TARGET_OFFSET_HART4_M].PRIORITY_THRESHOLD = 0U;
780 /* Disable supervisor level */
781 PLIC->TARGET[TARGET_OFFSET_HART4_S].PRIORITY_THRESHOLD = 7U;
782 break;
783 default:
784 break;
785 }
786
787 /* Enable machine external interrupts. */
788 set_csr(mie, MIP_MEIP);
789 }
790
791
792
793 /***************************************************************************//**
794 * The function PLIC_EnableIRQ() enables the external interrupt for the
795 * interrupt number indicated by the parameter IRQn.
796 */
PLIC_EnableIRQ(PLIC_IRQn_Type IRQn)797 static inline void PLIC_EnableIRQ(PLIC_IRQn_Type IRQn)
798 {
799 uint32_t current;
800 uint64_t hart_id = read_csr(mhartid);
801
802 switch(hart_id)
803 {
804 case 0:
805 current = PLIC->HART0_MMODE_ENA[IRQn / 32U];
806 current |= (uint32_t)1 << (IRQn % 32U);
807 PLIC->HART0_MMODE_ENA[IRQn / 32U] = current;
808 break;
809 case 1:
810 current = PLIC->HART1_MMODE_ENA[IRQn / 32U];
811 current |= (uint32_t)1 << (IRQn % 32U);
812 PLIC->HART1_MMODE_ENA[IRQn / 32U] = current;
813 break;
814 case 2:
815 current = PLIC->HART2_MMODE_ENA[IRQn / 32U];
816 current |= (uint32_t)1 << (IRQn % 32U);
817 PLIC->HART2_MMODE_ENA[IRQn / 32U] = current;
818 break;
819 case 3:
820 current = PLIC->HART3_MMODE_ENA[IRQn / 32U];
821 current |= (uint32_t)1 << (IRQn % 32U);
822 PLIC->HART3_MMODE_ENA[IRQn / 32U] = current;
823 break;
824 case 4:
825 current = PLIC->HART4_MMODE_ENA[IRQn / 32U];
826 current |= (uint32_t)1 << (IRQn % 32U);
827 PLIC->HART4_MMODE_ENA[IRQn / 32U] = current;
828 break;
829 default:
830 break;
831 }
832 }
833
834 /***************************************************************************//**
835 * The function PLIC_DisableIRQ() disables the external interrupt for the
836 * interrupt number indicated by the parameter IRQn.
837
838 * NOTE:
839 * This function can be used to disable the external interrupt from outside
840 * external interrupt handler function.
841 * This function MUST NOT be used from within the External Interrupt
842 * handler.
843 * If you wish to disable the external interrupt while the interrupt handler
844 * for that external interrupt is executing then you must use the return
845 * value EXT_IRQ_DISABLE to return from the extern interrupt handler.
846 */
PLIC_DisableIRQ(PLIC_IRQn_Type IRQn)847 static inline void PLIC_DisableIRQ(PLIC_IRQn_Type IRQn)
848 {
849 uint32_t current;
850 uint64_t hart_id = read_csr(mhartid);
851
852 switch(hart_id)
853 {
854 case 0:
855 current = PLIC->HART0_MMODE_ENA[IRQn / 32U];
856 current &= ~((uint32_t)1 << (IRQn % 32U));
857 PLIC->HART0_MMODE_ENA[IRQn / 32U] = current;
858 break;
859 case 1:
860 current = PLIC->HART1_MMODE_ENA[IRQn / 32U];
861 current &= ~((uint32_t)1 << (IRQn % 32U));
862 PLIC->HART1_MMODE_ENA[IRQn / 32U] = current;
863 break;
864 case 2:
865 current = PLIC->HART2_MMODE_ENA[IRQn / 32U];
866 current &= ~((uint32_t)1 << (IRQn % 32U));
867 PLIC->HART2_MMODE_ENA[IRQn / 32U] = current;
868 break;
869 case 3:
870 current = PLIC->HART3_MMODE_ENA[IRQn / 32U];
871 current &= ~((uint32_t)1 << (IRQn % 32U));
872 PLIC->HART3_MMODE_ENA[IRQn / 32U] = current;
873 break;
874 case 4:
875 current = PLIC->HART4_MMODE_ENA[IRQn / 32U];
876 current &= ~((uint32_t)1 << (IRQn % 32U));
877 PLIC->HART4_MMODE_ENA[IRQn / 32U] = current;
878 break;
879 default:
880 break;
881 }
882 }
883
884 /***************************************************************************//**
885 * The function PLIC_SetPriority() sets the priority for the external interrupt
886 * for the interrupt number indicated by the parameter IRQn.
887 */
PLIC_SetPriority(PLIC_IRQn_Type IRQn,uint32_t priority)888 static inline void PLIC_SetPriority(PLIC_IRQn_Type IRQn, uint32_t priority)
889 {
890 if((IRQn > INVALID_IRQn) && (IRQn < PLIC_NUM_SOURCES))
891 {
892 PLIC->SOURCE_PRIORITY[IRQn-1] = priority;
893 }
894 }
895
896 /***************************************************************************//**
897 * The function PLIC_GetPriority() returns the priority for the external
898 * interrupt for the interrupt number indicated by the parameter IRQn.
899 */
PLIC_GetPriority(PLIC_IRQn_Type IRQn)900 static inline uint32_t PLIC_GetPriority(PLIC_IRQn_Type IRQn)
901 {
902 uint32_t ret_val = 0U;
903
904 if((IRQn > INVALID_IRQn) && (IRQn < PLIC_NUM_SOURCES))
905 {
906 ret_val = PLIC->SOURCE_PRIORITY[IRQn-1];
907 }
908
909 return(ret_val);
910 }
911
912
PLIC_pending(PLIC_IRQn_Type IRQn)913 static inline uint32_t PLIC_pending(PLIC_IRQn_Type IRQn)
914 {
915 return (PLIC->PENDING_ARRAY[IRQn/32U] & (0x01U<<(IRQn%32U)));
916 }
917
918 /***************************************************************************//**
919 * The function PLIC_ClaimIRQ() claims the interrupt from the PLIC controller.
920 */
PLIC_ClaimIRQ(void)921 static inline uint32_t PLIC_ClaimIRQ(void)
922 {
923 uint64_t hart_id = read_csr(mhartid);
924
925 return (PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE);
926 }
927
928 /***************************************************************************//**
929 * The function PLIC_CompleteIRQ() indicates to the PLIC controller the
930 * interrupt is processed and claim is complete.
931 */
PLIC_CompleteIRQ(uint32_t source)932 static inline void PLIC_CompleteIRQ(uint32_t source)
933 {
934 uint64_t hart_id = read_csr(mhartid);
935
936 ASSERT(source <= MAX_PLIC_INT);
937
938 PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE = source;
939 }
940
941 /***************************************************************************//**
942 *
943 * The function PLIC_SetPriority_Threshold() sets the threshold for a particular
944 * hart. The default threshold on reset is 0.
945 * The PFSoC Core Complex supports setting of an interrupt priority threshold
946 * via the threshold register. The threshold is a WARL field, where the PFSoC
947 * Core Complex supports a maximum threshold of 7.
948 * The PFSoC Core Complex will mask all PLIC interrupts of a priority less than
949 * or equal to threshold. For example, a threshold value of zero permits all
950 * interrupts with non-zero priority, whereas a value of 7 masks all
951 * interrupts.
952 */
PLIC_SetPriority_Threshold(uint32_t threshold)953 static inline void PLIC_SetPriority_Threshold(uint32_t threshold)
954 {
955 uint64_t hart_id = read_csr(mhartid);
956
957 ASSERT(threshold <= 7);
958
959 PLIC->TARGET[plic_hart_lookup[hart_id]].PRIORITY_THRESHOLD = threshold;
960 }
961
962 /***************************************************************************//**
963 * PLIC_ClearPendingIRQ(void)
964 * This is only called by the startup hart and only once
965 * Clears any pending interrupts as PLIC can be in unknown state on startup
966 */
PLIC_ClearPendingIRQ(void)967 static inline void PLIC_ClearPendingIRQ(void)
968 {
969 volatile uint32_t int_num = PLIC_ClaimIRQ();
970 volatile int32_t wait_possible_int;
971
972 while ( int_num != INVALID_IRQn)
973 {
974 PLIC_CompleteIRQ(int_num);
975 wait_possible_int = 0xFU;
976 while (wait_possible_int)
977 {
978 wait_possible_int--;
979 }
980 int_num = PLIC_ClaimIRQ(); /* obtain interrupt, auto clears */
981 }
982 }
983
984 /***************************************************************************//**
985 * This function is only called from one hart on startup
986 */
PLIC_init_on_reset(void)987 static inline void PLIC_init_on_reset(void)
988 {
989 uint32_t inc;
990
991 /* default all priorities so effectively disabled */
992 for(inc = 0U; inc < PLIC_NUM_SOURCES; ++inc)
993 {
994 /* priority must be greater than threshold to be enabled, so setting to
995 * 7 disables */
996 PLIC->SOURCE_PRIORITY[inc] = 0U;
997 }
998
999 for(inc = 0U; inc < NUM_CLAIM_REGS; ++inc)
1000 {
1001 PLIC->TARGET[inc].PRIORITY_THRESHOLD = 7U;
1002 }
1003
1004 /* and clear all the enables */
1005 for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
1006 {
1007 PLIC->HART0_MMODE_ENA[inc] = 0U;
1008 PLIC->HART1_MMODE_ENA[inc] = 0U;
1009 PLIC->HART1_SMODE_ENA[inc] = 0U;
1010 PLIC->HART2_MMODE_ENA[inc] = 0U;
1011 PLIC->HART2_SMODE_ENA[inc] = 0U;
1012 PLIC->HART3_MMODE_ENA[inc] = 0U;
1013 PLIC->HART3_SMODE_ENA[inc] = 0U;
1014 PLIC->HART4_MMODE_ENA[inc] = 0U;
1015 PLIC->HART4_SMODE_ENA[inc] = 0U;
1016 }
1017
1018 /* clear any pending interrupts- in case already there */
1019 PLIC_ClearPendingIRQ();
1020 }
1021
1022 #ifdef __cplusplus
1023 }
1024 #endif
1025
1026 #endif /* MSS_PLIC_H */
1027
