1 /*******************************************************************************
2 * Copyright 2020 Microchip Corporation.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * TI DP83867ISRGZ PHY interface driver implementation for use with the G5 SoC
7 * Emulation Platform.
8 *
9 * This system uses the SGMII interface.
10 *
11 * The following are the default selections from the hardware strapping:
12 *
13 * RX_D0 - Strap option 4, PHY_ADD0 = 1, PHY_ADD1 = 1
14 * RX_D2 - Strap option 0, PHY_ADD2 = 0, PHY_ADD1 = 0
15 * RX_CTRL - Strap option 0, N/A - the following note applies:
16 * Strap modes 1 and 2 are not applicable for RX_CTRL. The RX_CTRL
17 * strap must be configured for strap mode 3 or strap mode 4. If the
18 * RX_CTRL pin cannot be strapped to mode 3 or mode 4, bit[7] of
19 * Configuration Register 4 (address 0x0031) must be cleared to 0.
20 * GPIO_0 - Strap option 0, RGMII Clock Skew RX[0] = 0. GPIO_0 is connected to
21 * I/O pin AR22 on the VU9P FPGA device.
22 * GPIO_1 - Strap option 0, RGMII Clock Skew RX[1] = 0,
23 * RGMII Clock Skew RX[2] = 0
24 * LED_2 - Strap option 2, RGMII Clock Skew TX[0] = 1,
25 * RGMII Clock Skew TX[1] = 0
26 * LED_1 - Strap option 2, RGMII Clock Skew TX[2] = 1, ANEG_SEL = 0
27 * LED_0 - Strap option 2, SGMII_Enable = 1, Mirror Enable = 0
28 *
29 */
30 #include "mpfs_hal/mss_hal.h"
31 #include "hal/hal.h"
32 #include "drivers/mss_ethernet_mac/mss_ethernet_registers.h"
33 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_regs.h"
34 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_sw_cfg.h"
35 #include "drivers/mss_ethernet_mac/mss_ethernet_mac.h"
36 #include "drivers/mss_ethernet_mac/phy.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #if MSS_MAC_USE_PHY_DP83867
43
44 /**************************************************************************/
45 /* Preprocessor Macros */
46 /**************************************************************************/
47
48 #define BMSR_AUTO_NEGOTIATION_COMPLETE (0x0020U)
49
50 /**************************************************************************//**
51 *
52 */
MSS_MAC_DP83867_phy_init(const void * v_this_mac,uint8_t phy_addr)53 void MSS_MAC_DP83867_phy_init(/* mss_mac_instance_t */ const void *v_this_mac, uint8_t phy_addr)
54 {
55 const mss_mac_instance_t *this_mac = (const mss_mac_instance_t *)v_this_mac;
56 uint16_t phy_reg;
57 (void)phy_addr;
58
59 /* Start by doing a software reset of the PHY */
60 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_CTRL, CTRL_SW_RESET);
61
62 /* Enable SGMII interface */
63 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_PHYCR);
64 phy_reg |= PHYCR_SGMII_EN;
65 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_PHYCR, phy_reg);
66
67 /* Enable 6 wire SGMII so that the 625MHz clock to the SGMII core is active */
68 #if 0
69 ti_write_extended_regs(this_mac, MII_TI_SGMIICTL1, SGMII_TYPE_6_WIRE);
70 #endif
71
72 if(GMII_SGMII == this_mac->interface_type)
73 {
74 /* Reset SGMII core side of I/F. */
75 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR);
76 phy_reg |= 0x9000U; /* Reset and start autonegotiation */
77 phy_reg &= 0xFBFFU; /* Clear Isolate bit */
78 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg);
79
80 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR);
81 phy_reg &= 0xFBFFU; /* Clear Isolate bit */
82 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg);
83
84 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR);
85 phy_reg |= 0x1000U; /* Kick off autonegotiation - belt and braces approach...*/
86 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg);
87 }
88 }
89
90
91 /**************************************************************************//**
92 *
93 */
MSS_MAC_DP83867_phy_set_link_speed(void * v_this_mac,uint32_t speed_duplex_select,mss_mac_speed_mode_t speed_mode)94 void MSS_MAC_DP83867_phy_set_link_speed(/* mss_mac_instance_t */ void *v_this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode)
95 {
96 mss_mac_instance_t *this_mac = (mss_mac_instance_t *)v_this_mac;
97 uint16_t phy_reg;
98 uint32_t inc;
99 uint32_t speed_select;
100 const uint16_t mii_advertise_bits[4] = {ADVERTISE_10FULL, ADVERTISE_10HALF,
101 ADVERTISE_100FULL, ADVERTISE_100HALF};
102
103 this_mac->speed_mode = speed_mode;
104
105 if(MSS_MAC_SPEED_AN == speed_mode) /* Set auto-negotiation advertisement. */
106 {
107 /* Set auto-negotiation advertisement. */
108
109 /* Set 10Mbps and 100Mbps advertisement. */
110 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_ADVERTISE);
111 phy_reg &= (uint16_t)(~(ADVERTISE_10HALF | ADVERTISE_10FULL |
112 ADVERTISE_100HALF | ADVERTISE_100FULL));
113
114 phy_reg |= 0x0C00U; /* Set Asymmetric pause and symmetric pause bits */
115
116 speed_select = speed_duplex_select;
117 for(inc = 0U; inc < 4U; ++inc)
118 {
119 uint32_t advertise;
120 advertise = speed_select & 0x00000001U;
121 if(advertise != 0U)
122 {
123 phy_reg |= mii_advertise_bits[inc];
124 }
125 speed_select = speed_select >> 1;
126 }
127
128 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_ADVERTISE, phy_reg);
129
130 /* Set 1000Mbps advertisement. */
131 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000);
132 phy_reg &= (uint16_t)(~(ADVERTISE_1000FULL | ADVERTISE_1000HALF));
133
134 if((speed_duplex_select & MSS_MAC_ANEG_1000M_FD) != 0U)
135 {
136 phy_reg |= ADVERTISE_1000FULL;
137 }
138
139 if((speed_duplex_select & MSS_MAC_ANEG_1000M_HD) != 0U)
140 {
141 phy_reg |= ADVERTISE_1000HALF;
142 }
143
144 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, phy_reg);
145 }
146 else
147 {
148 uint16_t temp_reg = 0x0000U; /* Default with 10M, half duplex */
149
150 if((MSS_MAC_10_FDX == this_mac->speed_mode) || (MSS_MAC_100_FDX == this_mac->speed_mode) || (MSS_MAC_1000_FDX == this_mac->speed_mode))
151 {
152 temp_reg |= BMCR_FULLDPLX;
153 }
154
155 if((MSS_MAC_100_FDX == this_mac->speed_mode) || (MSS_MAC_100_HDX == this_mac->speed_mode))
156 {
157 temp_reg |= BMCR_SPEED100;
158 }
159
160 if((MSS_MAC_1000_FDX == this_mac->speed_mode) || (MSS_MAC_1000_HDX == this_mac->speed_mode))
161 {
162 temp_reg |= BMCR_SPEED1000;
163 /* Set Master mode */
164 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000);
165 phy_reg |= 0x1800U;
166 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, phy_reg);
167 }
168
169 /* Apply static speed/duplex selection */
170 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_BMCR, temp_reg);
171
172 /* Full duplex mode or half duplex, single port device */
173 if((MSS_MAC_10_FDX == this_mac->speed_mode) || (MSS_MAC_100_FDX == this_mac->speed_mode) || (MSS_MAC_1000_FDX == this_mac->speed_mode))
174 {
175 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, (uint16_t)(ADVERTISE_1000FULL));
176 }
177 else
178 {
179 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, (uint16_t)(ADVERTISE_1000HALF));
180 }
181 }
182 }
183
184
185 /**************************************************************************//**
186 *
187 */
MSS_MAC_DP83867_phy_autonegotiate(const void * v_this_mac)188 void MSS_MAC_DP83867_phy_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac)
189 {
190 const mss_mac_instance_t *this_mac = (const mss_mac_instance_t *)v_this_mac;
191 volatile uint16_t phy_reg;
192 uint16_t autoneg_complete;
193 volatile uint32_t copper_aneg_timeout = 1000000U;
194 volatile uint32_t sgmii_aneg_timeout = 100000U;
195
196 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 2);
197 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 3);
198
199 /* Enable auto-negotiation. */
200 phy_reg = 0x1340U;
201 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_BMCR, phy_reg);
202
203 /* Wait for copper auto-negotiation to complete. */
204 do {
205 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_BMSR);
206 autoneg_complete = phy_reg & BMSR_AUTO_NEGOTIATION_COMPLETE;
207 --copper_aneg_timeout;
208 } while((0u == autoneg_complete) && (0U != copper_aneg_timeout) && (0xFFFFU != phy_reg));
209
210 if(GMII_SGMII == this_mac->interface_type)
211 {
212 /* Initiate auto-negotiation on the SGMII link. */
213 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, 0x00U);
214 phy_reg |= 0x1000U;
215 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, 0x00U, phy_reg);
216 phy_reg |= 0x0200U;
217 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, 0x00U, phy_reg);
218
219 /* Wait for SGMII auto-negotiation to complete. */
220 do {
221 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMSR);
222 autoneg_complete = phy_reg & BMSR_AUTO_NEGOTIATION_COMPLETE;
223 --sgmii_aneg_timeout;
224 } while((0U == autoneg_complete) && (0U != sgmii_aneg_timeout));
225 }
226 }
227
228
229 /**************************************************************************//**
230 *
231 */
MSS_MAC_DP83867_mac_autonegotiate(const void * v_this_mac)232 void MSS_MAC_DP83867_mac_autonegotiate(/* mss_mac_instance_t */ const void *v_this_mac)
233 {
234 (void)v_this_mac;
235 }
236
237
238 /**************************************************************************//**
239 *
240 */
MSS_MAC_DP83867_phy_get_link_status(const void * v_this_mac,mss_mac_speed_t * speed,uint8_t * fullduplex)241 uint8_t MSS_MAC_DP83867_phy_get_link_status
242 (
243 /* mss_mac_instance_t*/ const void *v_this_mac,
244 mss_mac_speed_t * speed,
245 uint8_t * fullduplex
246 )
247 {
248 const mss_mac_instance_t *this_mac = (const mss_mac_instance_t *)v_this_mac;
249 uint16_t phy_reg;
250 uint16_t link_up;
251 uint8_t link_status;
252
253 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_BMSR);
254 link_up = phy_reg & BMSR_LSTATUS;
255
256 if(link_up != MSS_MAC_LINK_DOWN)
257 {
258 uint16_t duplex;
259 uint16_t speed_field;
260
261 /* Link is up. */
262 link_status = MSS_MAC_LINK_UP;
263
264 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x11U); /* Device Auxillary Control and Status */
265 duplex = phy_reg & 0x2000U;
266 speed_field = phy_reg >> 14;
267
268 if(MSS_MAC_HALF_DUPLEX == duplex)
269 {
270 *fullduplex = MSS_MAC_HALF_DUPLEX;
271 }
272 else
273 {
274 *fullduplex = MSS_MAC_FULL_DUPLEX;
275 }
276
277 switch(speed_field)
278 {
279 case 0U:
280 *speed = MSS_MAC_10MBPS;
281 break;
282
283 case 1U:
284 *speed = MSS_MAC_100MBPS;
285 break;
286
287 case 2U:
288 *speed = MSS_MAC_1000MBPS;
289 break;
290
291 default:
292 link_status = (uint8_t)MSS_MAC_LINK_DOWN;
293 break;
294 }
295 }
296 else
297 {
298 /* Link is down. */
299 link_status = (uint8_t)MSS_MAC_LINK_DOWN;
300 }
301
302 return link_status;
303 }
304
305
306 /**************************************************************************//**
307 *
308 */
309
310 /*
311 * TI DP83867 PHY has 32 standard registers and a collection of additional
312 * registers that are accessed through the use of registers 0x0D and 0x0E.
313 * Register 0x0D (REGCR) holds the control bits which determine what register
314 * 0x0E (ADDAR) does.
315 *
316 * The following extended registers are available:
317 *
318 * 0x0025 - Testmode Channel Control
319 * 0x002D - Fast Link Drop Configuration
320 * 0x0031 - Configuration Register 4
321 * 0x0032 - RGMII Control Register
322 * 0x0033 - RGMII Control Register 2
323 * 0x0037 - SGMII Auto-Negotiation Status
324 * 0x0043 - 100BASE-TX Configuration
325 * 0x0055 - Skew FIFO Status
326 * 0x006E - Strap Configuration Status Register 1
327 * 0x006F - Strap Configuration Status Register 2
328 * 0x0071 - BIST Control and Status Register 1
329 * 0x0072 - BIST Control and Status Register 2
330 * 0x0086 - RGMII Delay Control Register
331 * 0x00D3 - SGMII Control Register 1
332 * 0x00E9 - Sync FIFO Control
333 * 0x00FE - Loopback Configuration Register
334 * 0x0134 - Receive Configuration Register
335 * 0x0135 - Receive Status Register
336 * 0x0136 - Pattern Match Data Register 1
337 * 0x0137 - Pattern Match Data Register 2
338 * 0x0138 - Pattern Match Data Register 3
339 * 0x0139 - SecureOn Pass Register 1
340 * 0x013A - SecureOn Pass Register 2
341 * 0x013B - SecureOn Pass Register 3
342 * 0x013C - 0x015B - Receive Pattern Registers 1 to 32
343 * 0x015C - Receive Pattern Byte Mask Register 1
344 * 0x015D - Receive Pattern Byte Mask Register 2
345 * 0x015E - Receive Pattern Byte Mask Register 3
346 * 0x015F - Receive Pattern Byte Mask Register 4
347 * 0x0161 - Receive Pattern Control
348 * 0x016F - 10M SGMII Configuration
349 * 0x0170 - I/O configuration
350 * 0x0172 - GPIO Mux Control Register
351 * 0x0180 - TDR General Configuration Register 1
352 * 0x01A7 - Advanced Link Cable Diagnostics Control Register
353 * 0x0000 - MMD3 PCS Control Register - indirect addressing only
354 *
355 */
356
357 uint16_t phy_reg_list[25] =
358 {
359 0x0025U, /* 00 Testmode Channel Control */
360 0x002DU, /* 01 Fast Link Drop Configuration */
361 0x0031U, /* 02 Configuration Register 4 */
362 0x0032U, /* 03 RGMII Control Register */
363 0x0033U, /* 04 RGMII Control Register 2 */
364 0x0037U, /* 05 SGMII Auto-Negotiation Status */
365 0x0043U, /* 06 100BASE-TX Configuration */
366 0x0055U, /* 07 Skew FIFO Status */
367 0x006EU, /* 08 Strap Configuration Status Register 1 */
368 0x006FU, /* 09 Strap Configuration Status Register 2 */
369 0x0071U, /* 10 BIST Control and Status Register 1 */
370 0x0072U, /* 11 BIST Control and Status Register 2 */
371 0x0086U, /* 12 RGMII Delay Control Register */
372 0x00D3U, /* 13 SGMII Control Register 1 */
373 0x00E9U, /* 14 Sync FIFO Control */
374 0x00FEU, /* 15 Loopback Configuration Register */
375 0x0134U, /* 16 Receive Configuration Register */
376 0x0135U, /* 17 Receive Status Register */
377 0x016FU, /* 18 10M SGMII Configuration */
378 0x0170U, /* 19 I/O configuration */
379 0x0172U, /* 20 GPIO Mux Control Register */
380 0x0180U, /* 21 TDR General Configuration Register 1 */
381 0x01A7U, /* 22 Advanced Link Cable Diagnostics Control Register */
382 0x0000U, /* 23 MMD3 PCS Control Register - indirect addressing only */
383 0xFFFFU /* 24 End of list... */
384 };
385
386 uint16_t TI_reg_0[32];
387 uint16_t TI_reg_1[25];
388 uint16_t TI_MSS_SGMII_reg[17];
389 uint32_t TI_MSS_MAC_reg[80];
390 uint32_t TI_MSS_PLIC_REG[80];
391
392
393 void dump_ti_regs(const mss_mac_instance_t * this_mac);
dump_ti_regs(const mss_mac_instance_t * this_mac)394 void dump_ti_regs(const mss_mac_instance_t * this_mac)
395 {
396 int32_t count;
397 uint16_t old_ctrl;
398 uint16_t old_addr;
399 uint32_t *pbigdata;
400 volatile psr_t lev;
401
402 for(count = 0; count <= 0x1F; count++)
403 {
404 lev = HAL_disable_interrupts();
405 TI_reg_0[count] = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, (uint8_t)count);
406 HAL_restore_interrupts(lev);
407 }
408
409 lev = HAL_disable_interrupts();
410 old_ctrl = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR); /* Fetch current REGCR value */
411 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
412 old_addr = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR); /* Fetch current indirect address */
413 HAL_restore_interrupts(lev);
414
415 for(count = 0; 0xFFFFU != phy_reg_list[count]; count++)
416 {
417 lev = HAL_disable_interrupts();
418 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
419 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, phy_reg_list[count]); /* Select new indirect Address */
420 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x401FU); /* Select simple data mode */
421 TI_reg_1[count] = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR); /* Finally, read the data */
422 HAL_restore_interrupts(lev);
423 }
424
425 lev = HAL_disable_interrupts();
426 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
427 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, old_addr); /* Restore old address */
428 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, old_ctrl); /* Restore old control mode */
429 HAL_restore_interrupts(lev);
430
431 for(count = 0; count <= 0x10; count++)
432 {
433 TI_MSS_SGMII_reg[count] = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, (uint8_t)count);
434 }
435
436 pbigdata = (uint32_t *)0x20110000UL;
437 for(count = 0; count < 19; count++)
438 {
439 TI_MSS_MAC_reg[count] = *pbigdata;
440 pbigdata++;
441 }
442 pbigdata =(uint32_t *)0x0C000000UL;
443 for(count = 0; count < 8; count++)
444 {
445 TI_MSS_PLIC_REG[count] = *pbigdata;
446 pbigdata++;
447 }
448 }
449
450
451 /**************************************************************************//**
452 *
453 */
ti_read_extended_regs(const void * v_this_mac,uint16_t reg)454 uint16_t ti_read_extended_regs(/* mss_mac_instance_t*/ const void *v_this_mac, uint16_t reg)
455 {
456 const mss_mac_instance_t *this_mac = (const mss_mac_instance_t *)v_this_mac;
457 uint16_t old_ctrl;
458 uint16_t old_addr;
459 uint16_t ret_val = 0U;
460 volatile psr_t lev;
461
462 lev = HAL_disable_interrupts();
463 old_ctrl = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR); /* Fetch current REGCR value */
464 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
465 old_addr = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR); /* Fetch current indirect address */
466
467 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
468 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, reg); /* Select new indirect Address */
469 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x401FU); /* Select simple data mode */
470 ret_val = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR); /* Finally, read the data */
471
472 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
473 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, old_addr); /* Restore old address */
474 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, old_ctrl); /* Restore old control mode */
475 HAL_restore_interrupts(lev);
476
477 return(ret_val);
478 }
479
480
481 /**************************************************************************//**
482 *
483 */
ti_write_extended_regs(const void * v_this_mac,uint16_t reg,uint16_t data)484 void ti_write_extended_regs(/* mss_mac_instance_t*/ const void *v_this_mac, uint16_t reg, uint16_t data)
485 {
486 const mss_mac_instance_t *this_mac = (const mss_mac_instance_t *)v_this_mac;
487 uint16_t old_ctrl;
488 uint16_t old_addr;
489 volatile psr_t lev;
490
491 lev = HAL_disable_interrupts();
492 old_ctrl = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR); /* Fetch current REGCR value */
493 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
494 old_addr = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR); /* Fetch current indirect address */
495
496 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
497 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, reg); /* Select new indirect Address */
498 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x401FU); /* Select simple data mode */
499 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, data); /* Now write the data */
500
501 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, 0x001FU); /* Select Address mode */
502 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_ADDAR, old_addr); /* Restore old address */
503 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_REGCR, old_ctrl); /* Restore old control mode */
504 HAL_restore_interrupts(lev);
505 }
506 #endif /* #if defined(TARGET_ALOE) */
507 #ifdef __cplusplus
508 }
509 #endif
510
511 /******************************** END OF FILE ******************************/
512
513
514
515
516
517
518
