1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_ddrc.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_DDRC_H_ 28 #define HW_DDRC_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP) 36 /*IP Blk = ADDR_MAP Access=RW */ 37 #define LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP 0x00000000UL 38 /* CFG_MANUAL_ADDRESS_MAP [0:32] RW value= 0x0 */ 39 #endif 40 #if !defined (LIBERO_SETTING_CFG_CHIPADDR_MAP) 41 /*IP Blk = ADDR_MAP Access=RW */ 42 #define LIBERO_SETTING_CFG_CHIPADDR_MAP 0x0000001DUL 43 /* CFG_CHIPADDR_MAP [0:32] RW value= 0x00001D */ 44 #endif 45 #if !defined (LIBERO_SETTING_CFG_CIDADDR_MAP) 46 /*IP Blk = ADDR_MAP Access=RW */ 47 #define LIBERO_SETTING_CFG_CIDADDR_MAP 0x00000000UL 48 /* CFG_CIDADDR_MAP [0:32] RW value= 0x00000000 */ 49 #endif 50 #if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW) 51 /*IP Blk = ADDR_MAP Access=RW */ 52 #define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW 0x00000004UL 53 /* CFG_MB_AUTOPCH_COL_BIT_POS_LOW [0:32] RW value= 0x00000004 */ 54 #endif 55 #if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH) 56 /*IP Blk = ADDR_MAP Access=RW */ 57 #define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH 0x0000000AUL 58 /* CFG_MB_AUTOPCH_COL_BIT_POS_HIGH [0:32] RW value= 0x0000000A */ 59 #endif 60 #if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_0) 61 /*IP Blk = ADDR_MAP Access=RW */ 62 #define LIBERO_SETTING_CFG_BANKADDR_MAP_0 0x0000C2CAUL 63 /* CFG_BANKADDR_MAP_0 [0:32] RW value= 0x00C2CA */ 64 #endif 65 #if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_1) 66 /*IP Blk = ADDR_MAP Access=RW */ 67 #define LIBERO_SETTING_CFG_BANKADDR_MAP_1 0x00000000UL 68 /* CFG_BANKADDR_MAP_1 [0:32] RW value= 0x0 */ 69 #endif 70 #if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_0) 71 /*IP Blk = ADDR_MAP Access=RW */ 72 #define LIBERO_SETTING_CFG_ROWADDR_MAP_0 0x9140F38DUL 73 /* CFG_ROWADDR_MAP_0 [0:32] RW value= 0x9140F38D */ 74 #endif 75 #if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_1) 76 /*IP Blk = ADDR_MAP Access=RW */ 77 #define LIBERO_SETTING_CFG_ROWADDR_MAP_1 0x75955134UL 78 /* CFG_ROWADDR_MAP_1 [0:32] RW value= 0x75955134 */ 79 #endif 80 #if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_2) 81 /*IP Blk = ADDR_MAP Access=RW */ 82 #define LIBERO_SETTING_CFG_ROWADDR_MAP_2 0x71B69961UL 83 /* CFG_ROWADDR_MAP_2 [0:32] RW value= 0x71B69961 */ 84 #endif 85 #if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_3) 86 /*IP Blk = ADDR_MAP Access=RW */ 87 #define LIBERO_SETTING_CFG_ROWADDR_MAP_3 0x00000000UL 88 /* CFG_ROWADDR_MAP_3 [0:32] RW value= 0x000 */ 89 #endif 90 #if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_0) 91 /*IP Blk = ADDR_MAP Access=RW */ 92 #define LIBERO_SETTING_CFG_COLADDR_MAP_0 0x440C2040UL 93 /* CFG_COLADDR_MAP_0 [0:32] RW value= 0x440C2040 */ 94 #endif 95 #if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_1) 96 /*IP Blk = ADDR_MAP Access=RW */ 97 #define LIBERO_SETTING_CFG_COLADDR_MAP_1 0x02481C61UL 98 /* CFG_COLADDR_MAP_1 [0:32] RW value= 0x02481C61 */ 99 #endif 100 #if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_2) 101 /*IP Blk = ADDR_MAP Access=RW */ 102 #define LIBERO_SETTING_CFG_COLADDR_MAP_2 0x00000000UL 103 /* CFG_COLADDR_MAP_2 [0:32] RW value= 0x00000000 */ 104 #endif 105 #if !defined (LIBERO_SETTING_CFG_VRCG_ENABLE) 106 /*IP Blk = MC_BASE3 Access=RW */ 107 #define LIBERO_SETTING_CFG_VRCG_ENABLE 0x00000140UL 108 /* CFG_VRCG_ENABLE [0:32] RW value= 0x00000140 */ 109 #endif 110 #if !defined (LIBERO_SETTING_CFG_VRCG_DISABLE) 111 /*IP Blk = MC_BASE3 Access=RW */ 112 #define LIBERO_SETTING_CFG_VRCG_DISABLE 0x000000A0UL 113 /* CFG_VRCG_DISABLE [0:32] RW value= 0x000000A0 */ 114 #endif 115 #if !defined (LIBERO_SETTING_CFG_WRITE_LATENCY_SET) 116 /*IP Blk = MC_BASE3 Access=RW */ 117 #define LIBERO_SETTING_CFG_WRITE_LATENCY_SET 0x00000000UL 118 /* CFG_WRITE_LATENCY_SET [0:32] RW value= 0x00000000 */ 119 #endif 120 #if !defined (LIBERO_SETTING_CFG_THERMAL_OFFSET) 121 /*IP Blk = MC_BASE3 Access=RW */ 122 #define LIBERO_SETTING_CFG_THERMAL_OFFSET 0x00000000UL 123 /* CFG_THERMAL_OFFSET [0:32] RW value= 0x00000000 */ 124 #endif 125 #if !defined (LIBERO_SETTING_CFG_SOC_ODT) 126 /*IP Blk = MC_BASE3 Access=RW */ 127 #define LIBERO_SETTING_CFG_SOC_ODT 0x00000006UL 128 /* CFG_SOC_ODT [0:32] RW value= 0x6 */ 129 #endif 130 #if !defined (LIBERO_SETTING_CFG_ODTE_CK) 131 /*IP Blk = MC_BASE3 Access=RW */ 132 #define LIBERO_SETTING_CFG_ODTE_CK 0x00000000UL 133 /* CFG_ODTE_CK [0:32] RW value= 0x0 */ 134 #endif 135 #if !defined (LIBERO_SETTING_CFG_ODTE_CS) 136 /*IP Blk = MC_BASE3 Access=RW */ 137 #define LIBERO_SETTING_CFG_ODTE_CS 0x00000000UL 138 /* CFG_ODTE_CS [0:32] RW value= 0x0 */ 139 #endif 140 #if !defined (LIBERO_SETTING_CFG_ODTD_CA) 141 /*IP Blk = MC_BASE3 Access=RW */ 142 #define LIBERO_SETTING_CFG_ODTD_CA 0x00000000UL 143 /* CFG_ODTD_CA [0:32] RW value= 0x0 */ 144 #endif 145 #if !defined (LIBERO_SETTING_CFG_LPDDR4_FSP_OP) 146 /*IP Blk = MC_BASE3 Access=RW */ 147 #define LIBERO_SETTING_CFG_LPDDR4_FSP_OP 0x00000001UL 148 /* CFG_LPDDR4_FSP_OP [0:32] RW value= 0x1 */ 149 #endif 150 #if !defined (LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX) 151 /*IP Blk = MC_BASE3 Access=RW */ 152 #define LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX 0x00000001UL 153 /* CFG_GENERATE_REFRESH_ON_SRX [0:32] RW value= 0x00000001 */ 154 #endif 155 #if !defined (LIBERO_SETTING_CFG_DBI_CL) 156 /*IP Blk = MC_BASE3 Access=RW */ 157 #define LIBERO_SETTING_CFG_DBI_CL 0x00000016UL 158 /* CFG_DBI_CL [0:32] RW value= 0x00000016 */ 159 #endif 160 #if !defined (LIBERO_SETTING_CFG_NON_DBI_CL) 161 /*IP Blk = MC_BASE3 Access=RW */ 162 #define LIBERO_SETTING_CFG_NON_DBI_CL 0x00000016UL 163 /* CFG_NON_DBI_CL [0:32] RW value= 0x00000016 */ 164 #endif 165 #if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0) 166 /*IP Blk = MC_BASE3 Access=RW */ 167 #define LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0 0x00000000UL 168 /* INIT_FORCE_WRITE_DATA_0 [0:32] RW value= 0x00000000 */ 169 #endif 170 #if !defined (LIBERO_SETTING_CFG_WRITE_CRC) 171 /*IP Blk = MC_BASE1 Access=RW */ 172 #define LIBERO_SETTING_CFG_WRITE_CRC 0x00000000UL 173 /* CFG_WRITE_CRC [0:32] RW value= 0x00000000 */ 174 #endif 175 #if !defined (LIBERO_SETTING_CFG_MPR_READ_FORMAT) 176 /*IP Blk = MC_BASE1 Access=RW */ 177 #define LIBERO_SETTING_CFG_MPR_READ_FORMAT 0x00000000UL 178 /* CFG_MPR_READ_FORMAT [0:32] RW value= 0x00000000 */ 179 #endif 180 #if !defined (LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM) 181 /*IP Blk = MC_BASE1 Access=RW */ 182 #define LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM 0x00000000UL 183 /* CFG_WR_CMD_LAT_CRC_DM [0:32] RW value= 0x00000000 */ 184 #endif 185 #if !defined (LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE) 186 /*IP Blk = MC_BASE1 Access=RW */ 187 #define LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE 0x00000000UL 188 /* CFG_FINE_GRAN_REF_MODE [0:32] RW value= 0x00000000 */ 189 #endif 190 #if !defined (LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT) 191 /*IP Blk = MC_BASE1 Access=RW */ 192 #define LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT 0x00000000UL 193 /* CFG_TEMP_SENSOR_READOUT [0:32] RW value= 0x00000000 */ 194 #endif 195 #if !defined (LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN) 196 /*IP Blk = MC_BASE1 Access=RW */ 197 #define LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN 0x00000000UL 198 /* CFG_PER_DRAM_ADDR_EN [0:32] RW value= 0x00000000 */ 199 #endif 200 #if !defined (LIBERO_SETTING_CFG_GEARDOWN_MODE) 201 /*IP Blk = MC_BASE1 Access=RW */ 202 #define LIBERO_SETTING_CFG_GEARDOWN_MODE 0x00000000UL 203 /* CFG_GEARDOWN_MODE [0:32] RW value= 0x00000000 */ 204 #endif 205 #if !defined (LIBERO_SETTING_CFG_WR_PREAMBLE) 206 /*IP Blk = MC_BASE1 Access=RW */ 207 #define LIBERO_SETTING_CFG_WR_PREAMBLE 0x00000001UL 208 /* CFG_WR_PREAMBLE [0:32] RW value= 0x1 */ 209 #endif 210 #if !defined (LIBERO_SETTING_CFG_RD_PREAMBLE) 211 /*IP Blk = MC_BASE1 Access=RW */ 212 #define LIBERO_SETTING_CFG_RD_PREAMBLE 0x00000000UL 213 /* CFG_RD_PREAMBLE [0:32] RW value= 0x0 */ 214 #endif 215 #if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE) 216 /*IP Blk = MC_BASE1 Access=RW */ 217 #define LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE 0x00000000UL 218 /* CFG_RD_PREAMB_TRN_MODE [0:32] RW value= 0x00000000 */ 219 #endif 220 #if !defined (LIBERO_SETTING_CFG_SR_ABORT) 221 /*IP Blk = MC_BASE1 Access=RW */ 222 #define LIBERO_SETTING_CFG_SR_ABORT 0x00000000UL 223 /* CFG_SR_ABORT [0:32] RW value= 0x0 */ 224 #endif 225 #if !defined (LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY) 226 /*IP Blk = MC_BASE1 Access=RW */ 227 #define LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY 0x00000000UL 228 /* CFG_CS_TO_CMDADDR_LATENCY [0:32] RW value= 0x00000000 */ 229 #endif 230 #if !defined (LIBERO_SETTING_CFG_INT_VREF_MON) 231 /*IP Blk = MC_BASE1 Access=RW */ 232 #define LIBERO_SETTING_CFG_INT_VREF_MON 0x00000000UL 233 /* CFG_INT_VREF_MON [0:32] RW value= 0x00000000 */ 234 #endif 235 #if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE) 236 /*IP Blk = MC_BASE1 Access=RW */ 237 #define LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE 0x00000000UL 238 /* CFG_TEMP_CTRL_REF_MODE [0:32] RW value= 0x00000000 */ 239 #endif 240 #if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE) 241 /*IP Blk = MC_BASE1 Access=RW */ 242 #define LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE 0x00000000UL 243 /* CFG_TEMP_CTRL_REF_RANGE [0:32] RW value= 0x00000000 */ 244 #endif 245 #if !defined (LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE) 246 /*IP Blk = MC_BASE1 Access=RW */ 247 #define LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE 0x00000000UL 248 /* CFG_MAX_PWR_DOWN_MODE [0:32] RW value= 0x00000000 */ 249 #endif 250 #if !defined (LIBERO_SETTING_CFG_READ_DBI) 251 /*IP Blk = MC_BASE1 Access=RW */ 252 #define LIBERO_SETTING_CFG_READ_DBI 0x00000000UL 253 /* CFG_READ_DBI [0:32] RW value= 0x00000000 */ 254 #endif 255 #if !defined (LIBERO_SETTING_CFG_WRITE_DBI) 256 /*IP Blk = MC_BASE1 Access=RW */ 257 #define LIBERO_SETTING_CFG_WRITE_DBI 0x00000000UL 258 /* CFG_WRITE_DBI [0:32] RW value= 0x00000000 */ 259 #endif 260 #if !defined (LIBERO_SETTING_CFG_DATA_MASK) 261 /*IP Blk = MC_BASE1 Access=RW */ 262 #define LIBERO_SETTING_CFG_DATA_MASK 0x00000001UL 263 /* CFG_DATA_MASK [0:32] RW value= 0x1 */ 264 #endif 265 #if !defined (LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR) 266 /*IP Blk = MC_BASE1 Access=RW */ 267 #define LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR 0x00000000UL 268 /* CFG_CA_PARITY_PERSIST_ERR [0:32] RW value= 0x00000000 */ 269 #endif 270 #if !defined (LIBERO_SETTING_CFG_RTT_PARK) 271 /*IP Blk = MC_BASE1 Access=RW */ 272 #define LIBERO_SETTING_CFG_RTT_PARK 0x00000000UL 273 /* CFG_RTT_PARK [0:32] RW value= 0x00000000 */ 274 #endif 275 #if !defined (LIBERO_SETTING_CFG_ODT_INBUF_4_PD) 276 /*IP Blk = MC_BASE1 Access=RW */ 277 #define LIBERO_SETTING_CFG_ODT_INBUF_4_PD 0x00000000UL 278 /* CFG_ODT_INBUF_4_PD [0:32] RW value= 0x00000000 */ 279 #endif 280 #if !defined (LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS) 281 /*IP Blk = MC_BASE1 Access=RW */ 282 #define LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS 0x00000000UL 283 /* CFG_CA_PARITY_ERR_STATUS [0:32] RW value= 0x00000000 */ 284 #endif 285 #if !defined (LIBERO_SETTING_CFG_CRC_ERROR_CLEAR) 286 /*IP Blk = MC_BASE1 Access=RW */ 287 #define LIBERO_SETTING_CFG_CRC_ERROR_CLEAR 0x00000000UL 288 /* CFG_CRC_ERROR_CLEAR [0:32] RW value= 0x00000000 */ 289 #endif 290 #if !defined (LIBERO_SETTING_CFG_CA_PARITY_LATENCY) 291 /*IP Blk = MC_BASE1 Access=RW */ 292 #define LIBERO_SETTING_CFG_CA_PARITY_LATENCY 0x00000000UL 293 /* CFG_CA_PARITY_LATENCY [0:32] RW value= 0x00000000 */ 294 #endif 295 #if !defined (LIBERO_SETTING_CFG_CCD_S) 296 /*IP Blk = MC_BASE1 Access=RW */ 297 #define LIBERO_SETTING_CFG_CCD_S 0x00000005UL 298 /* CFG_CCD_S [0:32] RW value= 0x00000005 */ 299 #endif 300 #if !defined (LIBERO_SETTING_CFG_CCD_L) 301 /*IP Blk = MC_BASE1 Access=RW */ 302 #define LIBERO_SETTING_CFG_CCD_L 0x00000006UL 303 /* CFG_CCD_L [0:32] RW value= 0x00000006 */ 304 #endif 305 #if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE) 306 /*IP Blk = MC_BASE1 Access=RW */ 307 #define LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE 0x00000000UL 308 /* CFG_VREFDQ_TRN_ENABLE [0:32] RW value= 0x00000000 */ 309 #endif 310 #if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE) 311 /*IP Blk = MC_BASE1 Access=RW */ 312 #define LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE 0x00000000UL 313 /* CFG_VREFDQ_TRN_RANGE [0:32] RW value= 0x00000000 */ 314 #endif 315 #if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE) 316 /*IP Blk = MC_BASE1 Access=RW */ 317 #define LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE 0x00000000UL 318 /* CFG_VREFDQ_TRN_VALUE [0:32] RW value= 0x00000000 */ 319 #endif 320 #if !defined (LIBERO_SETTING_CFG_RRD_S) 321 /*IP Blk = MC_BASE1 Access=RW */ 322 #define LIBERO_SETTING_CFG_RRD_S 0x00000004UL 323 /* CFG_RRD_S [0:32] RW value= 0x00000004 */ 324 #endif 325 #if !defined (LIBERO_SETTING_CFG_RRD_L) 326 /*IP Blk = MC_BASE1 Access=RW */ 327 #define LIBERO_SETTING_CFG_RRD_L 0x00000003UL 328 /* CFG_RRD_L [0:32] RW value= 0x00000003 */ 329 #endif 330 #if !defined (LIBERO_SETTING_CFG_WTR_S) 331 /*IP Blk = MC_BASE1 Access=RW */ 332 #define LIBERO_SETTING_CFG_WTR_S 0x00000003UL 333 /* CFG_WTR_S [0:32] RW value= 0x00000003 */ 334 #endif 335 #if !defined (LIBERO_SETTING_CFG_WTR_L) 336 /*IP Blk = MC_BASE1 Access=RW */ 337 #define LIBERO_SETTING_CFG_WTR_L 0x00000003UL 338 /* CFG_WTR_L [0:32] RW value= 0x00000003 */ 339 #endif 340 #if !defined (LIBERO_SETTING_CFG_WTR_S_CRC_DM) 341 /*IP Blk = MC_BASE1 Access=RW */ 342 #define LIBERO_SETTING_CFG_WTR_S_CRC_DM 0x00000003UL 343 /* CFG_WTR_S_CRC_DM [0:32] RW value= 0x00000003 */ 344 #endif 345 #if !defined (LIBERO_SETTING_CFG_WTR_L_CRC_DM) 346 /*IP Blk = MC_BASE1 Access=RW */ 347 #define LIBERO_SETTING_CFG_WTR_L_CRC_DM 0x00000003UL 348 /* CFG_WTR_L_CRC_DM [0:32] RW value= 0x00000003 */ 349 #endif 350 #if !defined (LIBERO_SETTING_CFG_WR_CRC_DM) 351 /*IP Blk = MC_BASE1 Access=RW */ 352 #define LIBERO_SETTING_CFG_WR_CRC_DM 0x00000006UL 353 /* CFG_WR_CRC_DM [0:32] RW value= 0x00000006 */ 354 #endif 355 #if !defined (LIBERO_SETTING_CFG_RFC1) 356 /*IP Blk = MC_BASE1 Access=RW */ 357 #define LIBERO_SETTING_CFG_RFC1 0x00000036UL 358 /* CFG_RFC1 [0:32] RW value= 0x00000036 */ 359 #endif 360 #if !defined (LIBERO_SETTING_CFG_RFC2) 361 /*IP Blk = MC_BASE1 Access=RW */ 362 #define LIBERO_SETTING_CFG_RFC2 0x00000036UL 363 /* CFG_RFC2 [0:32] RW value= 0x00000036 */ 364 #endif 365 #if !defined (LIBERO_SETTING_CFG_RFC4) 366 /*IP Blk = MC_BASE1 Access=RW */ 367 #define LIBERO_SETTING_CFG_RFC4 0x00000036UL 368 /* CFG_RFC4 [0:32] RW value= 0x00000036 */ 369 #endif 370 #if !defined (LIBERO_SETTING_CFG_NIBBLE_DEVICES) 371 /*IP Blk = MC_BASE1 Access=RW */ 372 #define LIBERO_SETTING_CFG_NIBBLE_DEVICES 0x00000000UL 373 /* CFG_NIBBLE_DEVICES [0:32] RW value= 0x0 */ 374 #endif 375 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0) 376 /*IP Blk = MC_BASE1 Access=RW */ 377 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0 0x81881881UL 378 /* CFG_BIT_MAP_INDEX_CS0_0 [0:32] RW value= 0x81881881 */ 379 #endif 380 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1) 381 /*IP Blk = MC_BASE1 Access=RW */ 382 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1 0x00008818UL 383 /* CFG_BIT_MAP_INDEX_CS0_1 [0:32] RW value= 0x00008818 */ 384 #endif 385 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0) 386 /*IP Blk = MC_BASE1 Access=RW */ 387 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0 0xA92A92A9UL 388 /* CFG_BIT_MAP_INDEX_CS1_0 [0:32] RW value= 0xa92a92a9 */ 389 #endif 390 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1) 391 /*IP Blk = MC_BASE1 Access=RW */ 392 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1 0x00002A92UL 393 /* CFG_BIT_MAP_INDEX_CS1_1 [0:32] RW value= 0x00002a92 */ 394 #endif 395 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0) 396 /*IP Blk = MC_BASE1 Access=RW */ 397 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0 0xC28C28C2UL 398 /* CFG_BIT_MAP_INDEX_CS2_0 [0:32] RW value= 0xc28c28c2 */ 399 #endif 400 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1) 401 /*IP Blk = MC_BASE1 Access=RW */ 402 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1 0x00008C28UL 403 /* CFG_BIT_MAP_INDEX_CS2_1 [0:32] RW value= 0x00008c28 */ 404 #endif 405 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0) 406 /*IP Blk = MC_BASE1 Access=RW */ 407 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0 0xEA2EA2EAUL 408 /* CFG_BIT_MAP_INDEX_CS3_0 [0:32] RW value= 0xea2ea2ea */ 409 #endif 410 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1) 411 /*IP Blk = MC_BASE1 Access=RW */ 412 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1 0x00002EA2UL 413 /* CFG_BIT_MAP_INDEX_CS3_1 [0:32] RW value= 0x00002ea2 */ 414 #endif 415 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0) 416 /*IP Blk = MC_BASE1 Access=RW */ 417 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0 0x03903903UL 418 /* CFG_BIT_MAP_INDEX_CS4_0 [0:32] RW value= 0x03903903 */ 419 #endif 420 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1) 421 /*IP Blk = MC_BASE1 Access=RW */ 422 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1 0x00009039UL 423 /* CFG_BIT_MAP_INDEX_CS4_1 [0:32] RW value= 0x00009039 */ 424 #endif 425 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0) 426 /*IP Blk = MC_BASE1 Access=RW */ 427 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0 0x2B32B32BUL 428 /* CFG_BIT_MAP_INDEX_CS5_0 [0:32] RW value= 0x2b32b32b */ 429 #endif 430 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1) 431 /*IP Blk = MC_BASE1 Access=RW */ 432 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1 0x000032B3UL 433 /* CFG_BIT_MAP_INDEX_CS5_1 [0:32] RW value= 0x000032b3 */ 434 #endif 435 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0) 436 /*IP Blk = MC_BASE1 Access=RW */ 437 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0 0x44944944UL 438 /* CFG_BIT_MAP_INDEX_CS6_0 [0:32] RW value= 0x44944944 */ 439 #endif 440 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1) 441 /*IP Blk = MC_BASE1 Access=RW */ 442 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1 0x00009449UL 443 /* CFG_BIT_MAP_INDEX_CS6_1 [0:32] RW value= 0x00009449 */ 444 #endif 445 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0) 446 /*IP Blk = MC_BASE1 Access=RW */ 447 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0 0x6C36C36CUL 448 /* CFG_BIT_MAP_INDEX_CS7_0 [0:32] RW value= 0x6c36c36c */ 449 #endif 450 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1) 451 /*IP Blk = MC_BASE1 Access=RW */ 452 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1 0x000036C3UL 453 /* CFG_BIT_MAP_INDEX_CS7_1 [0:32] RW value= 0x000036c3 */ 454 #endif 455 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0) 456 /*IP Blk = MC_BASE1 Access=RW */ 457 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0 0x85985985UL 458 /* CFG_BIT_MAP_INDEX_CS8_0 [0:32] RW value= 0x85985985 */ 459 #endif 460 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1) 461 /*IP Blk = MC_BASE1 Access=RW */ 462 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1 0x00009859UL 463 /* CFG_BIT_MAP_INDEX_CS8_1 [0:32] RW value= 0x00009859 */ 464 #endif 465 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0) 466 /*IP Blk = MC_BASE1 Access=RW */ 467 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0 0xAD3AD3ADUL 468 /* CFG_BIT_MAP_INDEX_CS9_0 [0:32] RW value= 0xad3ad3ad */ 469 #endif 470 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1) 471 /*IP Blk = MC_BASE1 Access=RW */ 472 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1 0x00003AD3UL 473 /* CFG_BIT_MAP_INDEX_CS9_1 [0:32] RW value= 0x00003ad3 */ 474 #endif 475 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0) 476 /*IP Blk = MC_BASE1 Access=RW */ 477 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0 0xC69C69C6UL 478 /* CFG_BIT_MAP_INDEX_CS10_0 [0:32] RW value= 0xc69c69c6 */ 479 #endif 480 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1) 481 /*IP Blk = MC_BASE1 Access=RW */ 482 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1 0x00009C69UL 483 /* CFG_BIT_MAP_INDEX_CS10_1 [0:32] RW value= 0x00009c69 */ 484 #endif 485 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0) 486 /*IP Blk = MC_BASE1 Access=RW */ 487 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0 0xEE3EE3EEUL 488 /* CFG_BIT_MAP_INDEX_CS11_0 [0:32] RW value= 0xee3ee3ee */ 489 #endif 490 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1) 491 /*IP Blk = MC_BASE1 Access=RW */ 492 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1 0x00003EE3UL 493 /* CFG_BIT_MAP_INDEX_CS11_1 [0:32] RW value= 0x00003ee3 */ 494 #endif 495 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0) 496 /*IP Blk = MC_BASE1 Access=RW */ 497 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0 0x07A07A07UL 498 /* CFG_BIT_MAP_INDEX_CS12_0 [0:32] RW value= 0x07a07a07 */ 499 #endif 500 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1) 501 /*IP Blk = MC_BASE1 Access=RW */ 502 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1 0x0000A07AUL 503 /* CFG_BIT_MAP_INDEX_CS12_1 [0:32] RW value= 0x0000a07a */ 504 #endif 505 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0) 506 /*IP Blk = MC_BASE1 Access=RW */ 507 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0 0x2F42F42FUL 508 /* CFG_BIT_MAP_INDEX_CS13_0 [0:32] RW value= 0x2f42f42f */ 509 #endif 510 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1) 511 /*IP Blk = MC_BASE1 Access=RW */ 512 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1 0x000042F4UL 513 /* CFG_BIT_MAP_INDEX_CS13_1 [0:32] RW value= 0x000042f4 */ 514 #endif 515 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0) 516 /*IP Blk = MC_BASE1 Access=RW */ 517 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0 0x48A48A48UL 518 /* CFG_BIT_MAP_INDEX_CS14_0 [0:32] RW value= 0x48a48a48 */ 519 #endif 520 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1) 521 /*IP Blk = MC_BASE1 Access=RW */ 522 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1 0x0000A48AUL 523 /* CFG_BIT_MAP_INDEX_CS14_1 [0:32] RW value= 0x0000a48a */ 524 #endif 525 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0) 526 /*IP Blk = MC_BASE1 Access=RW */ 527 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0 0x70470470UL 528 /* CFG_BIT_MAP_INDEX_CS15_0 [0:32] RW value= 0x70470470 */ 529 #endif 530 #if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1) 531 /*IP Blk = MC_BASE1 Access=RW */ 532 #define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1 0x00004704UL 533 /* CFG_BIT_MAP_INDEX_CS15_1 [0:32] RW value= 0x00004704 */ 534 #endif 535 #if !defined (LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS) 536 /*IP Blk = MC_BASE1 Access=RW */ 537 #define LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS 0x00000000UL 538 /* CFG_NUM_LOGICAL_RANKS_PER_3DS [0:32] RW value= 0x00000000 */ 539 #endif 540 #if !defined (LIBERO_SETTING_CFG_RFC_DLR1) 541 /*IP Blk = MC_BASE1 Access=RW */ 542 #define LIBERO_SETTING_CFG_RFC_DLR1 0x00000048UL 543 /* CFG_RFC_DLR1 [0:32] RW value= 0x00000048 */ 544 #endif 545 #if !defined (LIBERO_SETTING_CFG_RFC_DLR2) 546 /*IP Blk = MC_BASE1 Access=RW */ 547 #define LIBERO_SETTING_CFG_RFC_DLR2 0x0000002CUL 548 /* CFG_RFC_DLR2 [0:32] RW value= 0x0000002C */ 549 #endif 550 #if !defined (LIBERO_SETTING_CFG_RFC_DLR4) 551 /*IP Blk = MC_BASE1 Access=RW */ 552 #define LIBERO_SETTING_CFG_RFC_DLR4 0x00000020UL 553 /* CFG_RFC_DLR4 [0:32] RW value= 0x00000020 */ 554 #endif 555 #if !defined (LIBERO_SETTING_CFG_RRD_DLR) 556 /*IP Blk = MC_BASE1 Access=RW */ 557 #define LIBERO_SETTING_CFG_RRD_DLR 0x00000004UL 558 /* CFG_RRD_DLR [0:32] RW value= 0x00000004 */ 559 #endif 560 #if !defined (LIBERO_SETTING_CFG_FAW_DLR) 561 /*IP Blk = MC_BASE1 Access=RW */ 562 #define LIBERO_SETTING_CFG_FAW_DLR 0x00000010UL 563 /* CFG_FAW_DLR [0:32] RW value= 0x00000010 */ 564 #endif 565 #if !defined (LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY) 566 /*IP Blk = MC_BASE1 Access=RW */ 567 #define LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY 0x00000000UL 568 /* CFG_ADVANCE_ACTIVATE_READY [0:32] RW value= 0x00000000 */ 569 #endif 570 #if !defined (LIBERO_SETTING_CTRLR_SOFT_RESET_N) 571 /*IP Blk = MC_BASE2 Access=RW */ 572 #define LIBERO_SETTING_CTRLR_SOFT_RESET_N 0x00000001UL 573 /* CTRLR_SOFT_RESET_N [0:32] RW value= 0x1 */ 574 #endif 575 #if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_PCH) 576 /*IP Blk = MC_BASE2 Access=RW */ 577 #define LIBERO_SETTING_CFG_LOOKAHEAD_PCH 0x00000000UL 578 /* CFG_LOOKAHEAD_PCH [0:32] RW value= 0x0 */ 579 #endif 580 #if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_ACT) 581 /*IP Blk = MC_BASE2 Access=RW */ 582 #define LIBERO_SETTING_CFG_LOOKAHEAD_ACT 0x00000000UL 583 /* CFG_LOOKAHEAD_ACT [0:32] RW value= 0x0 */ 584 #endif 585 #if !defined (LIBERO_SETTING_INIT_AUTOINIT_DISABLE) 586 /*IP Blk = MC_BASE2 Access=RW */ 587 #define LIBERO_SETTING_INIT_AUTOINIT_DISABLE 0x00000000UL 588 /* INIT_AUTOINIT_DISABLE [0:32] RW value= 0x00000000 */ 589 #endif 590 #if !defined (LIBERO_SETTING_INIT_FORCE_RESET) 591 /*IP Blk = MC_BASE2 Access=RW */ 592 #define LIBERO_SETTING_INIT_FORCE_RESET 0x00000000UL 593 /* INIT_FORCE_RESET [0:32] RW value= 0x00000000 */ 594 #endif 595 #if !defined (LIBERO_SETTING_INIT_GEARDOWN_EN) 596 /*IP Blk = MC_BASE2 Access=RW */ 597 #define LIBERO_SETTING_INIT_GEARDOWN_EN 0x00000000UL 598 /* INIT_GEARDOWN_EN [0:32] RW value= 0x00000000 */ 599 #endif 600 #if !defined (LIBERO_SETTING_INIT_DISABLE_CKE) 601 /*IP Blk = MC_BASE2 Access=RW */ 602 #define LIBERO_SETTING_INIT_DISABLE_CKE 0x00000000UL 603 /* INIT_DISABLE_CKE [0:32] RW value= 0x00000000 */ 604 #endif 605 #if !defined (LIBERO_SETTING_INIT_CS) 606 /*IP Blk = MC_BASE2 Access=RW */ 607 #define LIBERO_SETTING_INIT_CS 0x00000000UL 608 /* INIT_CS [0:32] RW value= 0x00000000 */ 609 #endif 610 #if !defined (LIBERO_SETTING_INIT_PRECHARGE_ALL) 611 /*IP Blk = MC_BASE2 Access=RW */ 612 #define LIBERO_SETTING_INIT_PRECHARGE_ALL 0x00000000UL 613 /* INIT_PRECHARGE_ALL [0:32] RW value= 0x00000000 */ 614 #endif 615 #if !defined (LIBERO_SETTING_INIT_REFRESH) 616 /*IP Blk = MC_BASE2 Access=RW */ 617 #define LIBERO_SETTING_INIT_REFRESH 0x00000000UL 618 /* INIT_REFRESH [0:32] RW value= 0x00000000 */ 619 #endif 620 #if !defined (LIBERO_SETTING_INIT_ZQ_CAL_REQ) 621 /*IP Blk = MC_BASE2 Access=RW */ 622 #define LIBERO_SETTING_INIT_ZQ_CAL_REQ 0x00000000UL 623 /* INIT_ZQ_CAL_REQ [0:32] RW value= 0x00000000 */ 624 #endif 625 #if !defined (LIBERO_SETTING_CFG_BL) 626 /*IP Blk = MC_BASE2 Access=RW */ 627 #define LIBERO_SETTING_CFG_BL 0x00000000UL 628 /* CFG_BL [0:32] RW value= 0x0 */ 629 #endif 630 #if !defined (LIBERO_SETTING_CTRLR_INIT) 631 /*IP Blk = MC_BASE2 Access=RW */ 632 #define LIBERO_SETTING_CTRLR_INIT 0x00000000UL 633 /* CTRLR_INIT [0:32] RW value= 0x00000000 */ 634 #endif 635 #if !defined (LIBERO_SETTING_CFG_AUTO_REF_EN) 636 /*IP Blk = MC_BASE2 Access=RW */ 637 #define LIBERO_SETTING_CFG_AUTO_REF_EN 0x00000001UL 638 /* CFG_AUTO_REF_EN [0:32] RW value= 0x1 */ 639 #endif 640 #if !defined (LIBERO_SETTING_CFG_RAS) 641 /*IP Blk = MC_BASE2 Access=RW */ 642 #define LIBERO_SETTING_CFG_RAS 0x00000022UL 643 /* CFG_RAS [0:32] RW value= 0x22 */ 644 #endif 645 #if !defined (LIBERO_SETTING_CFG_RCD) 646 /*IP Blk = MC_BASE2 Access=RW */ 647 #define LIBERO_SETTING_CFG_RCD 0x0000000FUL 648 /* CFG_RCD [0:32] RW value= 0xF */ 649 #endif 650 #if !defined (LIBERO_SETTING_CFG_RRD) 651 /*IP Blk = MC_BASE2 Access=RW */ 652 #define LIBERO_SETTING_CFG_RRD 0x00000008UL 653 /* CFG_RRD [0:32] RW value= 0x8 */ 654 #endif 655 #if !defined (LIBERO_SETTING_CFG_RP) 656 /*IP Blk = MC_BASE2 Access=RW */ 657 #define LIBERO_SETTING_CFG_RP 0x00000011UL 658 /* CFG_RP [0:32] RW value= 0x11 */ 659 #endif 660 #if !defined (LIBERO_SETTING_CFG_RC) 661 /*IP Blk = MC_BASE2 Access=RW */ 662 #define LIBERO_SETTING_CFG_RC 0x00000033UL 663 /* CFG_RC [0:32] RW value= 0x33 */ 664 #endif 665 #if !defined (LIBERO_SETTING_CFG_FAW) 666 /*IP Blk = MC_BASE2 Access=RW */ 667 #define LIBERO_SETTING_CFG_FAW 0x00000020UL 668 /* CFG_FAW [0:32] RW value= 0x20 */ 669 #endif 670 #if !defined (LIBERO_SETTING_CFG_RFC) 671 /*IP Blk = MC_BASE2 Access=RW */ 672 #define LIBERO_SETTING_CFG_RFC 0x00000130UL 673 /* CFG_RFC [0:32] RW value= 0x130 */ 674 #endif 675 #if !defined (LIBERO_SETTING_CFG_RTP) 676 /*IP Blk = MC_BASE2 Access=RW */ 677 #define LIBERO_SETTING_CFG_RTP 0x00000008UL 678 /* CFG_RTP [0:32] RW value= 0x8 */ 679 #endif 680 #if !defined (LIBERO_SETTING_CFG_WR) 681 /*IP Blk = MC_BASE2 Access=RW */ 682 #define LIBERO_SETTING_CFG_WR 0x00000010UL 683 /* CFG_WR [0:32] RW value= 0x10 */ 684 #endif 685 #if !defined (LIBERO_SETTING_CFG_WTR) 686 /*IP Blk = MC_BASE2 Access=RW */ 687 #define LIBERO_SETTING_CFG_WTR 0x00000008UL 688 /* CFG_WTR [0:32] RW value= 0x8 */ 689 #endif 690 #if !defined (LIBERO_SETTING_CFG_PASR) 691 /*IP Blk = MC_BASE2 Access=RW */ 692 #define LIBERO_SETTING_CFG_PASR 0x00000000UL 693 /* CFG_PASR [0:32] RW value= 0x0 */ 694 #endif 695 #if !defined (LIBERO_SETTING_CFG_XP) 696 /*IP Blk = MC_BASE2 Access=RW */ 697 #define LIBERO_SETTING_CFG_XP 0x00000006UL 698 /* CFG_XP [0:32] RW value= 0x6 */ 699 #endif 700 #if !defined (LIBERO_SETTING_CFG_XSR) 701 /*IP Blk = MC_BASE2 Access=RW */ 702 #define LIBERO_SETTING_CFG_XSR 0x0000001FUL 703 /* CFG_XSR [0:32] RW value= 0x1F */ 704 #endif 705 #if !defined (LIBERO_SETTING_CFG_CL) 706 /*IP Blk = MC_BASE2 Access=RW */ 707 #define LIBERO_SETTING_CFG_CL 0x00000005UL 708 /* CFG_CL [0:32] RW value= 0x5 */ 709 #endif 710 #if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE) 711 /*IP Blk = MC_BASE2 Access=RW */ 712 #define LIBERO_SETTING_CFG_READ_TO_WRITE 0x0000000FUL 713 /* CFG_READ_TO_WRITE [0:32] RW value= 0xF */ 714 #endif 715 #if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE) 716 /*IP Blk = MC_BASE2 Access=RW */ 717 #define LIBERO_SETTING_CFG_WRITE_TO_WRITE 0x0000000FUL 718 /* CFG_WRITE_TO_WRITE [0:32] RW value= 0xF */ 719 #endif 720 #if !defined (LIBERO_SETTING_CFG_READ_TO_READ) 721 /*IP Blk = MC_BASE2 Access=RW */ 722 #define LIBERO_SETTING_CFG_READ_TO_READ 0x0000000FUL 723 /* CFG_READ_TO_READ [0:32] RW value= 0xF */ 724 #endif 725 #if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ) 726 /*IP Blk = MC_BASE2 Access=RW */ 727 #define LIBERO_SETTING_CFG_WRITE_TO_READ 0x0000001FUL 728 /* CFG_WRITE_TO_READ [0:32] RW value= 0x1F */ 729 #endif 730 #if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE_ODT) 731 /*IP Blk = MC_BASE2 Access=RW */ 732 #define LIBERO_SETTING_CFG_READ_TO_WRITE_ODT 0x00000001UL 733 /* CFG_READ_TO_WRITE_ODT [0:32] RW value= 0x1 */ 734 #endif 735 #if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT) 736 /*IP Blk = MC_BASE2 Access=RW */ 737 #define LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT 0x00000000UL 738 /* CFG_WRITE_TO_WRITE_ODT [0:32] RW value= 0x0 */ 739 #endif 740 #if !defined (LIBERO_SETTING_CFG_READ_TO_READ_ODT) 741 /*IP Blk = MC_BASE2 Access=RW */ 742 #define LIBERO_SETTING_CFG_READ_TO_READ_ODT 0x00000001UL 743 /* CFG_READ_TO_READ_ODT [0:32] RW value= 0x1 */ 744 #endif 745 #if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ_ODT) 746 /*IP Blk = MC_BASE2 Access=RW */ 747 #define LIBERO_SETTING_CFG_WRITE_TO_READ_ODT 0x00000001UL 748 /* CFG_WRITE_TO_READ_ODT [0:32] RW value= 0x1 */ 749 #endif 750 #if !defined (LIBERO_SETTING_CFG_MIN_READ_IDLE) 751 /*IP Blk = MC_BASE2 Access=RW */ 752 #define LIBERO_SETTING_CFG_MIN_READ_IDLE 0x00000007UL 753 /* CFG_MIN_READ_IDLE [0:32] RW value= 0x7 */ 754 #endif 755 #if !defined (LIBERO_SETTING_CFG_MRD) 756 /*IP Blk = MC_BASE2 Access=RW */ 757 #define LIBERO_SETTING_CFG_MRD 0x0000000CUL 758 /* CFG_MRD [0:32] RW value= 0xC */ 759 #endif 760 #if !defined (LIBERO_SETTING_CFG_BT) 761 /*IP Blk = MC_BASE2 Access=RW */ 762 #define LIBERO_SETTING_CFG_BT 0x00000000UL 763 /* CFG_BT [0:32] RW value= 0x0 */ 764 #endif 765 #if !defined (LIBERO_SETTING_CFG_DS) 766 /*IP Blk = MC_BASE2 Access=RW */ 767 #define LIBERO_SETTING_CFG_DS 0x00000006UL 768 /* CFG_DS [0:32] RW value= 0x6 */ 769 #endif 770 #if !defined (LIBERO_SETTING_CFG_QOFF) 771 /*IP Blk = MC_BASE2 Access=RW */ 772 #define LIBERO_SETTING_CFG_QOFF 0x00000000UL 773 /* CFG_QOFF [0:32] RW value= 0x0 */ 774 #endif 775 #if !defined (LIBERO_SETTING_CFG_RTT) 776 /*IP Blk = MC_BASE2 Access=RW */ 777 #define LIBERO_SETTING_CFG_RTT 0x00000002UL 778 /* CFG_RTT [0:32] RW value= 0x2 */ 779 #endif 780 #if !defined (LIBERO_SETTING_CFG_DLL_DISABLE) 781 /*IP Blk = MC_BASE2 Access=RW */ 782 #define LIBERO_SETTING_CFG_DLL_DISABLE 0x00000000UL 783 /* CFG_DLL_DISABLE [0:32] RW value= 0x0 */ 784 #endif 785 #if !defined (LIBERO_SETTING_CFG_REF_PER) 786 /*IP Blk = MC_BASE2 Access=RW */ 787 #define LIBERO_SETTING_CFG_REF_PER 0x00000C34UL 788 /* CFG_REF_PER [0:32] RW value= 0xC34 */ 789 #endif 790 #if !defined (LIBERO_SETTING_CFG_STARTUP_DELAY) 791 /*IP Blk = MC_BASE2 Access=RW */ 792 #define LIBERO_SETTING_CFG_STARTUP_DELAY 0x00027100UL 793 /* CFG_STARTUP_DELAY [0:32] RW value= 0x27100 */ 794 #endif 795 #if !defined (LIBERO_SETTING_CFG_MEM_COLBITS) 796 /*IP Blk = MC_BASE2 Access=RW */ 797 #define LIBERO_SETTING_CFG_MEM_COLBITS 0x0000000AUL 798 /* CFG_MEM_COLBITS [0:32] RW value= 0xA */ 799 #endif 800 #if !defined (LIBERO_SETTING_CFG_MEM_ROWBITS) 801 /*IP Blk = MC_BASE2 Access=RW */ 802 #define LIBERO_SETTING_CFG_MEM_ROWBITS 0x00000010UL 803 /* CFG_MEM_ROWBITS [0:32] RW value= 0x10 */ 804 #endif 805 #if !defined (LIBERO_SETTING_CFG_MEM_BANKBITS) 806 /*IP Blk = MC_BASE2 Access=RW */ 807 #define LIBERO_SETTING_CFG_MEM_BANKBITS 0x00000003UL 808 /* CFG_MEM_BANKBITS [0:32] RW value= 0x3 */ 809 #endif 810 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS0) 811 /*IP Blk = MC_BASE2 Access=RW */ 812 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS0 0x00000000UL 813 /* CFG_ODT_RD_MAP_CS0 [0:32] RW value= 0x0 */ 814 #endif 815 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS1) 816 /*IP Blk = MC_BASE2 Access=RW */ 817 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS1 0x00000000UL 818 /* CFG_ODT_RD_MAP_CS1 [0:32] RW value= 0x0 */ 819 #endif 820 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS2) 821 /*IP Blk = MC_BASE2 Access=RW */ 822 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS2 0x00000000UL 823 /* CFG_ODT_RD_MAP_CS2 [0:32] RW value= 0x0 */ 824 #endif 825 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS3) 826 /*IP Blk = MC_BASE2 Access=RW */ 827 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS3 0x00000000UL 828 /* CFG_ODT_RD_MAP_CS3 [0:32] RW value= 0x0 */ 829 #endif 830 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS4) 831 /*IP Blk = MC_BASE2 Access=RW */ 832 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS4 0x00000000UL 833 /* CFG_ODT_RD_MAP_CS4 [0:32] RW value= 0x0 */ 834 #endif 835 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS5) 836 /*IP Blk = MC_BASE2 Access=RW */ 837 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS5 0x00000000UL 838 /* CFG_ODT_RD_MAP_CS5 [0:32] RW value= 0x0 */ 839 #endif 840 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS6) 841 /*IP Blk = MC_BASE2 Access=RW */ 842 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS6 0x00000000UL 843 /* CFG_ODT_RD_MAP_CS6 [0:32] RW value= 0x0 */ 844 #endif 845 #if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS7) 846 /*IP Blk = MC_BASE2 Access=RW */ 847 #define LIBERO_SETTING_CFG_ODT_RD_MAP_CS7 0x00000000UL 848 /* CFG_ODT_RD_MAP_CS7 [0:32] RW value= 0x0 */ 849 #endif 850 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS0) 851 /*IP Blk = MC_BASE2 Access=RW */ 852 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS0 0x00000000UL 853 /* CFG_ODT_WR_MAP_CS0 [0:32] RW value= 0x0 */ 854 #endif 855 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS1) 856 /*IP Blk = MC_BASE2 Access=RW */ 857 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS1 0x00000000UL 858 /* CFG_ODT_WR_MAP_CS1 [0:32] RW value= 0x0 */ 859 #endif 860 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS2) 861 /*IP Blk = MC_BASE2 Access=RW */ 862 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS2 0x00000000UL 863 /* CFG_ODT_WR_MAP_CS2 [0:32] RW value= 0x0 */ 864 #endif 865 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS3) 866 /*IP Blk = MC_BASE2 Access=RW */ 867 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS3 0x00000000UL 868 /* CFG_ODT_WR_MAP_CS3 [0:32] RW value= 0x0 */ 869 #endif 870 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS4) 871 /*IP Blk = MC_BASE2 Access=RW */ 872 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS4 0x00000000UL 873 /* CFG_ODT_WR_MAP_CS4 [0:32] RW value= 0x0 */ 874 #endif 875 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS5) 876 /*IP Blk = MC_BASE2 Access=RW */ 877 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS5 0x00000000UL 878 /* CFG_ODT_WR_MAP_CS5 [0:32] RW value= 0x0 */ 879 #endif 880 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS6) 881 /*IP Blk = MC_BASE2 Access=RW */ 882 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS6 0x00000000UL 883 /* CFG_ODT_WR_MAP_CS6 [0:32] RW value= 0x0 */ 884 #endif 885 #if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS7) 886 /*IP Blk = MC_BASE2 Access=RW */ 887 #define LIBERO_SETTING_CFG_ODT_WR_MAP_CS7 0x00000000UL 888 /* CFG_ODT_WR_MAP_CS7 [0:32] RW value= 0x0 */ 889 #endif 890 #if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_ON) 891 /*IP Blk = MC_BASE2 Access=RW */ 892 #define LIBERO_SETTING_CFG_ODT_RD_TURN_ON 0x00000000UL 893 /* CFG_ODT_RD_TURN_ON [0:32] RW value= 0x0 */ 894 #endif 895 #if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_ON) 896 /*IP Blk = MC_BASE2 Access=RW */ 897 #define LIBERO_SETTING_CFG_ODT_WR_TURN_ON 0x00000000UL 898 /* CFG_ODT_WR_TURN_ON [0:32] RW value= 0x0 */ 899 #endif 900 #if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_OFF) 901 /*IP Blk = MC_BASE2 Access=RW */ 902 #define LIBERO_SETTING_CFG_ODT_RD_TURN_OFF 0x00000000UL 903 /* CFG_ODT_RD_TURN_OFF [0:32] RW value= 0x0 */ 904 #endif 905 #if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_OFF) 906 /*IP Blk = MC_BASE2 Access=RW */ 907 #define LIBERO_SETTING_CFG_ODT_WR_TURN_OFF 0x00000000UL 908 /* CFG_ODT_WR_TURN_OFF [0:32] RW value= 0x0 */ 909 #endif 910 #if !defined (LIBERO_SETTING_CFG_EMR3) 911 /*IP Blk = MC_BASE2 Access=RW */ 912 #define LIBERO_SETTING_CFG_EMR3 0x00000000UL 913 /* CFG_EMR3 [0:32] RW value= 0x0 */ 914 #endif 915 #if !defined (LIBERO_SETTING_CFG_TWO_T) 916 /*IP Blk = MC_BASE2 Access=RW */ 917 #define LIBERO_SETTING_CFG_TWO_T 0x00000000UL 918 /* CFG_TWO_T [0:32] RW value= 0x0 */ 919 #endif 920 #if !defined (LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE) 921 /*IP Blk = MC_BASE2 Access=RW */ 922 #define LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE 0x00000001UL 923 /* CFG_TWO_T_SEL_CYCLE [0:32] RW value= 0x1 */ 924 #endif 925 #if !defined (LIBERO_SETTING_CFG_REGDIMM) 926 /*IP Blk = MC_BASE2 Access=RW */ 927 #define LIBERO_SETTING_CFG_REGDIMM 0x00000000UL 928 /* CFG_REGDIMM [0:32] RW value= 0x0 */ 929 #endif 930 #if !defined (LIBERO_SETTING_CFG_MOD) 931 /*IP Blk = MC_BASE2 Access=RW */ 932 #define LIBERO_SETTING_CFG_MOD 0x0000000CUL 933 /* CFG_MOD [0:32] RW value= 0xC */ 934 #endif 935 #if !defined (LIBERO_SETTING_CFG_XS) 936 /*IP Blk = MC_BASE2 Access=RW */ 937 #define LIBERO_SETTING_CFG_XS 0x00000005UL 938 /* CFG_XS [0:32] RW value= 0x5 */ 939 #endif 940 #if !defined (LIBERO_SETTING_CFG_XSDLL) 941 /*IP Blk = MC_BASE2 Access=RW */ 942 #define LIBERO_SETTING_CFG_XSDLL 0x00000200UL 943 /* CFG_XSDLL [0:32] RW value= 0x00000200 */ 944 #endif 945 #if !defined (LIBERO_SETTING_CFG_XPR) 946 /*IP Blk = MC_BASE2 Access=RW */ 947 #define LIBERO_SETTING_CFG_XPR 0x00000005UL 948 /* CFG_XPR [0:32] RW value= 0x5 */ 949 #endif 950 #if !defined (LIBERO_SETTING_CFG_AL_MODE) 951 /*IP Blk = MC_BASE2 Access=RW */ 952 #define LIBERO_SETTING_CFG_AL_MODE 0x00000000UL 953 /* CFG_AL_MODE [0:32] RW value= 0x0 */ 954 #endif 955 #if !defined (LIBERO_SETTING_CFG_CWL) 956 /*IP Blk = MC_BASE2 Access=RW */ 957 #define LIBERO_SETTING_CFG_CWL 0x00000005UL 958 /* CFG_CWL [0:32] RW value= 0x5 */ 959 #endif 960 #if !defined (LIBERO_SETTING_CFG_BL_MODE) 961 /*IP Blk = MC_BASE2 Access=RW */ 962 #define LIBERO_SETTING_CFG_BL_MODE 0x00000000UL 963 /* CFG_BL_MODE [0:32] RW value= 0x0 */ 964 #endif 965 #if !defined (LIBERO_SETTING_CFG_TDQS) 966 /*IP Blk = MC_BASE2 Access=RW */ 967 #define LIBERO_SETTING_CFG_TDQS 0x00000000UL 968 /* CFG_TDQS [0:32] RW value= 0x0 */ 969 #endif 970 #if !defined (LIBERO_SETTING_CFG_RTT_WR) 971 /*IP Blk = MC_BASE2 Access=RW */ 972 #define LIBERO_SETTING_CFG_RTT_WR 0x00000000UL 973 /* CFG_RTT_WR [0:32] RW value= 0x0 */ 974 #endif 975 #if !defined (LIBERO_SETTING_CFG_LP_ASR) 976 /*IP Blk = MC_BASE2 Access=RW */ 977 #define LIBERO_SETTING_CFG_LP_ASR 0x00000000UL 978 /* CFG_LP_ASR [0:32] RW value= 0x00000000 */ 979 #endif 980 #if !defined (LIBERO_SETTING_CFG_AUTO_SR) 981 /*IP Blk = MC_BASE2 Access=RW */ 982 #define LIBERO_SETTING_CFG_AUTO_SR 0x00000000UL 983 /* CFG_AUTO_SR [0:32] RW value= 0x0 */ 984 #endif 985 #if !defined (LIBERO_SETTING_CFG_SRT) 986 /*IP Blk = MC_BASE2 Access=RW */ 987 #define LIBERO_SETTING_CFG_SRT 0x00000000UL 988 /* CFG_SRT [0:32] RW value= 0x0 */ 989 #endif 990 #if !defined (LIBERO_SETTING_CFG_ADDR_MIRROR) 991 /*IP Blk = MC_BASE2 Access=RW */ 992 #define LIBERO_SETTING_CFG_ADDR_MIRROR 0x00000000UL 993 /* CFG_ADDR_MIRROR [0:32] RW value= 0x0 */ 994 #endif 995 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_TYPE) 996 /*IP Blk = MC_BASE2 Access=RW */ 997 #define LIBERO_SETTING_CFG_ZQ_CAL_TYPE 0x00000001UL 998 /* CFG_ZQ_CAL_TYPE [0:32] RW value= 0x1 */ 999 #endif 1000 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_PER) 1001 /*IP Blk = MC_BASE2 Access=RW */ 1002 #define LIBERO_SETTING_CFG_ZQ_CAL_PER 0x00027100UL 1003 /* CFG_ZQ_CAL_PER [0:32] RW value= 0x27100 */ 1004 #endif 1005 #if !defined (LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN) 1006 /*IP Blk = MC_BASE2 Access=RW */ 1007 #define LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN 0x00000000UL 1008 /* CFG_AUTO_ZQ_CAL_EN [0:32] RW value= 0x0 */ 1009 #endif 1010 #if !defined (LIBERO_SETTING_CFG_MEMORY_TYPE) 1011 /*IP Blk = MC_BASE2 Access=RW */ 1012 #define LIBERO_SETTING_CFG_MEMORY_TYPE 0x00000400UL 1013 /* CFG_MEMORY_TYPE [0:32] RW value= 0x400 */ 1014 #endif 1015 #if !defined (LIBERO_SETTING_CFG_ONLY_SRANK_CMDS) 1016 /*IP Blk = MC_BASE2 Access=RW */ 1017 #define LIBERO_SETTING_CFG_ONLY_SRANK_CMDS 0x00000000UL 1018 /* CFG_ONLY_SRANK_CMDS [0:32] RW value= 0x0 */ 1019 #endif 1020 #if !defined (LIBERO_SETTING_CFG_NUM_RANKS) 1021 /*IP Blk = MC_BASE2 Access=RW */ 1022 #define LIBERO_SETTING_CFG_NUM_RANKS 0x00000001UL 1023 /* CFG_NUM_RANKS [0:32] RW value= 0x1 */ 1024 #endif 1025 #if !defined (LIBERO_SETTING_CFG_QUAD_RANK) 1026 /*IP Blk = MC_BASE2 Access=RW */ 1027 #define LIBERO_SETTING_CFG_QUAD_RANK 0x00000000UL 1028 /* CFG_QUAD_RANK [0:32] RW value= 0x0 */ 1029 #endif 1030 #if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START) 1031 /*IP Blk = MC_BASE2 Access=RW */ 1032 #define LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START 0x00000000UL 1033 /* CFG_EARLY_RANK_TO_WR_START [0:32] RW value= 0x0 */ 1034 #endif 1035 #if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START) 1036 /*IP Blk = MC_BASE2 Access=RW */ 1037 #define LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START 0x00000000UL 1038 /* CFG_EARLY_RANK_TO_RD_START [0:32] RW value= 0x0 */ 1039 #endif 1040 #if !defined (LIBERO_SETTING_CFG_PASR_BANK) 1041 /*IP Blk = MC_BASE2 Access=RW */ 1042 #define LIBERO_SETTING_CFG_PASR_BANK 0x00000000UL 1043 /* CFG_PASR_BANK [0:32] RW value= 0x00000000 */ 1044 #endif 1045 #if !defined (LIBERO_SETTING_CFG_PASR_SEG) 1046 /*IP Blk = MC_BASE2 Access=RW */ 1047 #define LIBERO_SETTING_CFG_PASR_SEG 0x00000000UL 1048 /* CFG_PASR_SEG [0:32] RW value= 0x00000000 */ 1049 #endif 1050 #if !defined (LIBERO_SETTING_INIT_MRR_MODE) 1051 /*IP Blk = MC_BASE2 Access=RW */ 1052 #define LIBERO_SETTING_INIT_MRR_MODE 0x00000000UL 1053 /* INIT_MRR_MODE [0:32] RW value= 0x00000000 */ 1054 #endif 1055 #if !defined (LIBERO_SETTING_INIT_MR_W_REQ) 1056 /*IP Blk = MC_BASE2 Access=RW */ 1057 #define LIBERO_SETTING_INIT_MR_W_REQ 0x00000000UL 1058 /* INIT_MR_W_REQ [0:32] RW value= 0x00000000 */ 1059 #endif 1060 #if !defined (LIBERO_SETTING_INIT_MR_ADDR) 1061 /*IP Blk = MC_BASE2 Access=RW */ 1062 #define LIBERO_SETTING_INIT_MR_ADDR 0x00000000UL 1063 /* INIT_MR_ADDR [0:32] RW value= 0x00000000 */ 1064 #endif 1065 #if !defined (LIBERO_SETTING_INIT_MR_WR_DATA) 1066 /*IP Blk = MC_BASE2 Access=RW */ 1067 #define LIBERO_SETTING_INIT_MR_WR_DATA 0x00000000UL 1068 /* INIT_MR_WR_DATA [0:32] RW value= 0x00000000 */ 1069 #endif 1070 #if !defined (LIBERO_SETTING_INIT_MR_WR_MASK) 1071 /*IP Blk = MC_BASE2 Access=RW */ 1072 #define LIBERO_SETTING_INIT_MR_WR_MASK 0x00000000UL 1073 /* INIT_MR_WR_MASK [0:32] RW value= 0x00000000 */ 1074 #endif 1075 #if !defined (LIBERO_SETTING_INIT_NOP) 1076 /*IP Blk = MC_BASE2 Access=RW */ 1077 #define LIBERO_SETTING_INIT_NOP 0x00000000UL 1078 /* INIT_NOP [0:32] RW value= 0x00000000 */ 1079 #endif 1080 #if !defined (LIBERO_SETTING_CFG_INIT_DURATION) 1081 /*IP Blk = MC_BASE2 Access=RW */ 1082 #define LIBERO_SETTING_CFG_INIT_DURATION 0x00000640UL 1083 /* CFG_INIT_DURATION [0:32] RW value= 0x640 */ 1084 #endif 1085 #if !defined (LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION) 1086 /*IP Blk = MC_BASE2 Access=RW */ 1087 #define LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION 0x00000000UL 1088 /* CFG_ZQINIT_CAL_DURATION [0:32] RW value= 0x0 */ 1089 #endif 1090 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION) 1091 /*IP Blk = MC_BASE2 Access=RW */ 1092 #define LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION 0x00000000UL 1093 /* CFG_ZQ_CAL_L_DURATION [0:32] RW value= 0x0 */ 1094 #endif 1095 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION) 1096 /*IP Blk = MC_BASE2 Access=RW */ 1097 #define LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION 0x00000000UL 1098 /* CFG_ZQ_CAL_S_DURATION [0:32] RW value= 0x0 */ 1099 #endif 1100 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION) 1101 /*IP Blk = MC_BASE2 Access=RW */ 1102 #define LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION 0x00000028UL 1103 /* CFG_ZQ_CAL_R_DURATION [0:32] RW value= 0x28 */ 1104 #endif 1105 #if !defined (LIBERO_SETTING_CFG_MRR) 1106 /*IP Blk = MC_BASE2 Access=RW */ 1107 #define LIBERO_SETTING_CFG_MRR 0x00000008UL 1108 /* CFG_MRR [0:32] RW value= 0x8 */ 1109 #endif 1110 #if !defined (LIBERO_SETTING_CFG_MRW) 1111 /*IP Blk = MC_BASE2 Access=RW */ 1112 #define LIBERO_SETTING_CFG_MRW 0x0000000AUL 1113 /* CFG_MRW [0:32] RW value= 0xA */ 1114 #endif 1115 #if !defined (LIBERO_SETTING_CFG_ODT_POWERDOWN) 1116 /*IP Blk = MC_BASE2 Access=RW */ 1117 #define LIBERO_SETTING_CFG_ODT_POWERDOWN 0x00000000UL 1118 /* CFG_ODT_POWERDOWN [0:32] RW value= 0x00000000 */ 1119 #endif 1120 #if !defined (LIBERO_SETTING_CFG_WL) 1121 /*IP Blk = MC_BASE2 Access=RW */ 1122 #define LIBERO_SETTING_CFG_WL 0x00000008UL 1123 /* CFG_WL [0:32] RW value= 0x8 */ 1124 #endif 1125 #if !defined (LIBERO_SETTING_CFG_RL) 1126 /*IP Blk = MC_BASE2 Access=RW */ 1127 #define LIBERO_SETTING_CFG_RL 0x0000000EUL 1128 /* CFG_RL [0:32] RW value= 0xE */ 1129 #endif 1130 #if !defined (LIBERO_SETTING_CFG_CAL_READ_PERIOD) 1131 /*IP Blk = MC_BASE2 Access=RW */ 1132 #define LIBERO_SETTING_CFG_CAL_READ_PERIOD 0x00000000UL 1133 /* CFG_CAL_READ_PERIOD [0:32] RW value= 0x0 */ 1134 #endif 1135 #if !defined (LIBERO_SETTING_CFG_NUM_CAL_READS) 1136 /*IP Blk = MC_BASE2 Access=RW */ 1137 #define LIBERO_SETTING_CFG_NUM_CAL_READS 0x00000001UL 1138 /* CFG_NUM_CAL_READS [0:32] RW value= 0x1 */ 1139 #endif 1140 #if !defined (LIBERO_SETTING_INIT_SELF_REFRESH) 1141 /*IP Blk = MC_BASE2 Access=RW */ 1142 #define LIBERO_SETTING_INIT_SELF_REFRESH 0x00000000UL 1143 /* INIT_SELF_REFRESH [0:32] RW value= 0x00000000 */ 1144 #endif 1145 #if !defined (LIBERO_SETTING_INIT_POWER_DOWN) 1146 /*IP Blk = MC_BASE2 Access=RW */ 1147 #define LIBERO_SETTING_INIT_POWER_DOWN 0x00000000UL 1148 /* INIT_POWER_DOWN [0:32] RW value= 0x00000000 */ 1149 #endif 1150 #if !defined (LIBERO_SETTING_INIT_FORCE_WRITE) 1151 /*IP Blk = MC_BASE2 Access=RW */ 1152 #define LIBERO_SETTING_INIT_FORCE_WRITE 0x00000000UL 1153 /* INIT_FORCE_WRITE [0:32] RW value= 0x00000000 */ 1154 #endif 1155 #if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_CS) 1156 /*IP Blk = MC_BASE2 Access=RW */ 1157 #define LIBERO_SETTING_INIT_FORCE_WRITE_CS 0x00000000UL 1158 /* INIT_FORCE_WRITE_CS [0:32] RW value= 0x00000000 */ 1159 #endif 1160 #if !defined (LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE) 1161 /*IP Blk = MC_BASE2 Access=RW */ 1162 #define LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE 0x00000000UL 1163 /* CFG_CTRLR_INIT_DISABLE [0:32] RW value= 0x0 */ 1164 #endif 1165 #if !defined (LIBERO_SETTING_INIT_RDIMM_COMPLETE) 1166 /*IP Blk = MC_BASE2 Access=RW */ 1167 #define LIBERO_SETTING_INIT_RDIMM_COMPLETE 0x00000000UL 1168 /* INIT_RDIMM_COMPLETE [0:32] RW value= 0x00000000 */ 1169 #endif 1170 #if !defined (LIBERO_SETTING_CFG_RDIMM_LAT) 1171 /*IP Blk = MC_BASE2 Access=RW */ 1172 #define LIBERO_SETTING_CFG_RDIMM_LAT 0x00000000UL 1173 /* CFG_RDIMM_LAT [0:32] RW value= 0x0 */ 1174 #endif 1175 #if !defined (LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT) 1176 /*IP Blk = MC_BASE2 Access=RW */ 1177 #define LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT 0x00000001UL 1178 /* CFG_RDIMM_BSIDE_INVERT [0:32] RW value= 0x00000001 */ 1179 #endif 1180 #if !defined (LIBERO_SETTING_CFG_LRDIMM) 1181 /*IP Blk = MC_BASE2 Access=RW */ 1182 #define LIBERO_SETTING_CFG_LRDIMM 0x00000000UL 1183 /* CFG_LRDIMM [0:32] RW value= 0x00000000 */ 1184 #endif 1185 #if !defined (LIBERO_SETTING_INIT_MEMORY_RESET_MASK) 1186 /*IP Blk = MC_BASE2 Access=RW */ 1187 #define LIBERO_SETTING_INIT_MEMORY_RESET_MASK 0x00000000UL 1188 /* INIT_MEMORY_RESET_MASK [0:32] RW value= 0x00000000 */ 1189 #endif 1190 #if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE) 1191 /*IP Blk = MC_BASE2 Access=RW */ 1192 #define LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE 0x00000000UL 1193 /* CFG_RD_PREAMB_TOGGLE [0:32] RW value= 0x0 */ 1194 #endif 1195 #if !defined (LIBERO_SETTING_CFG_RD_POSTAMBLE) 1196 /*IP Blk = MC_BASE2 Access=RW */ 1197 #define LIBERO_SETTING_CFG_RD_POSTAMBLE 0x00000000UL 1198 /* CFG_RD_POSTAMBLE [0:32] RW value= 0x0 */ 1199 #endif 1200 #if !defined (LIBERO_SETTING_CFG_PU_CAL) 1201 /*IP Blk = MC_BASE2 Access=RW */ 1202 #define LIBERO_SETTING_CFG_PU_CAL 0x00000001UL 1203 /* CFG_PU_CAL [0:32] RW value= 0x1 */ 1204 #endif 1205 #if !defined (LIBERO_SETTING_CFG_DQ_ODT) 1206 /*IP Blk = MC_BASE2 Access=RW */ 1207 #define LIBERO_SETTING_CFG_DQ_ODT 0x00000002UL 1208 /* CFG_DQ_ODT [0:32] RW value= 0x2 */ 1209 #endif 1210 #if !defined (LIBERO_SETTING_CFG_CA_ODT) 1211 /*IP Blk = MC_BASE2 Access=RW */ 1212 #define LIBERO_SETTING_CFG_CA_ODT 0x00000004UL 1213 /* CFG_CA_ODT [0:32] RW value= 0x4 */ 1214 #endif 1215 #if !defined (LIBERO_SETTING_CFG_ZQLATCH_DURATION) 1216 /*IP Blk = MC_BASE2 Access=RW */ 1217 #define LIBERO_SETTING_CFG_ZQLATCH_DURATION 0x00000018UL 1218 /* CFG_ZQLATCH_DURATION [0:32] RW value= 0x18 */ 1219 #endif 1220 #if !defined (LIBERO_SETTING_INIT_CAL_SELECT) 1221 /*IP Blk = MC_BASE2 Access=RW */ 1222 #define LIBERO_SETTING_INIT_CAL_SELECT 0x00000000UL 1223 /* INIT_CAL_SELECT [0:32] RW value= 0x00000000 */ 1224 #endif 1225 #if !defined (LIBERO_SETTING_INIT_CAL_L_R_REQ) 1226 /*IP Blk = MC_BASE2 Access=RW */ 1227 #define LIBERO_SETTING_INIT_CAL_L_R_REQ 0x00000000UL 1228 /* INIT_CAL_L_R_REQ [0:32] RW value= 0x00000000 */ 1229 #endif 1230 #if !defined (LIBERO_SETTING_INIT_CAL_L_B_SIZE) 1231 /*IP Blk = MC_BASE2 Access=RW */ 1232 #define LIBERO_SETTING_INIT_CAL_L_B_SIZE 0x00000000UL 1233 /* INIT_CAL_L_B_SIZE [0:32] RW value= 0x00000000 */ 1234 #endif 1235 #if !defined (LIBERO_SETTING_INIT_RWFIFO) 1236 /*IP Blk = MC_BASE2 Access=RW */ 1237 #define LIBERO_SETTING_INIT_RWFIFO 0x00000000UL 1238 /* INIT_RWFIFO [0:32] RW value= 0x00000000 */ 1239 #endif 1240 #if !defined (LIBERO_SETTING_INIT_RD_DQCAL) 1241 /*IP Blk = MC_BASE2 Access=RW */ 1242 #define LIBERO_SETTING_INIT_RD_DQCAL 0x00000000UL 1243 /* INIT_RD_DQCAL [0:32] RW value= 0x00000000 */ 1244 #endif 1245 #if !defined (LIBERO_SETTING_INIT_START_DQSOSC) 1246 /*IP Blk = MC_BASE2 Access=RW */ 1247 #define LIBERO_SETTING_INIT_START_DQSOSC 0x00000000UL 1248 /* INIT_START_DQSOSC [0:32] RW value= 0x00000000 */ 1249 #endif 1250 #if !defined (LIBERO_SETTING_INIT_STOP_DQSOSC) 1251 /*IP Blk = MC_BASE2 Access=RW */ 1252 #define LIBERO_SETTING_INIT_STOP_DQSOSC 0x00000000UL 1253 /* INIT_STOP_DQSOSC [0:32] RW value= 0x00000000 */ 1254 #endif 1255 #if !defined (LIBERO_SETTING_INIT_ZQ_CAL_START) 1256 /*IP Blk = MC_BASE2 Access=RW */ 1257 #define LIBERO_SETTING_INIT_ZQ_CAL_START 0x00000000UL 1258 /* INIT_ZQ_CAL_START [0:32] RW value= 0x00000000 */ 1259 #endif 1260 #if !defined (LIBERO_SETTING_CFG_WR_POSTAMBLE) 1261 /*IP Blk = MC_BASE2 Access=RW */ 1262 #define LIBERO_SETTING_CFG_WR_POSTAMBLE 0x00000000UL 1263 /* CFG_WR_POSTAMBLE [0:32] RW value= 0x0 */ 1264 #endif 1265 #if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_0) 1266 /*IP Blk = MC_BASE2 Access=RW */ 1267 #define LIBERO_SETTING_INIT_CAL_L_ADDR_0 0x00000000UL 1268 /* INIT_CAL_L_ADDR_0 [0:32] RW value= 0x00000000 */ 1269 #endif 1270 #if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_1) 1271 /*IP Blk = MC_BASE2 Access=RW */ 1272 #define LIBERO_SETTING_INIT_CAL_L_ADDR_1 0x00000000UL 1273 /* INIT_CAL_L_ADDR_1 [0:32] RW value= 0x00000000 */ 1274 #endif 1275 #if !defined (LIBERO_SETTING_CFG_CTRLUPD_TRIG) 1276 /*IP Blk = MC_BASE2 Access=RW */ 1277 #define LIBERO_SETTING_CFG_CTRLUPD_TRIG 0x00000000UL 1278 /* CFG_CTRLUPD_TRIG [0:32] RW value= 0x0 */ 1279 #endif 1280 #if !defined (LIBERO_SETTING_CFG_CTRLUPD_START_DELAY) 1281 /*IP Blk = MC_BASE2 Access=RW */ 1282 #define LIBERO_SETTING_CFG_CTRLUPD_START_DELAY 0x00000000UL 1283 /* CFG_CTRLUPD_START_DELAY [0:32] RW value= 0x0 */ 1284 #endif 1285 #if !defined (LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX) 1286 /*IP Blk = MC_BASE2 Access=RW */ 1287 #define LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX 0x00000000UL 1288 /* CFG_DFI_T_CTRLUPD_MAX [0:32] RW value= 0x0 */ 1289 #endif 1290 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SEL) 1291 /*IP Blk = MC_BASE2 Access=RW */ 1292 #define LIBERO_SETTING_CFG_CTRLR_BUSY_SEL 0x00000000UL 1293 /* CFG_CTRLR_BUSY_SEL [0:32] RW value= 0x00000000 */ 1294 #endif 1295 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE) 1296 /*IP Blk = MC_BASE2 Access=RW */ 1297 #define LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE 0x00000000UL 1298 /* CFG_CTRLR_BUSY_VALUE [0:32] RW value= 0x00000000 */ 1299 #endif 1300 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY) 1301 /*IP Blk = MC_BASE2 Access=RW */ 1302 #define LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY 0x00000000UL 1303 /* CFG_CTRLR_BUSY_TURN_OFF_DELAY [0:32] RW value= 0x00000000 */ 1304 #endif 1305 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW) 1306 /*IP Blk = MC_BASE2 Access=RW */ 1307 #define LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW 0x00000000UL 1308 /* CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW [0:32] RW value= 0x00000000 */ 1309 #endif 1310 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF) 1311 /*IP Blk = MC_BASE2 Access=RW */ 1312 #define LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF 0x00000000UL 1313 /* CFG_CTRLR_BUSY_RESTART_HOLDOFF [0:32] RW value= 0x00000000 */ 1314 #endif 1315 #if !defined (LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY) 1316 /*IP Blk = MC_BASE2 Access=RW */ 1317 #define LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY 0x00000000UL 1318 /* CFG_PARITY_RDIMM_DELAY [0:32] RW value= 0x0 */ 1319 #endif 1320 #if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE) 1321 /*IP Blk = MC_BASE2 Access=RW */ 1322 #define LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE 0x00000000UL 1323 /* CFG_CTRLR_BUSY_ENABLE [0:32] RW value= 0x00000000 */ 1324 #endif 1325 #if !defined (LIBERO_SETTING_CFG_ASYNC_ODT) 1326 /*IP Blk = MC_BASE2 Access=RW */ 1327 #define LIBERO_SETTING_CFG_ASYNC_ODT 0x00000000UL 1328 /* CFG_ASYNC_ODT [0:32] RW value= 0x00000000 */ 1329 #endif 1330 #if !defined (LIBERO_SETTING_CFG_ZQ_CAL_DURATION) 1331 /*IP Blk = MC_BASE2 Access=RW */ 1332 #define LIBERO_SETTING_CFG_ZQ_CAL_DURATION 0x00000320UL 1333 /* CFG_ZQ_CAL_DURATION [0:32] RW value= 0x320 */ 1334 #endif 1335 #if !defined (LIBERO_SETTING_CFG_MRRI) 1336 /*IP Blk = MC_BASE2 Access=RW */ 1337 #define LIBERO_SETTING_CFG_MRRI 0x00000012UL 1338 /* CFG_MRRI [0:32] RW value= 0x12 */ 1339 #endif 1340 #if !defined (LIBERO_SETTING_INIT_ODT_FORCE_EN) 1341 /*IP Blk = MC_BASE2 Access=RW */ 1342 #define LIBERO_SETTING_INIT_ODT_FORCE_EN 0x00000000UL 1343 /* INIT_ODT_FORCE_EN [0:32] RW value= 0x00000000 */ 1344 #endif 1345 #if !defined (LIBERO_SETTING_INIT_ODT_FORCE_RANK) 1346 /*IP Blk = MC_BASE2 Access=RW */ 1347 #define LIBERO_SETTING_INIT_ODT_FORCE_RANK 0x00000000UL 1348 /* INIT_ODT_FORCE_RANK [0:32] RW value= 0x00000000 */ 1349 #endif 1350 #if !defined (LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY) 1351 /*IP Blk = MC_BASE2 Access=RW */ 1352 #define LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY 0x00000000UL 1353 /* CFG_PHYUPD_ACK_DELAY [0:32] RW value= 0x00000000 */ 1354 #endif 1355 #if !defined (LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1) 1356 /*IP Blk = MC_BASE2 Access=RW */ 1357 #define LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1 0x00000000UL 1358 /* CFG_MIRROR_X16_BG0_BG1 [0:32] RW value= 0x00000000 */ 1359 #endif 1360 #if !defined (LIBERO_SETTING_INIT_PDA_MR_W_REQ) 1361 /*IP Blk = MC_BASE2 Access=RW */ 1362 #define LIBERO_SETTING_INIT_PDA_MR_W_REQ 0x00000000UL 1363 /* INIT_PDA_MR_W_REQ [0:32] RW value= 0x00000000 */ 1364 #endif 1365 #if !defined (LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT) 1366 /*IP Blk = MC_BASE2 Access=RW */ 1367 #define LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT 0x00000000UL 1368 /* INIT_PDA_NIBBLE_SELECT [0:32] RW value= 0x00000000 */ 1369 #endif 1370 #if !defined (LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH) 1371 /*IP Blk = MC_BASE2 Access=RW */ 1372 #define LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH 0x00000000UL 1373 /* CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH [0:32] RW value= 0x00000000 */ 1374 #endif 1375 #if !defined (LIBERO_SETTING_CFG_CKSRE) 1376 /*IP Blk = MC_BASE2 Access=RW */ 1377 #define LIBERO_SETTING_CFG_CKSRE 0x00000008UL 1378 /* CFG_CKSRE [0:32] RW value= 0x00000008 */ 1379 #endif 1380 #if !defined (LIBERO_SETTING_CFG_CKSRX) 1381 /*IP Blk = MC_BASE2 Access=RW */ 1382 #define LIBERO_SETTING_CFG_CKSRX 0x0000000BUL 1383 /* CFG_CKSRX [0:32] RW value= 0x0000000b */ 1384 #endif 1385 #if !defined (LIBERO_SETTING_CFG_RCD_STAB) 1386 /*IP Blk = MC_BASE2 Access=RW */ 1387 #define LIBERO_SETTING_CFG_RCD_STAB 0x00000000UL 1388 /* CFG_RCD_STAB [0:32] RW value= 0x00000000 */ 1389 #endif 1390 #if !defined (LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY) 1391 /*IP Blk = MC_BASE2 Access=RW */ 1392 #define LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY 0x00000000UL 1393 /* CFG_DFI_T_CTRL_DELAY [0:32] RW value= 0x00000000 */ 1394 #endif 1395 #if !defined (LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE) 1396 /*IP Blk = MC_BASE2 Access=RW */ 1397 #define LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE 0x00000000UL 1398 /* CFG_DFI_T_DRAM_CLK_ENABLE [0:32] RW value= 0x00000000 */ 1399 #endif 1400 #if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH) 1401 /*IP Blk = MC_BASE2 Access=RW */ 1402 #define LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH 0x00000000UL 1403 /* CFG_IDLE_TIME_TO_SELF_REFRESH [0:32] RW value= 0x00000000 */ 1404 #endif 1405 #if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN) 1406 /*IP Blk = MC_BASE2 Access=RW */ 1407 #define LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN 0x00000000UL 1408 /* CFG_IDLE_TIME_TO_POWER_DOWN [0:32] RW value= 0x00000000 */ 1409 #endif 1410 #if !defined (LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF) 1411 /*IP Blk = MC_BASE2 Access=RW */ 1412 #define LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF 0x00000000UL 1413 /* CFG_BURST_RW_REFRESH_HOLDOFF [0:32] RW value= 0x00000000 */ 1414 #endif 1415 #if !defined (LIBERO_SETTING_CFG_BG_INTERLEAVE) 1416 /*IP Blk = MC_BASE2 Access=RW */ 1417 #define LIBERO_SETTING_CFG_BG_INTERLEAVE 0x00000001UL 1418 /* CFG_BG_INTERLEAVE [0:32] RW value= 0x00000001 */ 1419 #endif 1420 #if !defined (LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING) 1421 /*IP Blk = MC_BASE2 Access=RW */ 1422 #define LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING 0x00000000UL 1423 /* CFG_REFRESH_DURING_PHY_TRAINING [0:32] RW value= 0x00000000 */ 1424 #endif 1425 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0) 1426 /*IP Blk = MPFE Access=RW */ 1427 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0 0x00000000UL 1428 /* CFG_STARVE_TIMEOUT_P0 [0:32] RW value= 0x00000000 */ 1429 #endif 1430 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1) 1431 /*IP Blk = MPFE Access=RW */ 1432 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1 0x00000000UL 1433 /* CFG_STARVE_TIMEOUT_P1 [0:32] RW value= 0x00000000 */ 1434 #endif 1435 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2) 1436 /*IP Blk = MPFE Access=RW */ 1437 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2 0x00000000UL 1438 /* CFG_STARVE_TIMEOUT_P2 [0:32] RW value= 0x00000000 */ 1439 #endif 1440 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3) 1441 /*IP Blk = MPFE Access=RW */ 1442 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3 0x00000000UL 1443 /* CFG_STARVE_TIMEOUT_P3 [0:32] RW value= 0x00000000 */ 1444 #endif 1445 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4) 1446 /*IP Blk = MPFE Access=RW */ 1447 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4 0x00000000UL 1448 /* CFG_STARVE_TIMEOUT_P4 [0:32] RW value= 0x00000000 */ 1449 #endif 1450 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5) 1451 /*IP Blk = MPFE Access=RW */ 1452 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5 0x00000000UL 1453 /* CFG_STARVE_TIMEOUT_P5 [0:32] RW value= 0x00000000 */ 1454 #endif 1455 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6) 1456 /*IP Blk = MPFE Access=RW */ 1457 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6 0x00000000UL 1458 /* CFG_STARVE_TIMEOUT_P6 [0:32] RW value= 0x00000000 */ 1459 #endif 1460 #if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7) 1461 /*IP Blk = MPFE Access=RW */ 1462 #define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7 0x00000000UL 1463 /* CFG_STARVE_TIMEOUT_P7 [0:32] RW value= 0x00000000 */ 1464 #endif 1465 #if !defined (LIBERO_SETTING_CFG_REORDER_EN) 1466 /*IP Blk = REORDER Access=RW */ 1467 #define LIBERO_SETTING_CFG_REORDER_EN 0x00000001UL 1468 /* CFG_REORDER_EN [0:32] RW value= 0x00000001 */ 1469 #endif 1470 #if !defined (LIBERO_SETTING_CFG_REORDER_QUEUE_EN) 1471 /*IP Blk = REORDER Access=RW */ 1472 #define LIBERO_SETTING_CFG_REORDER_QUEUE_EN 0x00000001UL 1473 /* CFG_REORDER_QUEUE_EN [0:32] RW value= 0x00000001 */ 1474 #endif 1475 #if !defined (LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN) 1476 /*IP Blk = REORDER Access=RW */ 1477 #define LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN 0x00000000UL 1478 /* CFG_INTRAPORT_REORDER_EN [0:32] RW value= 0x00000000 */ 1479 #endif 1480 #if !defined (LIBERO_SETTING_CFG_MAINTAIN_COHERENCY) 1481 /*IP Blk = REORDER Access=RW */ 1482 #define LIBERO_SETTING_CFG_MAINTAIN_COHERENCY 0x00000001UL 1483 /* CFG_MAINTAIN_COHERENCY [0:32] RW value= 0x00000001 */ 1484 #endif 1485 #if !defined (LIBERO_SETTING_CFG_Q_AGE_LIMIT) 1486 /*IP Blk = REORDER Access=RW */ 1487 #define LIBERO_SETTING_CFG_Q_AGE_LIMIT 0x000000FFUL 1488 /* CFG_Q_AGE_LIMIT [0:32] RW value= 0x000000FF */ 1489 #endif 1490 #if !defined (LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY) 1491 /*IP Blk = REORDER Access=RW */ 1492 #define LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY 0x00000000UL 1493 /* CFG_RO_CLOSED_PAGE_POLICY [0:32] RW value= 0x00000000 */ 1494 #endif 1495 #if !defined (LIBERO_SETTING_CFG_REORDER_RW_ONLY) 1496 /*IP Blk = REORDER Access=RW */ 1497 #define LIBERO_SETTING_CFG_REORDER_RW_ONLY 0x00000000UL 1498 /* CFG_REORDER_RW_ONLY [0:32] RW value= 0x00000000 */ 1499 #endif 1500 #if !defined (LIBERO_SETTING_CFG_RO_PRIORITY_EN) 1501 /*IP Blk = REORDER Access=RW */ 1502 #define LIBERO_SETTING_CFG_RO_PRIORITY_EN 0x00000000UL 1503 /* CFG_RO_PRIORITY_EN [0:32] RW value= 0x00000000 */ 1504 #endif 1505 #if !defined (LIBERO_SETTING_CFG_DM_EN) 1506 /*IP Blk = RMW Access=RW */ 1507 #define LIBERO_SETTING_CFG_DM_EN 0x00000001UL 1508 /* CFG_DM_EN [0:32] RW value= 0x1 */ 1509 #endif 1510 #if !defined (LIBERO_SETTING_CFG_RMW_EN) 1511 /*IP Blk = RMW Access=RW */ 1512 #define LIBERO_SETTING_CFG_RMW_EN 0x00000000UL 1513 /* CFG_RMW_EN [0:32] RW value= 0x0 */ 1514 #endif 1515 #if !defined (LIBERO_SETTING_CFG_ECC_CORRECTION_EN) 1516 /*IP Blk = ECC Access=RW */ 1517 #define LIBERO_SETTING_CFG_ECC_CORRECTION_EN 0x00000000UL 1518 /* CFG_ECC_CORRECTION_EN [0:32] RW value= 0x0 */ 1519 #endif 1520 #if !defined (LIBERO_SETTING_CFG_ECC_BYPASS) 1521 /*IP Blk = ECC Access=RW */ 1522 #define LIBERO_SETTING_CFG_ECC_BYPASS 0x00000000UL 1523 /* CFG_ECC_BYPASS [0:32] RW value= 0x00000000 */ 1524 #endif 1525 #if !defined (LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN) 1526 /*IP Blk = ECC Access=RW */ 1527 #define LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN 0x00000000UL 1528 /* INIT_WRITE_DATA_1B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ 1529 #endif 1530 #if !defined (LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN) 1531 /*IP Blk = ECC Access=RW */ 1532 #define LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN 0x00000000UL 1533 /* INIT_WRITE_DATA_2B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ 1534 #endif 1535 #if !defined (LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH) 1536 /*IP Blk = ECC Access=RW */ 1537 #define LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH 0x00000000UL 1538 /* CFG_ECC_1BIT_INT_THRESH [0:32] RW value= 0x00000000 */ 1539 #endif 1540 #if !defined (LIBERO_SETTING_INIT_READ_CAPTURE_ADDR) 1541 /*IP Blk = READ_CAPT Access=RW */ 1542 #define LIBERO_SETTING_INIT_READ_CAPTURE_ADDR 0x00000000UL 1543 /* INIT_READ_CAPTURE_ADDR [0:32] RW value= 0x00000000 */ 1544 #endif 1545 #if !defined (LIBERO_SETTING_CFG_ERROR_GROUP_SEL) 1546 /*IP Blk = MTA Access=RW */ 1547 #define LIBERO_SETTING_CFG_ERROR_GROUP_SEL 0x00000000UL 1548 /* CFG_ERROR_GROUP_SEL [0:32] RW value= 0x00000000 */ 1549 #endif 1550 #if !defined (LIBERO_SETTING_CFG_DATA_SEL) 1551 /*IP Blk = MTA Access=RW */ 1552 #define LIBERO_SETTING_CFG_DATA_SEL 0x00000000UL 1553 /* CFG_DATA_SEL [0:32] RW value= 0x00000000 */ 1554 #endif 1555 #if !defined (LIBERO_SETTING_CFG_TRIG_MODE) 1556 /*IP Blk = MTA Access=RW */ 1557 #define LIBERO_SETTING_CFG_TRIG_MODE 0x00000000UL 1558 /* CFG_TRIG_MODE [0:32] RW value= 0x00000000 */ 1559 #endif 1560 #if !defined (LIBERO_SETTING_CFG_POST_TRIG_CYCS) 1561 /*IP Blk = MTA Access=RW */ 1562 #define LIBERO_SETTING_CFG_POST_TRIG_CYCS 0x00000000UL 1563 /* CFG_POST_TRIG_CYCS [0:32] RW value= 0x00000000 */ 1564 #endif 1565 #if !defined (LIBERO_SETTING_CFG_TRIG_MASK) 1566 /*IP Blk = MTA Access=RW */ 1567 #define LIBERO_SETTING_CFG_TRIG_MASK 0x00000000UL 1568 /* CFG_TRIG_MASK [0:32] RW value= 0x00000000 */ 1569 #endif 1570 #if !defined (LIBERO_SETTING_CFG_EN_MASK) 1571 /*IP Blk = MTA Access=RW */ 1572 #define LIBERO_SETTING_CFG_EN_MASK 0x00000000UL 1573 /* CFG_EN_MASK [0:32] RW value= 0x00000000 */ 1574 #endif 1575 #if !defined (LIBERO_SETTING_MTC_ACQ_ADDR) 1576 /*IP Blk = MTA Access=RW */ 1577 #define LIBERO_SETTING_MTC_ACQ_ADDR 0x00000000UL 1578 /* MTC_ACQ_ADDR [0:32] RW value= 0x00000000 */ 1579 #endif 1580 #if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_0) 1581 /*IP Blk = MTA Access=RW */ 1582 #define LIBERO_SETTING_CFG_TRIG_MT_ADDR_0 0x00000000UL 1583 /* CFG_TRIG_MT_ADDR_0 [0:32] RW value= 0x00000000 */ 1584 #endif 1585 #if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_1) 1586 /*IP Blk = MTA Access=RW */ 1587 #define LIBERO_SETTING_CFG_TRIG_MT_ADDR_1 0x00000000UL 1588 /* CFG_TRIG_MT_ADDR_1 [0:32] RW value= 0x00000000 */ 1589 #endif 1590 #if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_0) 1591 /*IP Blk = MTA Access=RW */ 1592 #define LIBERO_SETTING_CFG_TRIG_ERR_MASK_0 0x00000000UL 1593 /* CFG_TRIG_ERR_MASK_0 [0:32] RW value= 0x00000000 */ 1594 #endif 1595 #if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_1) 1596 /*IP Blk = MTA Access=RW */ 1597 #define LIBERO_SETTING_CFG_TRIG_ERR_MASK_1 0x00000000UL 1598 /* CFG_TRIG_ERR_MASK_1 [0:32] RW value= 0x00000000 */ 1599 #endif 1600 #if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_2) 1601 /*IP Blk = MTA Access=RW */ 1602 #define LIBERO_SETTING_CFG_TRIG_ERR_MASK_2 0x00000000UL 1603 /* CFG_TRIG_ERR_MASK_2 [0:32] RW value= 0x00000000 */ 1604 #endif 1605 #if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_3) 1606 /*IP Blk = MTA Access=RW */ 1607 #define LIBERO_SETTING_CFG_TRIG_ERR_MASK_3 0x00000000UL 1608 /* CFG_TRIG_ERR_MASK_3 [0:32] RW value= 0x00000000 */ 1609 #endif 1610 #if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_4) 1611 /*IP Blk = MTA Access=RW */ 1612 #define LIBERO_SETTING_CFG_TRIG_ERR_MASK_4 0x00000000UL 1613 /* CFG_TRIG_ERR_MASK_4 [0:32] RW value= 0x00000000 */ 1614 #endif 1615 #if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_0) 1616 /*IP Blk = MTA Access=RW */ 1617 #define LIBERO_SETTING_MTC_ACQ_WR_DATA_0 0x00000000UL 1618 /* MTC_ACQ_WR_DATA_0 [0:32] RW value= 0x00000000 */ 1619 #endif 1620 #if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_1) 1621 /*IP Blk = MTA Access=RW */ 1622 #define LIBERO_SETTING_MTC_ACQ_WR_DATA_1 0x00000000UL 1623 /* MTC_ACQ_WR_DATA_1 [0:32] RW value= 0x00000000 */ 1624 #endif 1625 #if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_2) 1626 /*IP Blk = MTA Access=RW */ 1627 #define LIBERO_SETTING_MTC_ACQ_WR_DATA_2 0x00000000UL 1628 /* MTC_ACQ_WR_DATA_2 [0:32] RW value= 0x00000000 */ 1629 #endif 1630 #if !defined (LIBERO_SETTING_CFG_PRE_TRIG_CYCS) 1631 /*IP Blk = MTA Access=RW */ 1632 #define LIBERO_SETTING_CFG_PRE_TRIG_CYCS 0x00000000UL 1633 /* CFG_PRE_TRIG_CYCS [0:32] RW value= 0x00000000 */ 1634 #endif 1635 #if !defined (LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR) 1636 /*IP Blk = MTA Access=RW */ 1637 #define LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR 0x00000000UL 1638 /* CFG_DATA_SEL_FIRST_ERROR [0:32] RW value= 0x00000000 */ 1639 #endif 1640 #if !defined (LIBERO_SETTING_CFG_DQ_WIDTH) 1641 /*IP Blk = DYN_WIDTH_ADJ Access=RW */ 1642 #define LIBERO_SETTING_CFG_DQ_WIDTH 0x00000000UL 1643 /* CFG_DQ_WIDTH [0:32] RW value= 0x0 */ 1644 #endif 1645 #if !defined (LIBERO_SETTING_CFG_ACTIVE_DQ_SEL) 1646 /*IP Blk = DYN_WIDTH_ADJ Access=RW */ 1647 #define LIBERO_SETTING_CFG_ACTIVE_DQ_SEL 0x00000000UL 1648 /* CFG_ACTIVE_DQ_SEL [0:32] RW value= 0x00000000 */ 1649 #endif 1650 #if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ) 1651 /*IP Blk = CA_PAR_ERR Access=RW */ 1652 #define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ 0x00000000UL 1653 /* INIT_CA_PARITY_ERROR_GEN_REQ [0:32] RW value= 0x00000000 */ 1654 #endif 1655 #if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD) 1656 /*IP Blk = CA_PAR_ERR Access=RW */ 1657 #define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD 0x00000000UL 1658 /* INIT_CA_PARITY_ERROR_GEN_CMD [0:32] RW value= 0x00000000 */ 1659 #endif 1660 #if !defined (LIBERO_SETTING_CFG_DFI_T_RDDATA_EN) 1661 /*IP Blk = DFI Access=RW */ 1662 #define LIBERO_SETTING_CFG_DFI_T_RDDATA_EN 0x00000015UL 1663 /* CFG_DFI_T_RDDATA_EN [0:32] RW value= 0x15 */ 1664 #endif 1665 #if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT) 1666 /*IP Blk = DFI Access=RW */ 1667 #define LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT 0x00000006UL 1668 /* CFG_DFI_T_PHY_RDLAT [0:32] RW value= 0x6 */ 1669 #endif 1670 #if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT) 1671 /*IP Blk = DFI Access=RW */ 1672 #define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL 1673 /* CFG_DFI_T_PHY_WRLAT [0:32] RW value= 0x3 */ 1674 #endif 1675 #if !defined (LIBERO_SETTING_CFG_DFI_PHYUPD_EN) 1676 /*IP Blk = DFI Access=RW */ 1677 #define LIBERO_SETTING_CFG_DFI_PHYUPD_EN 0x00000001UL 1678 /* CFG_DFI_PHYUPD_EN [0:32] RW value= 0x00000001 */ 1679 #endif 1680 #if !defined (LIBERO_SETTING_INIT_DFI_LP_DATA_REQ) 1681 /*IP Blk = DFI Access=RW */ 1682 #define LIBERO_SETTING_INIT_DFI_LP_DATA_REQ 0x00000000UL 1683 /* INIT_DFI_LP_DATA_REQ [0:32] RW value= 0x00000000 */ 1684 #endif 1685 #if !defined (LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ) 1686 /*IP Blk = DFI Access=RW */ 1687 #define LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ 0x00000000UL 1688 /* INIT_DFI_LP_CTRL_REQ [0:32] RW value= 0x00000000 */ 1689 #endif 1690 #if !defined (LIBERO_SETTING_INIT_DFI_LP_WAKEUP) 1691 /*IP Blk = DFI Access=RW */ 1692 #define LIBERO_SETTING_INIT_DFI_LP_WAKEUP 0x00000000UL 1693 /* INIT_DFI_LP_WAKEUP [0:32] RW value= 0x00000000 */ 1694 #endif 1695 #if !defined (LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE) 1696 /*IP Blk = DFI Access=RW */ 1697 #define LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE 0x00000000UL 1698 /* INIT_DFI_DRAM_CLK_DISABLE [0:32] RW value= 0x00000000 */ 1699 #endif 1700 #if !defined (LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE) 1701 /*IP Blk = DFI Access=RW */ 1702 #define LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE 0x00000000UL 1703 /* CFG_DFI_DATA_BYTE_DISABLE [0:32] RW value= 0x00000000 */ 1704 #endif 1705 #if !defined (LIBERO_SETTING_CFG_DFI_LVL_SEL) 1706 /*IP Blk = DFI Access=RW */ 1707 #define LIBERO_SETTING_CFG_DFI_LVL_SEL 0x00000000UL 1708 /* CFG_DFI_LVL_SEL [0:32] RW value= 0x00000000 */ 1709 #endif 1710 #if !defined (LIBERO_SETTING_CFG_DFI_LVL_PERIODIC) 1711 /*IP Blk = DFI Access=RW */ 1712 #define LIBERO_SETTING_CFG_DFI_LVL_PERIODIC 0x00000000UL 1713 /* CFG_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ 1714 #endif 1715 #if !defined (LIBERO_SETTING_CFG_DFI_LVL_PATTERN) 1716 /*IP Blk = DFI Access=RW */ 1717 #define LIBERO_SETTING_CFG_DFI_LVL_PATTERN 0x00000000UL 1718 /* CFG_DFI_LVL_PATTERN [0:32] RW value= 0x00000000 */ 1719 #endif 1720 #if !defined (LIBERO_SETTING_PHY_DFI_INIT_START) 1721 /*IP Blk = DFI Access=RW */ 1722 #define LIBERO_SETTING_PHY_DFI_INIT_START 0x00000001UL 1723 /* PHY_DFI_INIT_START [0:32] RW value= 0x1 */ 1724 #endif 1725 #if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0) 1726 /*IP Blk = AXI_IF Access=RW */ 1727 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0 0x00000000UL 1728 /* CFG_AXI_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ 1729 #endif 1730 #if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1) 1731 /*IP Blk = AXI_IF Access=RW */ 1732 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1 0x00000000UL 1733 /* CFG_AXI_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ 1734 #endif 1735 #if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0) 1736 /*IP Blk = AXI_IF Access=RW */ 1737 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0 0x00000000UL 1738 /* CFG_AXI_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ 1739 #endif 1740 #if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1) 1741 /*IP Blk = AXI_IF Access=RW */ 1742 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1 0x00000000UL 1743 /* CFG_AXI_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ 1744 #endif 1745 #if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0) 1746 /*IP Blk = AXI_IF Access=RW */ 1747 #define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 0x7FFFFFFFUL 1748 /* CFG_AXI_END_ADDRESS_AXI1_0 [0:32] RW value= 0x7FFFFFFF */ 1749 #endif 1750 #if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1) 1751 /*IP Blk = AXI_IF Access=RW */ 1752 #define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 0x00000000UL 1753 /* CFG_AXI_END_ADDRESS_AXI1_1 [0:32] RW value= 0x0 */ 1754 #endif 1755 #if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0) 1756 /*IP Blk = AXI_IF Access=RW */ 1757 #define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 0x7FFFFFFFUL 1758 /* CFG_AXI_END_ADDRESS_AXI2_0 [0:32] RW value= 0x7FFFFFFF */ 1759 #endif 1760 #if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1) 1761 /*IP Blk = AXI_IF Access=RW */ 1762 #define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 0x00000000UL 1763 /* CFG_AXI_END_ADDRESS_AXI2_1 [0:32] RW value= 0x0 */ 1764 #endif 1765 #if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0) 1766 /*IP Blk = AXI_IF Access=RW */ 1767 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0 0x00000000UL 1768 /* CFG_MEM_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ 1769 #endif 1770 #if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1) 1771 /*IP Blk = AXI_IF Access=RW */ 1772 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1 0x00000000UL 1773 /* CFG_MEM_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ 1774 #endif 1775 #if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0) 1776 /*IP Blk = AXI_IF Access=RW */ 1777 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0 0x00000000UL 1778 /* CFG_MEM_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ 1779 #endif 1780 #if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1) 1781 /*IP Blk = AXI_IF Access=RW */ 1782 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1 0x00000000UL 1783 /* CFG_MEM_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ 1784 #endif 1785 #if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1) 1786 /*IP Blk = AXI_IF Access=RW */ 1787 #define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1 0x00000000UL 1788 /* CFG_ENABLE_BUS_HOLD_AXI1 [0:32] RW value= 0x00000000 */ 1789 #endif 1790 #if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2) 1791 /*IP Blk = AXI_IF Access=RW */ 1792 #define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2 0x00000000UL 1793 /* CFG_ENABLE_BUS_HOLD_AXI2 [0:32] RW value= 0x00000000 */ 1794 #endif 1795 #if !defined (LIBERO_SETTING_CFG_AXI_AUTO_PCH) 1796 /*IP Blk = AXI_IF Access=RW */ 1797 #define LIBERO_SETTING_CFG_AXI_AUTO_PCH 0x00000000UL 1798 /* CFG_AXI_AUTO_PCH [0:32] RW value= 0x00000000 */ 1799 #endif 1800 #if !defined (LIBERO_SETTING_PHY_RESET_CONTROL) 1801 /*IP Blk = csr_custom Access=RW */ 1802 #define LIBERO_SETTING_PHY_RESET_CONTROL 0x00008001UL 1803 /* PHY_RESET_CONTROL [0:32] RW value= 0x8001 */ 1804 #endif 1805 #if !defined (LIBERO_SETTING_PHY_PC_RANK) 1806 /*IP Blk = csr_custom Access=RW */ 1807 #define LIBERO_SETTING_PHY_PC_RANK 0x00000001UL 1808 /* PHY_PC_RANK [0:32] RW value= 0x1 */ 1809 #endif 1810 #if !defined (LIBERO_SETTING_PHY_RANKS_TO_TRAIN) 1811 /*IP Blk = csr_custom Access=RW */ 1812 #define LIBERO_SETTING_PHY_RANKS_TO_TRAIN 0x00000001UL 1813 /* PHY_RANKS_TO_TRAIN [0:32] RW value= 0x1 */ 1814 #endif 1815 #if !defined (LIBERO_SETTING_PHY_WRITE_REQUEST) 1816 /*IP Blk = csr_custom Access=RW */ 1817 #define LIBERO_SETTING_PHY_WRITE_REQUEST 0x00000000UL 1818 /* PHY_WRITE_REQUEST [0:32] RW value= 0x00000000 */ 1819 #endif 1820 #if !defined (LIBERO_SETTING_PHY_READ_REQUEST) 1821 /*IP Blk = csr_custom Access=RW */ 1822 #define LIBERO_SETTING_PHY_READ_REQUEST 0x00000000UL 1823 /* PHY_READ_REQUEST [0:32] RW value= 0x00000000 */ 1824 #endif 1825 #if !defined (LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY) 1826 /*IP Blk = csr_custom Access=RW */ 1827 #define LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY 0x00000000UL 1828 /* PHY_WRITE_LEVEL_DELAY [0:32] RW value= 0x00000000 */ 1829 #endif 1830 #if !defined (LIBERO_SETTING_PHY_GATE_TRAIN_DELAY) 1831 /*IP Blk = csr_custom Access=RW */ 1832 #define LIBERO_SETTING_PHY_GATE_TRAIN_DELAY 0x0000003FUL 1833 /* PHY_GATE_TRAIN_DELAY [0:32] RW value= 0x3F */ 1834 #endif 1835 #if !defined (LIBERO_SETTING_PHY_EYE_TRAIN_DELAY) 1836 /*IP Blk = csr_custom Access=RW */ 1837 #define LIBERO_SETTING_PHY_EYE_TRAIN_DELAY 0x0000003FUL 1838 /* PHY_EYE_TRAIN_DELAY [0:32] RW value= 0x3F */ 1839 #endif 1840 #if !defined (LIBERO_SETTING_PHY_EYE_PAT) 1841 /*IP Blk = csr_custom Access=RW */ 1842 #define LIBERO_SETTING_PHY_EYE_PAT 0x00000000UL 1843 /* PHY_EYE_PAT [0:32] RW value= 0x00000000 */ 1844 #endif 1845 #if !defined (LIBERO_SETTING_PHY_START_RECAL) 1846 /*IP Blk = csr_custom Access=RW */ 1847 #define LIBERO_SETTING_PHY_START_RECAL 0x00000000UL 1848 /* PHY_START_RECAL [0:32] RW value= 0x00000000 */ 1849 #endif 1850 #if !defined (LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC) 1851 /*IP Blk = csr_custom Access=RW */ 1852 #define LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC 0x00000000UL 1853 /* PHY_CLR_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ 1854 #endif 1855 #if !defined (LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE) 1856 /*IP Blk = csr_custom Access=RW */ 1857 #define LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE 0x00000018UL 1858 /* PHY_TRAIN_STEP_ENABLE [0:32] RW value= 0x18 */ 1859 #endif 1860 #if !defined (LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT) 1861 /*IP Blk = csr_custom Access=RW */ 1862 #define LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT 0x00000000UL 1863 /* PHY_LPDDR_DQ_CAL_PAT [0:32] RW value= 0x00000000 */ 1864 #endif 1865 #if !defined (LIBERO_SETTING_PHY_INDPNDT_TRAINING) 1866 /*IP Blk = csr_custom Access=RW */ 1867 #define LIBERO_SETTING_PHY_INDPNDT_TRAINING 0x00000001UL 1868 /* PHY_INDPNDT_TRAINING [0:32] RW value= 0x1 */ 1869 #endif 1870 #if !defined (LIBERO_SETTING_PHY_ENCODED_QUAD_CS) 1871 /*IP Blk = csr_custom Access=RW */ 1872 #define LIBERO_SETTING_PHY_ENCODED_QUAD_CS 0x00000000UL 1873 /* PHY_ENCODED_QUAD_CS [0:32] RW value= 0x00000000 */ 1874 #endif 1875 #if !defined (LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE) 1876 /*IP Blk = csr_custom Access=RW */ 1877 #define LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE 0x00000000UL 1878 /* PHY_HALF_CLK_DLY_ENABLE [0:32] RW value= 0x00000000 */ 1879 #endif 1880 1881 #ifdef __cplusplus 1882 } 1883 #endif 1884 1885 1886 #endif /* #ifdef HW_DDRC_H_ */ 1887 1888
