1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_ddr_options.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_DDR_OPTIONS_H_ 28 #define HW_DDR_OPTIONS_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING) 36 /*Tip config: Referenced receivers in the CA bus are turned on for CA training. 37 These burn static power.(0x01 => turn off ; 0x00 => no action ) */ 38 #define LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING 0x00000001UL 39 /* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */ 40 #endif 41 #if !defined (LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN) 42 /*Tip config: 1 => 1 rank, 3 => 2 ranks */ 43 #define LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN 0x00000001UL 44 /* USER_INPUT_PHY_RANKS_TO_TRAIN [0:2] RW value= 0x1 */ 45 #endif 46 #if !defined (LIBERO_SETTING_TRAINING_SKIP_SETTING) 47 /*Tip config: Pick what trainings we want performed by the TIP, default is 0x1F 48 */ 49 #define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL 50 /* SKIP_BCLKSCLK_TIP_TRAINING [0:1] RW value= 0x0 */ 51 /* SKIP_ADDCMD_TIP_TRAINING [1:1] RW value= 0x1 */ 52 /* SKIP_WRLVL_TIP_TRAINING [2:1] RW value= 0x0 */ 53 /* SKIP_RDGATE_TIP_TRAINING [3:1] RW value= 0x0 */ 54 /* SKIP_DQ_DQS_OPT_TIP_TRAINING [4:1] RW value= 0x0 */ 55 #endif 56 #if !defined (LIBERO_SETTING_TIP_CFG_PARAMS) 57 /*Tip config: default: 0x2,0x4,0x0,0x1F,0x1F */ 58 #define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL 59 /* ADDCMD_OFFSET [0:3] RW value= 0x2 */ 60 /* BCKLSCLK_OFFSET [3:3] RW value= 0x5 */ 61 /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ 62 /* READ_GATE_MIN_READS [13:8] RW value= 0x7F */ 63 /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ 64 #endif 65 #if !defined (LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET) 66 /*in simulation we need to set this to 2, for hardware it will be dependent on 67 the trace lengths */ 68 #define LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET 0x00000002UL 69 /* TIP_CONFIG_PARAMS_BCLK_VCOPHS [0:32] RW value= 0x02 */ 70 #endif 71 72 #ifdef __cplusplus 73 } 74 #endif 75 76 77 #endif /* #ifdef HW_DDR_OPTIONS_H_ */ 78 79
