1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_ddr_mode.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_DDR_MODE_H_ 28 #define HW_DDR_MODE_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_DDRPHY_MODE) 36 /*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4, 37 111 OFF_MODE */ 38 #define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL 39 /* DDRMODE [0:3] RW value= 0x4 */ 40 /* ECC [3:1] RW value= 0x0 */ 41 /* CRC [4:1] RW value= 0x0 */ 42 /* BUS_WIDTH [5:3] RW value= 0x1 */ 43 /* DMI_DBI [8:1] RW value= 0x1 */ 44 /* DQ_DRIVE [9:2] RW value= 0x1 */ 45 /* DQS_DRIVE [11:2] RW value= 0x1 */ 46 /* ADD_CMD_DRIVE [13:2] RW value= 0x2 */ 47 /* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */ 48 /* DQ_TERMINATION [17:2] RW value= 0x0 */ 49 /* DQS_TERMINATION [19:2] RW value= 0x0 */ 50 /* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */ 51 /* PRESET_ODT_CLK [23:2] RW value= 0x0 */ 52 /* POWER_DOWN [25:1] RW value= 0x0 */ 53 /* RANK [26:1] RW value= 0x0 */ 54 /* RESERVED [27:5] RSVD */ 55 #endif 56 #if !defined (LIBERO_SETTING_DATA_LANES_USED) 57 /*number of lanes used for data- does not include ECC, infer from mode register 58 */ 59 #define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL 60 /* DATA_LANES [0:3] RW value= 0x4 */ 61 #endif 62 63 #ifdef __cplusplus 64 } 65 #endif 66 67 68 #endif /* #ifdef HW_DDR_MODE_H_ */ 69 70
