1 /*
2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #ifndef _MEC_PCR_API_H
7 #define _MEC_PCR_API_H
8
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12
13 #include "mec_defs.h"
14 #include <device_mec5.h>
15
16 /* Interfaces to any C modules */
17 #ifdef __cplusplus
18 extern "C"
19 {
20 #endif
21
22 #define PCR_SLP_EN0_IDX 0u
23 #define PCR_SLP_EN1_IDX 1u
24 #define PCR_SLP_EN2_IDX 2u
25 #define PCR_SLP_EN3_IDX 3u
26 #define PCR_SLP_EN4_IDX 4u
27 #define PCR_SLP_EN_IDX_MAX 5u
28
29 /* UART2 SLP_EN2 b[28]
30 * UART3 SLP_EN2 b[30]
31 */
32 enum mec_pcr_scr_id {
33 MEC_PCR_STAP_POS = 0, /* index 0 bit 0 */
34 MEC_PCR_OTP_POS,
35 MEC_PCR_ISPI_POS,
36 MEC_PCR_CHIP_TEST_POS,
37 MEC_PCR_ECIA = 32, /* index 1 bit 0 */
38 MEC_PCR_PECI,
39 MEC_PCR_TACH0,
40 MEC_PCR_PWM0 = 36, /* index 1 bit 4 */
41 MEC_PCR_PMC,
42 MEC_PCR_DMA,
43 MEC_PCR_TFDP,
44 MEC_PCR_CPU,
45 MEC_PCR_WDT0,
46 MEC_PCR_I2C_SMB0,
47 MEC_PCR_TACH1,
48 MEC_PCR_TACH2,
49 MEC_PCR_TACH3,
50 MEC_PCR_PWM1 = 52, /* index 1 bit 20 */
51 MEC_PCR_PWM2,
52 MEC_PCR_PWM3,
53 MEC_PCR_PWM4,
54 MEC_PCR_PWM5,
55 MEC_PCR_PWM6,
56 MEC_PCR_PWM7,
57 MEC_PCR_PWM8, /* index 1 bit 27 */
58 MEC_PCR_ECS = 61, /* index 1 bit 29 */
59 MEC_PCR_BTMR0,
60 MEC_PCR_BTMR1,
61 MEC_PCR_EMI0, /* 64: index 2 bit 0 */
62 MEC_PCR_UART0,
63 MEC_PCR_UART1,
64 MEC_PCR_EMI1,
65 MEC_PCR_EMI2,
66 MEC_PCR_GCFG = 76, /* index 2 bit 12 */
67 MEC_PCR_ACPI_EC0,
68 MEC_PCR_ACPI_EC1,
69 MEC_PCR_ACPI_PM1,
70 MEC_PCR_KBC0,
71 MEC_PCR_MBOX0,
72 MEC_PCR_RTC0,
73 MEC_PCR_ESPI,
74 MEC_PCR_SCR32,
75 MEC_PCR_ACPI_EC2,
76 MEC_PCR_ACPI_EC3,
77 MEC_PCR_ACPI_EC4,
78 MEC_PCR_P80BD0 = 89, /* index 2 bit 25 */
79 MEC_PCR_ESPI_TAF = 91, /* index 2 bit 27 */
80 MEC_PCR_UART2 = 92, /* index 2 bit 28 */
81 MEC_PCR_GLUE = 93, /* index 2 bit 29 */
82 MEC_PCR_UART3, /* index 2 bit 30 */
83 MEC_PCR_ADC0 = 99, /* index 3 bit 3 */
84 MEC_PCR_PS2_0 = 101, /* index 3 bit 5 */
85 MEC_PCR_PS2_1,
86 MEC_PCR_GSPI0 = 105, /* index 3 bit 9 */
87 MEC_PCR_HTMR0,
88 MEC_PCR_KSCAN0, /* index 3 bit 11 */
89 MEC_PCR_RPMPWM0, /* index 3 bit 12 */
90 MEC_PCR_I2C_SMB1,
91 MEC_PCR_I2C_SMB2,
92 MEC_PCR_I2C_SMB3,
93 MEC_PCR_LED0,
94 MEC_PCR_LED1,
95 MEC_PCR_LED2,
96 MEC_PCR_BCL,
97 MEC_PCR_I2C_SMB4,
98 MEC_PCR_BTMR2,
99 MEC_PCR_BTMR3,
100 MEC_PCR_BTMR4,
101 MEC_PCR_BTMR5,
102 MEC_PCR_LED3,
103 MEC_PCR_CRYPTO_ALL,
104 MEC_PCR_HTMR1 = 125, /* index 3 bit 29 */
105 MEC_PCR_CCT0,
106 MEC_PCR_PWM9, /* index 3 bit 31 */
107 MEC_PCR_PWM10 = 128, /* index 4 bit 0 */
108 MEC_PCR_PWM11,
109 MEC_PCR_CTMR0,
110 MEC_PCR_CTMR1,
111 MEC_PCR_CTMR2,
112 MEC_PCR_CTMR3,
113 MEC_PCR_RTMR,
114 MEC_PCR_RPMPWM1,
115 MEC_PCR_QSPI0,
116 MEC_PCR_RCID0 = 138, /* index 4 bit 10 */
117 MEC_PCR_RCID1,
118 MEC_PCR_RCID2,
119 MEC_PCR_PROCHOT,
120 MEC_PCR_PSPI,
121 MEC_PCR_VBATR = 145, /* index 4 bit 17 */
122 MEC_PCR_VBATM,
123 MEC_PCR_RTC_WT,
124 MEC_PCR_VCI0,
125 MEC_PCR_GSPI1 = 150, /* index 4 bit 22 */
126 MEC_PCR_I3C_HOST = 153, /* index 4 bit 25 */
127 MEC_PCR_I3C_SEC = 154, /* index 4 bit 26 */
128 MEC_PCR_USB_OTG0 = 155, /* index 4 bit 27 */
129 MEC_PCR_ROM_WDT = 156, /* index 4 bit 28 */
130 MEC_PCR_MAX_ID = (PCR_SLP_EN_IDX_MAX * 32),
131 };
132
133 int mec_hal_pcr_is_host_reset(void);
134 int mec_hal_pcr_is_vcc_pwrgd(void);
135 int mec_hal_pcr_is_turbo_clock(void);
136
137 #define MEC_PCR_VCC_PWRGD_ACTIVE 0x01
138 #define MEC_PCR_VCC_PWRGD2_ACTIVE 0x02
139 uint32_t mec_hal_pcr_vcc_power_good_state(void);
140
141 uint32_t mec_hal_pcr_cpu_max_freq(void);
142 uint32_t mec_hal_pcr_cpu_clk_speed(void);
143 int mec_hal_pcr_cpu_clk_speed_set(uint32_t fhz);
144 uint32_t mec_hal_pcr_slow_clock_freq_get(void);
145 void mec_hal_pcr_slow_clock_freq_set(uint32_t freqhz);
146
147 /* Get/set PCR CPU clock divider. Caller should know PLL input frequency. */
148 enum mec_pcr_cpu_clk_div {
149 MEC_PCR_CPU_CLK_DIV_1 = 1,
150 MEC_PCR_CPU_CLK_DIV_2 = 2,
151 MEC_PCR_CPU_CLK_DIV_4 = 4,
152 MEC_PCR_CPU_CLK_DIV_16 = 16,
153 MEC_PCR_CPU_CLK_DIV_48 = 48,
154 };
155
156 uint32_t mec_hal_pcr_cpu_clock_divider(void);
157 int mec_hal_pcr_cpu_clock_divider_set(enum mec_pcr_cpu_clk_div clk_div);
158
159 bool mec_hal_pcr_is_pll_locked(void);
160
161 void mec_hal_pcr_set_blk_slp_en(uint16_t scr);
162 void mec_hal_pcr_clr_blk_slp_en(uint16_t scr);
163 void mec_hal_pcr_blk_slp_en(uint16_t src, uint8_t enable);
164 uint8_t mec_hal_pcr_is_blk_slp_en(uint16_t src);
165
166 uint32_t mec_hal_pcr_blk_reset(uint16_t src);
167 uint32_t mec_hal_pcr_blk_reset_critical(uint16_t src);
168
169 int mec_hal_pcr_slp_en_set(uint8_t regid, uint32_t val);
170 int mec_hal_pcr_slp_en_mask(uint8_t regid, uint32_t val, uint32_t mask);
171 void mec_hal_pcr_slp_en_set_all(void);
172 void mec_hal_pcr_slp_en_por(void);
173
174 /* Disable sleep */
mec_hal_pcr_sleep_disable(void)175 static inline void mec_hal_pcr_sleep_disable(void)
176 {
177 MEC_PCR->SSC = 0;
178 SCB->SCR &= ~MEC_BIT(2);
179 }
180
181 /* Trigger lite or heavy sleep */
mec_hal_pcr_lite_sleep(void)182 static inline void mec_hal_pcr_lite_sleep(void)
183 {
184 SCB->SCR &= ~MEC_BIT(2);
185 MEC_PCR->SSC = MEC_BIT(MEC_PCR_SSC_SLPALL_Pos);
186 }
187
mec_hal_pcr_deep_sleep(void)188 static inline void mec_hal_pcr_deep_sleep(void)
189 {
190 SCB->SCR |= MEC_BIT(2);
191 MEC_PCR->SSC = MEC_BIT(MEC_PCR_SSC_DEEPSLP_Pos) | MEC_BIT(MEC_PCR_SSC_SLPALL_Pos);
192 }
193
194 /* SoC reset */
195 void mec_hal_pcr_reset_system(void) __attribute__((__noreturn__));
196
197 #define MEC_PCR_PLATFORM_RST_IS_ESPI_PLTRST 1
198 void mec_hal_pcr_host_reset_select(uint8_t use_espi_platform_reset);
199 void mec_hal_pcr_release_reset_vcc(uint8_t release);
200
201 /* or separate sources */
202 enum mec_pll_clk32k_src {
203 MEC_PLL_CLK32K_SRC_NONE = 0,
204 MEC_PLL_CLK32K_SRC_SI,
205 MEC_PLL_CLK32K_SRC_XTAL,
206 MEC_PLL_CLK32K_SRC_PIN,
207 };
208
209 enum mec_periph_clk32k_src {
210 MEC_PERIPH_CLK32K_SRC_SI_SI,
211 MEC_PERIPH_CLK32K_SRC_XTAL_XTAL,
212 MEC_PERIPH_CLK32K_SRC_PIN_SI,
213 MEC_PERIPH_CLK32K_SRC_PIN_XTAL,
214 };
215
216 /* Single-endend crystal on XTAL2 pin instead of parallel on XTAL1 and XTAL2 */
217 #define MEC_CLK32K_FLAG_XTAL_SE_POS 0
218
219 #define MEC_CLK32K_PERIOD_MIN 1435u
220 #define MEC_CLK32K_PERIOD_MAX 1495u
221 #define MEC_CLK32K_DUTY_VARIATION_MAX 74u
222 #define MEC_CLK32K_VALID_COUNT_MIN 4u
223
224 struct mec_pcr_clkmon_cfg {
225 uint16_t period_min;
226 uint16_t period_max;
227 uint16_t duty_var;
228 uint8_t valid_min;
229 };
230
231 int mec_hal_pcr_clk32k_init(enum mec_pll_clk32k_src pll_src,
232 enum mec_periph_clk32k_src periph_src,
233 struct mec_pcr_clkmon_cfg *cfg,
234 uint32_t flags,
235 uint32_t lock_wait);
236
237 enum mec_pll_clk32k_src mec_hal_pll_get_clk32k_source(void);
238 enum mec_periph_clk32k_src mec_hal_vbr_get_periph_clk32_source(void);
239
240 #ifdef MEC5_HAS_PERIPH_PRIVILEGE
241 uint32_t mec_hal_pcr_blk_privilege_enable(uint8_t pid, uint8_t enable);
242 uint32_t mec_hal_pcr_blk_privilege_mask(uint8_t priv_idx, uint32_t en_mask, uint32_t dis_mask);
243 #endif
244
245 void mec_hal_pcr_save_clk_req_to_vbatm(uint16_t vbatm_byte_ofs);
246
247 #ifdef __cplusplus
248 }
249 #endif
250
251 #endif /* #ifndef _MEC_PCR_API_H */
252
