1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file wdt.h 28 *MEC1501 Watch Dog Timer Registers 29 */ 30 /** @defgroup MEC1501 Peripherals WDT 31 */ 32 33 #ifndef _WDT_H 34 #define _WDT_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ WDT ====================*/ 43 /* =========================================================================*/ 44 45 #define MCHP_WDT_BASE_ADDR 0x40000400u 46 47 /* WDT Interrupt */ 48 #define MCHP_WDT_GIRQ 21u 49 #define MCHP_WDT_GIRQ_NVIC 13u 50 #define MCHP_WDT_GIRQ_NVIC_DIRECT 171u 51 52 /* Bit position in Interrupt Aggregator GIRQ registers */ 53 #define MCHP_WDT_GIRQ_POS 2u 54 55 /* Interrupt Aggregator Source, Enable Set/Clear registers value */ 56 #define MCHP_WDT_GIRQ_VAL (1u << MCHP_WDT_GIRQ_POS) 57 58 59 /* Load register */ 60 #define MCHP_WDT_LOAD_REG_OFS 0x00u 61 #define MCHP_WDT_LOAD_REG_MASK 0xffffu 62 63 /* Control register */ 64 #define MCHP_WDT_CTRL_REG_OFS 0x04u 65 #define MCHP_WDT_CTRL_REG_MASK 0x021du 66 #define MCHP_WDT_CTRL_EN_POS 0u 67 #define MCHP_WDT_CTRL_EN_MASK (1u << MCHP_WDT_CTRL_EN_POS) 68 #define MCHP_WDT_CTRL_EN (1u << MCHP_WDT_CTRL_EN_POS) 69 #define MCHP_WDT_CTRL_HTMR_STALL_POS 2u 70 #define MCHP_WDT_CTRL_HTMR_STALL_MASK (1u << MCHP_WDT_CTRL_HTMR_STALL_POS) 71 #define MCHP_WDT_CTRL_HTMR_STALL_EN (1u << MCHP_WDT_CTRL_HTMR_STALL_POS) 72 #define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u 73 #define MCHP_WDT_CTRL_WKTMR_STALL_MASK (1u << MCHP_WDT_CTRL_WKTMR_STALL_POS) 74 #define MCHP_WDT_CTRL_WKTMR_STALL_EN (1u << MCHP_WDT_CTRL_WKTMR_STALL_POS) 75 #define MCHP_WDT_CTRL_JTAG_STALL_POS 4u 76 #define MCHP_WDT_CTRL_JTAG_STALL_MASK (1u << MCHP_WDT_CTRL_JTAG_STALL_POS) 77 #define MCHP_WDT_CTRL_JTAG_STALL_EN (1u << MCHP_WDT_CTRL_JTAG_STALL_POS) 78 /* 79 * WDT mode selecting action taken upon count expiration. 80 * 0 = Generate chip reset 81 * 1 = Clear this bit, 82 * Set event status 83 * Generate interrupt if event IEN bit is set 84 * Kick WDT causing it to reload from LOAD register 85 * If interrupt is enabled in GIRQ21 and NVIC then the EC will jump 86 * to the WDT ISR. 87 */ 88 #define MCHP_WDT_CTRL_MODE_POS 9u 89 #define MCHP_WDT_CTRL_MODE_MASK (1u << MCHP_WDT_CTRL_MODE_POS) 90 #define MCHP_WDT_CTRL_MODE_RESET (0u << MCHP_WDT_CTRL_MODE_POS) 91 #define MCHP_WDT_CTRL_MODE_IRQ (1u << MCHP_WDT_CTRL_MODE_POS) 92 93 /* WDT Kick register. Write any value to reload counter */ 94 #define MCHP_WDT_KICK_REG_OFS 0x08u 95 #define MCHP_WDT_KICK_REG_MASK 0xffu 96 #define MCHP_WDT_KICK_VAL 0 97 98 /* WDT Count register. Read only */ 99 #define MCHP_WDT_CNT_RO_REG_OFS 0x0cu 100 #define MCHP_WDT_CNT_RO_REG_MASK 0xffffu 101 102 /* Status Register */ 103 #define MCHP_WDT_STS_REG_OFS 0x10u 104 #define MCHP_WDT_STS_REG_MASK 0x01u 105 #define MCHP_WDT_STS_EVENT_IRQ_POS 0u 106 #define MCHP_WDT_STS_EVENT_IRQ (1u << MCHP_WDT_STS_EVENT_IRQ_POS) 107 108 /* Interrupt Enable Register */ 109 #define MCHP_WDT_IEN_REG_OFS 0x14u 110 #define MCHP_WDT_IEN_REG_MASK 0x01u 111 #define MCHP_WDT_IEN_EVENT_IRQ_POS 0u 112 #define MCHP_WDT_IEN_EVENT_IRQ_MASK (1u << (MCHP_WDT_IEN_EVENT_IRQ_POS)) 113 #define MCHP_WDT_IEN_EVENT_IRQ_EN (1u << (MCHP_WDT_IEN_EVENT_IRQ_POS)) 114 115 /* Register access */ 116 #define MCHP_WDT_LOAD_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_LOAD_REG_OFS) 117 #define MCHP_WDT_CTRL_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_CTRL_REG_OFS) 118 #define MCHP_WDT_KICK_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_KICK_REG_OFS) 119 #define MCHP_WDT_STS_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_STS_REG_OFS) 120 #define MCHP_WDT_IEN_REG_ADDR (MCHP_WDT_BASE_ADDR + MCHP_WDT_IEN_REG_OFS) 121 122 #define MCHP_WDT_LOAD() REG16(MCHP_WDT_LOAD_REG_ADDR) 123 #define MCHP_WDT_CTRL() REG16(MCHP_WDT_CTRL_REG_ADDR) 124 #define MCHP_WDT_KICK() REG8(MCHP_WDT_KICK_REG_ADDR) 125 #define MCHP_WDT_CNT() REG16(MCHP_WDT_CNT_REG_ADDR) 126 #define MCHP_WDT_STS() REG8(MCHP_WDT_STS_REG_ADDR) 127 #define MCHP_WDT_IEN() REG8(MCHP_WDT_IEN_REG_ADDR) 128 129 /** 130 * @brief Watch Dog Timer (WDT) 131 */ 132 typedef struct wdt_regs { 133 __IOM uint16_t LOAD; /*!< (@ 0x00000000) WDT Load */ 134 uint8_t RSVD1[2]; 135 __IOM uint16_t CTRL; /*!< (@ 0x00000004) WDT Control */ 136 uint8_t RSVD2[2]; 137 __OM uint8_t KICK; /*!< (@ 0x00000008) WDT Kick (WO) */ 138 uint8_t RSVD3[3]; 139 __IM uint16_t CNT; /*!< (@ 0x0000000c) WDT Count (RO) */ 140 uint8_t RSVD4[2]; 141 __IOM uint16_t STS; /*!< (@ 0x00000010) WDT Status */ 142 uint8_t RSVD5[2]; 143 __IOM uint8_t IEN; /*!< (@ 0x00000014) WDT Interrupt Enable */ 144 } WDT_Type; 145 146 #endif /* #ifndef _WDT_H */ 147 /* end wdt.h */ 148 /** @} 149 */ 150
