1 /** 2 * 3 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file spi_periph.h 28 *MEC1501 SPI Peripheral registers 29 */ 30 /** @defgroup MEC152x SPI peripheral device 31 */ 32 33 #ifndef _SPI_PERIPH_H 34 #define _SPI_PERIPH_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ SPI Peripheral =========== */ 43 /* =========================================================================*/ 44 45 #define MCHP_SPIP_BASE_ADDR 0x40007000u 46 47 /* 48 * SPIP interrupts 49 */ 50 #define MCHP_SPIP_GIRQ 18u 51 52 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 53 #define MCHP_SPIP_GIRQ_POS 0u 54 55 #define MCHP_SPIP_GIRQ_VAL (1u << MCHP_SPIP_GIRQ_POS) 56 57 /* SPIP GIRQ aggregated NVIC input */ 58 #define MCHP_SPIP_NVIC_AGGR 10u 59 60 /* SPIP direct NVIC inputs */ 61 #define MCHP_SPIP_NVIC_DIRECT 90u 62 63 /* SPIP Configuration register */ 64 #define MCHP_SPIP_CFG_REG_OFS 0 65 #define MCHP_SPIP_CFG_REG_MASK 0x00ff0301u 66 #define MCHP_SPIP_CFG_SQ_SEL_POS 0 67 #define MCHP_SPIP_CFG_SINGLE (0u << 0) 68 #define MCHP_SPIP_CFG_QUAD (1u << 0) 69 #define MCHP_SPIP_CFG_TAR_POS 8 70 #define MCHP_SPIP_CFG_TAR_MASK0 0x03u 71 #define MCHP_SPIP_CFG_TAR_MASK (0x03u << 8) 72 #define MCHP_SPIP_CFG_TAR_1 0 73 #define MCHP_SPIP_CFG_TAR_2 (1u << 8) 74 #define MCHP_SPIP_CFG_TAR_4 (2u << 8) 75 #define MCHP_SPIP_CFG_TAR_8 (3u << 8) 76 #define MCHP_SPIP_CFG_WTM_POS 16 77 #define MCHP_SPIP_CFG_WTM_MASK0 0xffu 78 #define MCHP_SPIP_CFG_WTM_MASK 0xff0000u 79 80 /* SPIP Status register */ 81 #define MCHP_SPIP_STS_REG_OFS 4 82 #define MCHP_SPIP_STS_REG_MASK 0x1fffef7bu 83 #define MCHP_SPIP_SPI_STS_MWD (1u << 0) 84 #define MCHP_SPIP_SPI_STS_MRD (1u << 1) 85 #define MCHP_SPIP_SPI_STS_MWB (1u << 3) 86 #define MCHP_SPIP_SPI_STS_MRB (1u << 4) 87 #define MCHP_SPIP_SPI_STS_SRTB (1u << 5) 88 #define MCHP_SPIP_SPI_STS_PHI_REQ (1u << 6) 89 #define MCHP_SPIP_SPI_STS_RXFE (1u << 8) 90 #define MCHP_SPIP_SPI_STS_RXFF (1u << 9) 91 #define MCHP_SPIP_SPI_STS_TXFE (1u << 10) 92 #define MCHP_SPIP_SPI_STS_TXFF (1u << 11) 93 #define MCHP_SPIP_SPI_STS_SCCE (1u << 13) 94 #define MCHP_SPIP_SPI_STS_OBF (1u << 15) 95 #define MCHP_SPIP_SPI_STS_SPIMR (1u << 16) 96 #define MCHP_SPIP_SPI_STS_RXF_RSTD (1u << 17) 97 #define MCHP_SPIP_SPI_STS_TXF_RSTD (1u << 18) 98 #define MCHP_SPIP_SPI_STS_LIM0 (1u << 19) 99 #define MCHP_SPIP_SPI_STS_LIM1 (1u << 20) 100 #define MCHP_SPIP_SPI_STS_ABERR (1u << 21) 101 #define MCHP_SPIP_SPI_STS_UNDEF_CMD (1u << 22) 102 #define MCHP_SPIP_SPI_STS_DVB (1u << 23) 103 #define MCHP_SPIP_SPI_STS_RXF_SZ (1u << 24) 104 #define MCHP_SPIP_SPI_STS_TXF_UNF (1u << 25) 105 #define MCHP_SPIP_SPI_STS_TXF_OVF (1u << 26) 106 #define MCHP_SPIP_SPI_STS_RXF_UNF (1u << 27) 107 #define MCHP_SPIP_SPI_STS_RXF_OVF (1u << 28) 108 109 /* SPIP EC Status register */ 110 #define MCHP_SPIP_EC_STS_REG_OFS 8 111 #define MCHP_SPIP_EC_STS_REG_MASK 0x1fffef7bu 112 #define MCHP_SPIP_EC_STS_MWD (1u << 0) 113 #define MCHP_SPIP_EC_STS_MRD (1u << 1) 114 #define MCHP_SPIP_EC_STS_MWB (1u << 3) 115 #define MCHP_SPIP_EC_STS_MRB (1u << 4) 116 #define MCHP_SPIP_EC_STS_SRTB (1u << 5) 117 #define MCHP_SPIP_EC_STS_PHI_REQ (1u << 6) 118 #define MCHP_SPIP_EC_STS_RXFE (1u << 8) 119 #define MCHP_SPIP_EC_STS_RXFF (1u << 9) 120 #define MCHP_SPIP_EC_STS_TXFE (1u << 10) 121 #define MCHP_SPIP_EC_STS_TXFF (1u << 11) 122 #define MCHP_SPIP_EC_STS_SCCE (1u << 13) 123 #define MCHP_SPIP_EC_STS_IBF (1u << 14) 124 #define MCHP_SPIP_EC_STS_OBF (1u << 15) 125 #define MCHP_SPIP_EC_STS_SPIMR (1u << 16) 126 #define MCHP_SPIP_EC_STS_RXF_RSTD (1u << 17) 127 #define MCHP_SPIP_EC_STS_TXF_RSTD (1u << 18) 128 #define MCHP_SPIP_EC_STS_LIM0 (1u << 19) 129 #define MCHP_SPIP_EC_STS_LIM1 (1u << 20) 130 #define MCHP_SPIP_EC_STS_ABERR (1u << 21) 131 #define MCHP_SPIP_EC_STS_UNDEF_CMD (1u << 22) 132 #define MCHP_SPIP_EC_STS_DVB (1u << 23) 133 #define MCHP_SPIP_EC_STS_RXF_SZ (1u << 24) 134 #define MCHP_SPIP_EC_STS_TXF_UNF (1u << 25) 135 #define MCHP_SPIP_EC_STS_TXF_OVF (1u << 26) 136 #define MCHP_SPIP_EC_STS_RXF_UNF (1u << 27) 137 #define MCHP_SPIP_EC_STS_RXF_OVF (1u << 28) 138 139 /* SPIP SPI Interrupt Enable register */ 140 #define MCHP_SPIP_SPI_IEN_REG_OFS 0x0c 141 #define MCHP_SPIP_SPI_IEN_REG_MASK 0x1fffaf7au 142 #define MCHP_SPIP_SPI_IEN_MWD (1u << 0) 143 #define MCHP_SPIP_SPI_IEN_MRD (1u << 1) 144 #define MCHP_SPIP_SPI_IEN_MWB (1u << 3) 145 #define MCHP_SPIP_SPI_IEN_MRB (1u << 4) 146 #define MCHP_SPIP_SPI_IEN_SRTB (1u << 5) 147 #define MCHP_SPIP_SPI_IEN_PHI_REQ (1u << 6) 148 #define MCHP_SPIP_SPI_IEN_RXFE (1u << 8) 149 #define MCHP_SPIP_SPI_IEN_RXFF (1u << 9) 150 #define MCHP_SPIP_SPI_IEN_TXFE (1u << 10) 151 #define MCHP_SPIP_SPI_IEN_TXFF (1u << 11) 152 #define MCHP_SPIP_SPI_IEN_SCCE (1u << 13) 153 #define MCHP_SPIP_SPI_IEN_OBF (1u << 15) 154 #define MCHP_SPIP_SPI_IEN_SPIMR (1u << 16) 155 #define MCHP_SPIP_SPI_IEN_RXF_RSTD (1u << 17) 156 #define MCHP_SPIP_SPI_IEN_TXF_RSTD (1u << 18) 157 #define MCHP_SPIP_SPI_IEN_LIM0 (1u << 19) 158 #define MCHP_SPIP_SPI_IEN_LIM1 (1u << 20) 159 #define MCHP_SPIP_SPI_IEN_ABERR (1u << 21) 160 #define MCHP_SPIP_SPI_IEN_UNDEF_CMD (1u << 22) 161 #define MCHP_SPIP_SPI_IEN_DVB (1u << 23) 162 #define MCHP_SPIP_SPI_IEN_RXF_SZ (1u << 24) 163 #define MCHP_SPIP_SPI_IEN_TXF_UNF (1u << 25) 164 #define MCHP_SPIP_SPI_IEN_TXF_OVF (1u << 26) 165 #define MCHP_SPIP_SPI_IEN_RXF_UNF (1u << 27) 166 #define MCHP_SPIP_SPI_IEN_RXF_OVF (1u << 28) 167 168 /* SPIP EC Interrupt Enable register */ 169 #define MCHP_SPIP_EC_IEN_REG_OFS 0x10 170 #define MCHP_SPIP_EC_IEN_REG_MASK 0x1fffef7bu 171 #define MCHP_SPIP_EC_IEN_MWD (1u << 0) 172 #define MCHP_SPIP_EC_IEN_MRD (1u << 1) 173 #define MCHP_SPIP_EC_IEN_MWB (1u << 3) 174 #define MCHP_SPIP_EC_IEN_MRB (1u << 4) 175 #define MCHP_SPIP_EC_IEN_SRTB (1u << 5) 176 #define MCHP_SPIP_EC_IEN_PHI_REQ (1u << 6) 177 #define MCHP_SPIP_EC_IEN_RXFE (1u << 8) 178 #define MCHP_SPIP_EC_IEN_RXFF (1u << 9) 179 #define MCHP_SPIP_EC_IEN_TXFE (1u << 10) 180 #define MCHP_SPIP_EC_IEN_TXFF (1u << 11) 181 #define MCHP_SPIP_EC_IEN_SCCE (1u << 13) 182 #define MCHP_SPIP_EC_IEN_IBF (1u << 14) 183 #define MCHP_SPIP_EC_IEN_OBF (1u << 15) 184 #define MCHP_SPIP_EC_IEN_SPIMR (1u << 16) 185 #define MCHP_SPIP_EC_IEN_RXF_RSTD (1u << 17) 186 #define MCHP_SPIP_EC_IEN_TXF_RSTD (1u << 18) 187 #define MCHP_SPIP_EC_IEN_LIM0 (1u << 19) 188 #define MCHP_SPIP_EC_IEN_LIM1 (1u << 20) 189 #define MCHP_SPIP_EC_IEN_ABERR (1u << 21) 190 #define MCHP_SPIP_EC_IEN_UNDEF_CMD (1u << 22) 191 #define MCHP_SPIP_EC_IEN_DVB (1u << 23) 192 #define MCHP_SPIP_EC_IEN_RXF_SZ (1u << 24) 193 #define MCHP_SPIP_EC_IEN_TXF_UNF (1u << 25) 194 #define MCHP_SPIP_EC_IEN_TXF_OVF (1u << 26) 195 #define MCHP_SPIP_EC_IEN_RXF_UNF (1u << 27) 196 #define MCHP_SPIP_EC_IEN_RXF_OVF (1u << 28) 197 198 /* SPIP Memory Config register */ 199 #define MCHP_SPIP_MCFG_REG_OFS 0x14 200 #define MCHP_SPIP_MCFG_REG_MASK 0x03u 201 #define MCHP_SPIP_MCFG_BAR0_EN_POS 0 202 #define MCHP_SPIP_MCFG_BAR0_EN (1u << 0) 203 #define MCHP_SPIP_MCFG_BAR1_EN_POS 1 204 #define MCHP_SPIP_MCFG_BAR1_EN (1u << 1) 205 206 /* SPIP Memory Base Address 0 register */ 207 #define MCHP_SPIP_MBA0_REG_OFS 0x18 208 #define MCHP_SPIP_MBA0_REG_MASK 0xfffffffcu 209 210 /* SPIP Memory Write Limit 0 register */ 211 #define MCHP_SPIP_MWLIM0_REG_OFS 0x1c 212 #define MCHP_SPIP_MWLIM0_REG_MASK 0xfffffffcu 213 214 /* SPIP Memory Read Limit 0 register */ 215 #define MCHP_SPIP_MRLIM0_REG_OFS 0x20 216 #define MCHP_SPIP_MRLIM0_REG_MASK 0xfffffffcu 217 218 /* SPIP Memory Base Address 1 register */ 219 #define MCHP_SPIP_MBA1_REG_OFS 0x24 220 #define MCHP_SPIP_MBA1_REG_MASK 0xfffffffcu 221 222 /* SPIP Memory Write Limit 1 register */ 223 #define MCHP_SPIP_MWLIM1_REG_OFS 0x28 224 #define MCHP_SPIP_MWLIM1_REG_MASK 0xfffffffcu 225 226 /* SPIP Memory Read Limit 1 register */ 227 #define MCHP_SPIP_MRLIM1_REG_OFS 0x2c 228 #define MCHP_SPIP_MRLIM1_REG_MASK 0xfffffffcu 229 230 /* SPIP RX FIFO Host BAR register */ 231 #define MCHP_SPIP_RXFHB_REG_OFS 0x30 232 #define MCHP_SPIP_RXFHB_REG_MASK 0xffffu 233 234 /* SPIP RX FIFO Host BAR register */ 235 #define MCHP_SPIP_RXFBC_REG_OFS 0x34 236 #define MCHP_SPIP_RXFBC_REG_MASK 0x7fffu 237 238 /* SPIP TX FIFO Host BAR register */ 239 #define MCHP_SPIP_TXFHB_REG_OFS 0x38 240 #define MCHP_SPIP_TXFHB_REG_MASK 0xffffu 241 242 /* SPIP TX FIFO Host BAR register */ 243 #define MCHP_SPIP_TXFBC_REG_OFS 0x3c 244 #define MCHP_SPIP_TXFBC_REG_MASK 0x7fffu 245 246 /* SPIP System Configuration register */ 247 #define MCHP_SPIP_SYSCFG_REG_OFS 0x40 248 #define MCHP_SPIP_SYSCFG_REG_MASK 0x000f04ffu 249 #define MCHP_SPIP_SYSCFG_SRST (1u << 0) 250 #define MCHP_SPIP_SYSCFG_LOCK_WM (1u << 1) 251 #define MCHP_SPIP_SYSCFG_LOCK_TAR (1u << 2) 252 #define MCHP_SPIP_SYSCFG_LOCK_WC (1u << 3) 253 #define MCHP_SPIP_SYSCFG_LOCK_SPI_STS (1u << 4) 254 #define MCHP_SPIP_SYSCFG_LOCK_SPI_IEN (1u << 5) 255 #define MCHP_SPIP_SYSCFG_LOCK_MBA0 (1u << 6) 256 #define MCHP_SPIP_SYSCFG_LOCK_MBA1 (1u << 7) 257 #define MCHP_SPIP_SYSCFG_LOCK_TST (1u << 10) 258 #define MCHP_SPIP_SYSCFG_LOCK_ALL 0x04feu 259 #define MCHP_SPIP_SYSCFG_ACT (1u << 16) 260 #define MCHP_SPIP_SYSCFG_MASK_EC (1u << 17) 261 #define MCHP_SPIP_SYSCFG_SIMPLE_MODE (1u << 18) 262 #define MCHP_SPIP_SYSCFG_ECDA (1u << 19) 263 264 /* SPIP SPI Master to EC Mailbox register */ 265 #define MCHP_SPIP_MB_S2EC_REG_OFS 0x44 266 #define MCHP_SPIP_MB_S2EC_REG_MASK 0xffffffffu 267 #define MCHP_SPIP_MB_S2EC_CLR 0xffffffffu 268 269 /* SPIP EC to SPI Master Mailbox register */ 270 #define MCHP_SPIP_MB_EC2S_REG_OFS 0x48 271 #define MCHP_SPIP_MB_EC2S_REG_MASK 0xffffffffu 272 #define MCHP_SPIP_MB_EC2S_CLR 0xffffffffu 273 274 /* SPI commands supported by SPIP */ 275 #define SPIP_CMD_IN_BAND_RST 0xffu 276 #define SPIP_CMD_UNDEF_W32 0x01u 277 #define SPIP_CMD_UNDEF_W8 0x02u 278 #define SPIP_CMD_UNDEF_R32 0x05u 279 #define SPIP_CMD_UNDEF_R8 0x06u 280 #define SPIP_CMD_SREG_W8 0x09u 281 #define SPIP_CMD_SREG_W16 0x0au 282 #define SPIP_CMD_SREG_W32 0x0bu 283 #define SPIP_CMD_SREG_R8 0x0du 284 #define SPIP_CMD_SREG_R16 0x0eu 285 #define SPIP_CMD_SREG_R32 0x0fu 286 #define SPIP_CMD_RST_RX_FIFO 0x12u 287 #define SPIP_CMD_RST_TX_FIFO 0x14u 288 #define SPIP_CMD_RST_RXTX_FIFO 0x16u 289 #define SPIP_CMD_MEM_W8 0x21u 290 #define SPIP_CMD_MEM_W16 0x22u 291 #define SPIP_CMD_MEM_W32 0x23u 292 #define SPIP_CMD_MEM_R8 0x25u 293 #define SPIP_CMD_MEM_R16 0x26u 294 #define SPIP_CMD_MEM_R32 0x27u 295 #define SPIP_CMD_RS_FIFO8 0x28u 296 #define SPIP_CMD_RS_FIFO16 0x29u 297 #define SPIP_CMD_RS_FIFO32 0x2bu 298 #define SPIP_CMD_POLL_LO 0x2cu 299 #define SPIP_CMD_POLL_HI 0x2du 300 #define SPIP_CMD_POLL_ALL 0x2fu 301 #define SPIP_CMD_EXT_REG_W8 0x41u 302 #define SPIP_CMD_EXT_REG_R8 0x45u 303 #define SPIP_CMD_RS_FIFO8_FSR 0x68u 304 #define SPIP_CMD_RS_FIFO16_FSR 0x69u 305 #define SPIP_CMD_RS_FIFO32_FSR 0x6bu 306 #define SPIP_CMD_EXT_END 0x6cu 307 #define SPIP_CMD_MBLK_W 0x80u 308 #define SPIP_CMD_MBLK_R 0xa0u 309 #define SPIP_CMD_RD_BLK_FIFO 0xc0u 310 #define SPIP_CMD_RD_BLK_FIFO_FSR 0xe0u 311 312 /** @brief SPI Slave registers (SPIP) */ 313 typedef struct spip_regs { 314 __IOM uint32_t CONFIG; /*!< (@ 0x0000) SPIP Control */ 315 __IOM uint32_t SPI_STATUS; /*!< (@ 0x0004) SPIP Host Status */ 316 __IOM uint32_t EC_STATUS; /*!< (@ 0x0008) SPIP EC Status */ 317 __IOM uint32_t SPI_INT_EN; /*!< (@ 0x000c) SPIP SPI Interrupt Enable */ 318 __IOM uint32_t EC_INT_EN; /*!< (@ 0x0010) SPIP EC Interrupt Enable */ 319 __IOM uint32_t MCONFIG; /*!< (@ 0x0014) SPIP Memory Config */ 320 __IOM uint32_t MBA0; /*!< (@ 0x0018) SPIP Memory Base Address 0 */ 321 __IOM uint32_t MBA0_WLIM; /*!< (@ 0x001c) SPIP Memory Base Address 0 Write Limit */ 322 __IOM uint32_t MBA0_RLIM; /*!< (@ 0x0020) SPIP Memory Base Address 0 Read Limit */ 323 __IOM uint32_t MBA1; /*!< (@ 0x0024) SPIP Memory Base Address 1 */ 324 __IOM uint32_t MBA1_WLIM; /*!< (@ 0x0028) SPIP Memory Base Address 0 Write Limit */ 325 __IOM uint32_t MBA1_RLIM; /*!< (@ 0x002c) SPIP Memory Base Address 0 Read Limit */ 326 __IOM uint32_t RXF_HBAR; /*!< (@ 0x0030) SPIP RX FIFO Host BAR */ 327 __IOM uint32_t RXF_BCNT; /*!< (@ 0x0034) SPIP RX FIFO Byte Counter */ 328 __IOM uint32_t TXF_HBAR; /*!< (@ 0x0038) SPIP RX FIFO Host BAR */ 329 __IOM uint32_t TXF_BCNT; /*!< (@ 0x003c) SPIP TX FIFO Byte Counter */ 330 __IOM uint32_t SYS_CONFIG; /*!< (@ 0x0040) SPIP System Config */ 331 __IOM uint32_t MBOX_S2EC; /*!< (@ 0x0044) SPIP SPI Host to EC Mailbox */ 332 __IOM uint32_t MBOX_EC2S; /*!< (@ 0x0048) SPIP EC to SPI Host Mailbox */ 333 } SPIP_Type; 334 335 #endif /* #ifndef _SPI_PERIPH_H */ 336 /* end spi_periph.h */ 337 /** @} 338 */ 339
