1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file qmspi.h 28 *MEC1501 Quad Master SPI Registers 29 */ 30 /** @defgroup MEC1501 Peripherals QMSPI 31 */ 32 33 #ifndef _QMSPI_H_ 34 #define _QMSPI_H_ 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 #define QMPSPI_HW_VER 3u 42 43 #define MCHP_QMSPI_BASE_ADDR 0x40070000u 44 45 #define MCHP_QMSPI_MAX_DESCR 16u 46 47 #define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 48000000u 48 #define MCHP_QMSPI_MAX_FREQ_KHZ ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000u) 49 #define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256u) 50 51 #define MCHP_QMSPI_GIRQ_NUM 18u 52 #define MCHP_QMSPI_GIRQ_POS 1u 53 #define MCHP_QMSPI_GIRQ_VAL BIT(MCHP_QMSPI_GIRQ_POS) 54 #define MCHP_QMSPI_GIRQ_OFS (((MCHP_QMSPI0_GIRQ_NUM) - 8) * 20u) 55 56 #define MCHP_QMSPI_GIRQ_NVIC_AGGR 10u 57 #define MCHP_QMSPI_GIRQ_NVIC_DIRECT 91u 58 59 #define MCHP_QMSPI_GIRQ_BASE_ADDR 0x4000e0c8u 60 #define MCHP_QMSPI_GIRQ_SRC_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR) 61 #define MCHP_QMSPI_GIRQ_ENSET_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x04u) 62 #define MCHP_QMSPI_GIRQ_RESULT_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x08u) 63 #define MCHP_QMSPI_GIRQ_ENCLR_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x0cu) 64 65 /* Sleep Enable 4 bit 8 */ 66 #define MCHP_QMSPI_PCR_SLP_EN_ADDR 0x40080140u 67 #define MCHP_QMSPI_PCR_SLP_EN_POS 8u 68 69 #define MCHP_QMSPI_GIRQ_EN (1u << (MCHP_QMSPI_GIRQ_POS)) 70 #define MCHP_QMSPI_GIRQ_STS (1u << (MCHP_QMSPI_GIRQ_POS)) 71 72 /* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */ 73 #define MCHP_QMSPI_SPI_MODE0 0u 74 /* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */ 75 #define MCHP_QMSPI_SPI_MODE1 0x06u 76 /* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */ 77 #define MCHP_QMSPI_SPI_MODE2 0x06u 78 /* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */ 79 #define MCHP_QMSPI_SPI_MODE3 0x07u 80 81 /* Device ID used in DMA channel Control.DeviceID field */ 82 #define MCHP_QMSPI_TX_DMA_REQ_ID 10u 83 #define MCHP_QMSPI_RX_DMA_REQ_ID 11u 84 85 /* QMSPI transmit and receive FIFO lengths */ 86 #define MCHP_QMSPI_TX_FIFO_LEN 8u 87 #define MCHP_QMSPI_RX_FIFO_LEN 8u 88 89 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u 90 #define MCHP_QMSPI_M_SPI_MODE_OFS 1u 91 #define MCHP_QMSPI_M_CLK_DIV_OFS 2u 92 #define MCHP_QMSPI_CTRL_OFS 4u 93 #define MCHP_QMSPI_EXE_OFS 8u 94 #define MCHP_QMSPI_IF_CTRL_OFS 0x0cu 95 #define MCHP_QMSPI_STS_OFS 0x10u 96 #define MCHP_QMSPI_BUF_CNT_STS_OFS 0x14u 97 #define MCHP_QMSPI_IEN_OFS 0x18u 98 #define MCHP_QMSPI_BUF_CNT_TRIG_OFS 0x1cu 99 #define MCHP_QMSPI_TX_FIFO_OFS 0x20u 100 #define MCHP_QMSPI_RX_FIFO_OFS 0x24u 101 #define MCHP_QMSPI_CSTM_OFS 0x28u 102 /* 0 <= n < MCHP_QMSPI_MAX_DESCR */ 103 #define MCHP_QMSPI_DESCR_OFS(n) (0x30u + ((uint32_t)(n) * 4U)) 104 #define MCHP_QMSPI_DESC0_OFS 0x30u 105 106 #define MCHP_QMSPI_MODE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x00) 107 #define MCHP_QMSPI_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x04) 108 #define MCHP_QMSPI_EXE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x08) 109 #define MCHP_QMSPI_IFC_ADDR (MCHP_QMSPI_BASE_ADDR + 0x0c) 110 #define MCHP_QMSPI_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x10) 111 #define MCHP_QMSPI_BUFCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) 112 #define MCHP_QMSPI_TX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) 113 #define MCHP_QMSPI_RX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x16) 114 #define MCHP_QMSPI_IEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x18) 115 #define MCHP_QMSPI_TXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x20) 116 #define MCHP_QMSPI_RXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x24) 117 #define MCHP_QMSPI_CSTM_ADDR (MCHP_QMSPI_BASE_ADDR + 0x28) 118 #define MCHP_QMSPI_DESCR_ADDR(n) \ 119 (MCHP_QMSPI_BASE_ADDR + (0x30 + (((uint32_t)(n) & 0x0fu) << 2))) 120 121 /* Mode Register */ 122 #define MCHP_QMSPI_M_ACTIVATE BIT(0) 123 #define MCHP_QMSPI_M_SRST BIT(1) 124 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2) 125 #define MCHP_QMSPI_M_CPOL_POS 8u 126 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_LO 0 127 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8) 128 129 #define MCHP_QMSPI_M_CPHA_MOSI_POS 9u 130 /* MOSI data changes on first clock edge of clock pulse */ 131 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 (0u << 9) 132 /* MOSI data changes on second clock edge of clock pulse */ 133 #define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9) 134 135 #define MCHP_QMSPI_M_CPHA_MIS0_POS 10u 136 /* MISO data capture on first clock edge of clock pulse */ 137 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u 138 /* MISO data capture on second clock edge of clock pulse */ 139 #define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10) 140 141 #define MCHP_QMSPI_M_SIG_POS 8u 142 #define MCHP_QMSPI_M_SIG_MASK0 0x07u 143 #define MCHP_QMSPI_M_SIG_MASK 0x0700u 144 #define MCHP_QMSPI_M_SIG_MODE0_VAL 0x00u 145 #define MCHP_QMSPI_M_SIG_MODE1_VAL 0x06u 146 #define MCHP_QMSPI_M_SIG_MODE2_VAL 0x01u 147 #define MCHP_QMSPI_M_SIG_MODE3_VAL 0x07u 148 #define MCHP_QMSPI_M_SIG_MODE0 0x00u 149 #define MCHP_QMSPI_M_SIG_MODE1 (0x06u << MCHP_QMSPI_M_SIG_POS) 150 #define MCHP_QMSPI_M_SIG_MODE2 (0x01u << MCHP_QMSPI_M_SIG_POS) 151 #define MCHP_QMSPI_M_SIG_MODE3 (0x07u << MCHP_QMSPI_M_SIG_POS) 152 #define MCHP_QMSPI_M_CS_POS 12u 153 #define MCHP_QMSPI_M_CS_MASK0 0x03u 154 #define MCHP_QMSPI_M_CS_MASK (0x03u << 12) 155 #define MCHP_QMSPI_M_CS0 (0x00u << 12) 156 #define MCHP_QMSPI_M_CS1 (0x01u << 12) 157 /* Two chip selects only 0 and 1 */ 158 #define MCHP_QMSPI_M_CS(n) \ 159 (((uint32_t)(n) & MCHP_QMSPI_M_CS_MASK0) << MCHP_QMSPI_M_CS_POS) 160 #define MCHP_QMSPI_M_FDIV_POS 16u 161 #define MCHP_QMSPI_M_FDIV_MASK0 0xffu 162 #define MCHP_QMSPI_M_FDIV_MASK 0x00ff0000u 163 164 /* Control/Descriptors */ 165 #define MCHP_QMSPI_C_IFM_MASK 0x03u 166 #define MCHP_QMSPI_C_IFM_1X 0x00u 167 #define MCHP_QMSPI_C_IFM_2X 0x01u 168 #define MCHP_QMSPI_C_IFM_4X 0x02u 169 #define MCHP_QMSPI_C_TX_POS 2u 170 #define MCHP_QMSPI_C_TX_MASK (0x03u << MCHP_QMSPI_C_TX_POS) 171 #define MCHP_QMSPI_C_TX_DIS (0x00u << MCHP_QMSPI_C_TX_POS) 172 #define MCHP_QMSPI_C_TX_DATA (0x01u << MCHP_QMSPI_C_TX_POS) 173 #define MCHP_QMSPI_C_TX_ZEROS (0x02u << MCHP_QMSPI_C_TX_POS) 174 #define MCHP_QMSPI_C_TX_ONES (0x03u << MCHP_QMSPI_C_TX_POS) 175 #define MCHP_QMSPI_C_TX_DMA_POS 4u 176 #define MCHP_QMSPI_C_TX_DMA_MASK (0x03u << MCHP_QMSPI_C_TX_DMA_POS) 177 #define MCHP_QMSPI_C_TX_DMA_DIS (0x00u << MCHP_QMSPI_C_TX_DMA_POS) 178 #define MCHP_QMSPI_C_TX_DMA_1B (0x01u << MCHP_QMSPI_C_TX_DMA_POS) 179 #define MCHP_QMSPI_C_TX_DMA_2B (0x02u << MCHP_QMSPI_C_TX_DMA_POS) 180 #define MCHP_QMSPI_C_TX_DMA_4B (0x03u << MCHP_QMSPI_C_TX_DMA_POS) 181 #define MCHP_QMSPI_C_RX_POS 6u 182 #define MCHP_QMSPI_C_RX_DIS (0u << MCHP_QMSPI_C_RX_POS) 183 #define MCHP_QMSPI_C_RX_EN (1u << MCHP_QMSPI_C_RX_POS) 184 #define MCHP_QMSPI_C_RX_DMA_POS 7u 185 #define MCHP_QMSPI_C_RX_DMA_MASK (0x03u << MCHP_QMSPI_C_RX_DMA_POS) 186 #define MCHP_QMSPI_C_RX_DMA_DIS (0x00u << MCHP_QMSPI_C_RX_DMA_POS) 187 #define MCHP_QMSPI_C_RX_DMA_1B (0x01u << MCHP_QMSPI_C_RX_DMA_POS) 188 #define MCHP_QMSPI_C_RX_DMA_2B (0x02u << MCHP_QMSPI_C_RX_DMA_POS) 189 #define MCHP_QMSPI_C_RX_DMA_4B (0x03u << MCHP_QMSPI_C_RX_DMA_POS) 190 #define MCHP_QMSPI_C_CLOSE_POS 9u 191 #define MCHP_QMSPI_C_NO_CLOSE (0u << MCHP_QMSPI_C_CLOSE_POS) 192 #define MCHP_QMSPI_C_CLOSE (1u << MCHP_QMSPI_C_CLOSE_POS) 193 #define MCHP_QMSPI_C_XFR_UNITS_POS 10u 194 #define MCHP_QMSPI_C_XFR_UNITS_MASK (0x03u << MCHP_QMSPI_C_XFR_UNITS_POS) 195 #define MCHP_QMSPI_C_XFR_UNITS_BITS (0x00u << MCHP_QMSPI_C_XFR_UNITS_POS) 196 #define MCHP_QMSPI_C_XFR_UNITS_1 (0x01u << MCHP_QMSPI_C_XFR_UNITS_POS) 197 #define MCHP_QMSPI_C_XFR_UNITS_4 (0x02u << MCHP_QMSPI_C_XFR_UNITS_POS) 198 #define MCHP_QMSPI_C_XFR_UNITS_16 (0x03u << MCHP_QMSPI_C_XFR_UNITS_POS) 199 #define MCHP_QMSPI_C_NEXT_DESCR_POS 12u 200 #define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0x0fu 201 #define MCHP_QMSPI_C_NEXT_DESCR_MASK (MCHP_QMSPI_C_NEXT_DESCR_MASK0 << \ 202 MCHP_QMSPI_C_NEXT_DESCR_POS) 203 #define MCHP_QMSPI_C_DESCR0 (0u << MCHP_QMSPI_C_NEXT_DESCR_POS) 204 #define MCHP_QMSPI_C_DESCR1 (1u << MCHP_QMSPI_C_NEXT_DESCR_POS) 205 #define MCHP_QMSPI_C_DESCR2 (2u << MCHP_QMSPI_C_NEXT_DESCR_POS) 206 #define MCHP_QMSPI_C_DESCR3 (3u << MCHP_QMSPI_C_NEXT_DESCR_POS) 207 #define MCHP_QMSPI_C_DESCR4 (4u << MCHP_QMSPI_C_NEXT_DESCR_POS) 208 /* Control register start descriptor field */ 209 #define MCHP_QMSPI_C_DESCR(n) (((uint32_t)(n) & \ 210 MCHP_QMSPI_C_NEXT_DESCR_MASK0) << \ 211 MCHP_QMSPI_C_NEXT_DESCR_POS) 212 /* Descriptor registers next descriptor field */ 213 #define MCHP_QMSPI_C_NEXT_DESCR(n) (((uint32_t)(n) & \ 214 MCHP_QMSPI_C_NEXT_DESCR_MASK0) << \ 215 MCHP_QMSPI_C_NEXT_DESCR_POS) 216 /* Control register descriptor mode enable */ 217 #define MCHP_QMSPI_C_DESCR_EN_POS 16u 218 #define MCHP_QMSPI_C_DESCR_EN (1u << MCHP_QMSPI_C_DESCR_EN_POS) 219 /* Descriptor registers last descriptor flag */ 220 #define MCHP_QMSPI_C_DESCR_LAST (1u << MCHP_QMSPI_C_DESCR_EN_POS) 221 #define MCHP_QMSPI_C_MAX_UNITS 0x7fffu 222 #define MCHP_QMSPI_C_MAX_UNITS_MASK 0x7fffu 223 #define MCHP_QMSPI_C_XFR_NUNITS_POS 17u 224 #define MCHP_QMSPI_C_XFR_NUNITS_MASK0 0x7fffu 225 #define MCHP_QMSPI_C_XFR_NUNITS_MASK (MCHP_QMSPI_C_XFR_NUNITS_MASK0 << \ 226 MCHP_QMSPI_C_XFR_NUNITS_POS) 227 #define MCHP_QMSPI_C_XFR_NUNITS(n) ((uint32_t)(n) << \ 228 MCHP_QMSPI_C_XFR_NUNITS_POS) 229 #define MCHP_QMSPI_C_XFR_NUNITS_GET(n) (((uint32_t)(n) >> \ 230 MCHP_QMSPI_C_XFR_NUNITS_POS) & \ 231 MCHP_QMSPI_C_MAX_UNITS_MASK) 232 233 /* Exe */ 234 #define MCHP_QMSPI_EXE_START 0x01u 235 #define MCHP_QMSPI_EXE_STOP 0x02u 236 #define MCHP_QMSPI_EXE_CLR_FIFOS 0x04u 237 238 /* Interface Control */ 239 #define MCHP_QMSPI_IFC_DFLT 0x00u 240 #define MCHP_QMSPI_IFC_WP_OUT_HI BIT(0) 241 #define MCHP_QMSPI_IFC_WP_OUT_EN BIT(1) 242 #define MCHP_QMSPI_IFC_HOLD_OUT_HI BIT(2) 243 #define MCHP_QMSPI_IFC_HOLD_OUT_EN BIT(3) 244 #define MCHP_QMSPI_IFC_PD_ON_NS BIT(4) 245 #define MCHP_QMSPI_IFC_PU_ON_NS BIT(5) 246 #define MCHP_QMSPI_IFC_PD_ON_ND BIT(6) 247 #define MCHP_QMSPI_IFC_PU_ON_ND BIT(7) 248 249 /* Status Register */ 250 #define MCHP_QMSPI_STS_REG_MASK 0x0f01ff1fu 251 #define MCHP_QMSPI_STS_RO_MASK 0x0f013300u 252 #define MCHP_QMSPI_STS_RW1C_MASK 0x0000cc1fu 253 #define MCHP_QMSPI_STS_DONE BIT(0) 254 #define MCHP_QMSPI_STS_DMA_DONE BIT(1) 255 #define MCHP_QMSPI_STS_TXB_ERR BIT(2) 256 #define MCHP_QMSPI_STS_RXB_ERR BIT(3) 257 #define MCHP_QMSPI_STS_PROG_ERR BIT(4) 258 #define MCHP_QMSPI_STS_TXBF_RO BIT(8) 259 #define MCHP_QMSPI_STS_TXBE_RO BIT(9) 260 #define MCHP_QMSPI_STS_TXBR BIT(10) 261 #define MCHP_QMSPI_STS_TXBS BIT(11) 262 #define MCHP_QMSPI_STS_RXBF_RO BIT(12) 263 #define MCHP_QMSPI_STS_RXBE_RO BIT(13) 264 #define MCHP_QMSPI_STS_RXBR BIT(14) 265 #define MCHP_QMSPI_STS_RXBS BIT(15) 266 #define MCHP_QMSPI_STS_ACTIVE_RO BIT(16) 267 #define MCHP_QMSPI_STS_CD_POS 24u 268 #define MCHP_QMSPI_STS_CD_MASK0 0x0fu 269 #define MCHP_QMSPI_STS_CD_MASK (MCHP_QMSPI_STS_CD_MASK0 << \ 270 MCHP_QMSPI_STS_CD_POS) 271 272 /* Buffer Count Status (RO) */ 273 #define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u 274 #define MCHP_QMSPI_TX_BUF_CNT_STS_MASK 0xffffu 275 #define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u 276 #define MCHP_QMSPI_RX_BUF_CNT_STS_MASK 0xffff0000u 277 278 /* Interrupt Enable Register */ 279 #define MCHP_QMSPI_IEN_XFR_DONE BIT(0) 280 #define MCHP_QMSPI_IEN_DMA_DONE BIT(1) 281 #define MCHP_QMSPI_IEN_TXB_ERR BIT(2) 282 #define MCHP_QMSPI_IEN_RXB_ERR BIT(3) 283 #define MCHP_QMSPI_IEN_PROG_ERR BIT(4) 284 #define MCHP_QMSPI_IEN_TXB_FULL BIT(8) 285 #define MCHP_QMSPI_IEN_TXB_EMPTY BIT(9) 286 #define MCHP_QMSPI_IEN_TXB_REQ BIT(10) 287 #define MCHP_QMSPI_IEN_RXB_FULL BIT(12) 288 #define MCHP_QMSPI_IEN_RXB_EMPTY BIT(13) 289 #define MCHP_QMSPI_IEN_RXB_REQ BIT(14) 290 291 /* Buffer Count Trigger (RW) */ 292 #define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u 293 #define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u 294 295 /* Chip Select Timing (RW) */ 296 #define MCHP_QMSPI_CSTM_MASK 0xff0f0f0fu 297 #define MCHP_QMSPI_CSTM_DFLT 0x06060406u 298 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u 299 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_MASK 0x0fu 300 #define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u 301 #define MCHP_QMSPI_DLY_CK_STP_CS_OFF_MASK (0x0fu << \ 302 MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS) 303 #define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u 304 #define MCHP_QMSPI_DLY_LST_DAT_HLD_MASK (0x0fu << \ 305 MCHP_QMSPI_DLY_LST_DAT_HLD_POS) 306 #define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u 307 #define MCHP_QMSPI_DLY_CS_OFF_CS_ON_MASK (0x0fu << \ 308 MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS) 309 310 #define MCHP_QMSPI_PORT_MAX_IO_PINS 4u 311 #define MCHP_QMSPI_PORT_MAX_CS 2u 312 313 /* Full duplex and Dual I/O: 314 * CS#, CLK, IO0(MOSI), IO1(MISO) 315 * do not connect IO2(WP#) or IO3(HOLD#) to MCHP_QMSPI. 316 */ 317 #define MCHP_QMSPI_PORT_MASK_FULL_DUPLEX 0x0fu 318 #define MCHP_QMSPI_PORT_MASK_DUAL 0x0fu 319 320 #define MCHP_QMSPI_PIN_IO0_POS 0u 321 #define MCHP_QMSPI_PIN_IO1_POS 1u 322 #define MCHP_QMSPI_PIN_IO2_POS 2u 323 #define MCHP_QMSPI_PIN_IO3_POS 3u 324 #define MCHP_QMSPI_PIN_CLK_POS 4u 325 #define MCHP_QMSPI_PIN_CS0_POS 8u 326 #define MCHP_QMSPI_PIN_CS1_POS 9u 327 328 #define MCHP_QMSPI_PIN_IO0 (1u << MCHP_QMSPI_PIN_IO0_POS) 329 #define MCHP_QMSPI_PIN_IO1 (1u << MCHP_QMSPI_PIN_IO1_POS) 330 #define MCHP_QMSPI_PIN_IO2 (1u << MCHP_QMSPI_PIN_IO2_POS) 331 #define MCHP_QMSPI_PIN_IO3 (1u << MCHP_QMSPI_PIN_IO3_POS) 332 #define MCHP_QMSPI_PIN_CLK (1u << MCHP_QMSPI_PIN_CLK_POS) 333 #define MCHP_QMSPI_PIN_CS0 (1u << MCHP_QMSPI_PIN_CS0_POS) 334 #define MCHP_QMSPI_PIN_CS1 (1u << MCHP_QMSPI_PIN_CS1_POS) 335 336 /* 337 * Register Access 338 */ 339 #define MCHP_QMSPI_MODE() REG32(MCHP_QMSPI_MODE_ADDR) 340 #define MCHP_QMSPI_MODE_ACTRST() REG8(MCHP_QMSPI_MODE_ADDR) 341 #define MCHP_QMSPI_MODE_SIG() REG8(MCHP_QMSPI_MODE_ADDR + 1u) 342 #define MCHP_QMSPI_MODE_FDIV() REG16(MCHP_QMSPI_MODE_ADDR + 2u) 343 344 /* Control register */ 345 #define MCHP_QMSPI_CTRL() REG32(MCHP_QMSPI_CTRL_ADDR) 346 347 /* Execute register */ 348 #define MCHP_QMSPI_EXE() REG8(MCHP_QMSPI_EXE_ADDR) 349 350 /* Interface Control register */ 351 #define MCHP_QMSPI_IFC() REG8(MCHP_QMSPI_IFC_ADDR) 352 353 /* Status register */ 354 #define MCHP_QMSPI_STS() REG32(MCHP_QMSPI_STS_ADDR) 355 356 /* Buffer Count Status register (read-only) */ 357 #define MCHP_QMSPI_BCNT_STS() REG32(MCHP_QMSPI_BUFCNT_STS_ADDR) 358 /* b[15:0] = TX buffer count */ 359 #define MCHP_QMSPI_BCNT_TX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR) 360 /* b[31:15] = RX buffer count */ 361 #define MCHP_QMSPI_BCNT_RX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR + 2u) 362 363 /* Interrupt Enable register */ 364 #define MCHP_QMSPI_IEN() REG32(MCHP_QMSPI_IEN_ADDR) 365 366 /* TX FIFO write-only */ 367 #define MCHP_QMSPI_TXB_32() REG32(MCHP_QMSPI_TXB_ADDR) 368 #define MCHP_QMSPI_TXB_16() REG16(MCHP_QMSPI_TXB_ADDR) 369 #define MCHP_QMSPI_TXB_8() REG8(MCHP_QMSPI_TXB_ADDR) 370 371 /* RX FIFO read-only */ 372 #define MCHP_QMSPI_RXB_32() REG32(MCHP_QMSPI_RXB_ADDR) 373 #define MCHP_QMSPI_RXB_16() REG16(MCHP_QMSPI_RXB_ADDR) 374 #define MCHP_QMSPI_RXB_8() REG8(MCHP_QMSPI_RXB_ADDR) 375 376 /* 377 * Descriptor registers 378 * 0 <= id < MCHP_QMSPI_MAX_DESCR 379 */ 380 #define MCHP_QMSPI_DESCR(id) REG32(MCHP_QMSPI_DESCR_ADDR(id)) 381 382 #define MCHP_QMSPI_DESCR_NUNITS(id, nu) MCHP_QMSPI_DESCR(id) = \ 383 ((MCHP_QMSPI_DESCR(id) & ~(MCHP_QMSPI_C_XFR_NUNITS_MASK)) +\ 384 (((uint32_t)nu & MCHP_QMSPI_C_XFR_NUNITS_MASK0) \ 385 << MCHP_QMSPI_C_XFR_NUNITS_POS)) 386 387 /** 388 * @brief Quad Master SPI (QMSPI) registers 389 * MODE (@ 0x0000) Mode: frequency, chip select, signal sampling 390 * CTRL (@ 0x0004) Control 391 * EXE (@ 0x0008) Execute, write-only 392 * IFCTRL (@ 0x000c) Interface control 393 * STS (@ 0x0010) Status, RW/1C and RO 394 * BCNT_STS (@ 0x0014) Buffer Count Status, RO 395 * IEN (@ 0x0018) Interrupt Enable 396 * BCNT_TRIG (@ 0x001c) Buffer Count Trigger 397 * TX_FIFO (@ 0x0020) Transmit FIFO 398 * RX_FIFO (@ 0x0024) Receive FIFO 399 * CSTM (@ 0x0028) Chip select timing 400 * DESCR[] (@ 0x0030 - 0x006f descriptors) 401 */ 402 typedef struct qmspi_regs { 403 __IOM uint32_t MODE; 404 __IOM uint32_t CTRL; 405 __IOM uint32_t EXE; 406 __IOM uint32_t IFCTRL; 407 __IOM uint32_t STS; 408 __IOM uint32_t BCNT_STS; 409 __IOM uint32_t IEN; 410 __IOM uint32_t BCNT_TRIG; 411 __IOM uint32_t TX_FIFO; 412 __IOM uint32_t RX_FIFO; 413 __IOM uint32_t CSTM; 414 uint8_t RSVD1[4]; 415 __IOM uint32_t DESCR[MCHP_QMSPI_MAX_DESCR]; 416 } QMSPI_Type; 417 418 #endif /* #ifndef _QMSPI_H */ 419 /* end qmspi.h */ 420 /** @} 421 */ 422
