1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file ps2_ctrl.h 28 *MEC1501 PS/2 Controller Registers 29 */ 30 /** @defgroup MEC1501 Peripherals PS/2 31 */ 32 33 #ifndef _PS2_CTRL_H 34 #define _PS2_CTRL_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* ===================================================================*/ 42 /* ================ PS2 ============= */ 43 /* ===================================================================*/ 44 45 #define MCHP_PS2_MAX_INSTANCES 2u 46 #define MCHP_PS2_SPACING 0x40u 47 #define MCHP_PS2_SPACING_PWROF2 6u 48 49 #define MCHP_PS2_0_BASE_ADDR 0x40009000u 50 #define MCHP_PS2_1_BASE_ADDR 0x40009040u 51 52 /* 53 * PS2 interrupts 54 */ 55 #define MCHP_PS2_0_GIRQ 18u 56 #define MCHP_PS2_1_GIRQ 18u 57 #define MCHP_PS2_0_GIRQ_NVIC 10u 58 #define MCHP_PS2_1_GIRQ_NVIC 10u 59 #define MCHP_PS2_0_NVIC_DIRECT 100u 60 #define MCHP_PS2_1_NVIC_DIRECT 101u 61 62 #define MCHP_PS2_0_GIRQ_POS 10u 63 #define MCHP_PS2_1_GIRQ_POS 11u 64 65 #define MCHP_PS2_0_GIRQ_VAL (1u << 10) 66 #define MCHP_PS2_1_GIRQ_VAL (1u << 11) 67 68 /* 69 * PS2 TRX Buffer register 70 * Writes -> Transmit buffer 71 * Read <- Receive buffer 72 */ 73 #define MCHP_PS2_TRX_BUFF_REG_MASK 0xffu 74 75 /* 76 * PS2 Control register 77 */ 78 #define MCHP_PS2_CTRL_REG_MASK 0x3fu 79 80 /* Select Transmit or Receive */ 81 #define MCHP_PS2_CTRL_TR_POS 0 82 #define MCHP_PS2_CTRL_TR_RX (0U << (MCHP_PS2_CTRL_TR_POS)) 83 #define MCHP_PS2_CTRL_TR_TX (1U << (MCHP_PS2_CTRL_TR_POS)) 84 85 /* Enable PS2 state machine */ 86 #define MCHP_PS2_CTRL_EN_POS 1 87 #define MCHP_PS2_CTRL_EN (1U << (MCHP_PS2_CTRL_EN_POS)) 88 89 /* Protocol parity selection */ 90 #define MCHP_PS2_CTRL_PAR_POS 2 91 #define MCHP_PS2_CTRL_PAR_MASK0 0x03u 92 #define MCHP_PS2_CTRL_PAR_MASK ((MCHP_PS2_CTRL_PAR_MASK0) \ 93 << (MCHP_PS2_CTRL_PAR_POS)) 94 #define MCHP_PS2_CTRL_PAR_ODD (0U << (MCHP_PS2_CTRL_PAR_POS)) 95 #define MCHP_PS2_CTRL_PAR_EVEN (1U << (MCHP_PS2_CTRL_PAR_POS)) 96 #define MCHP_PS2_CTRL_PAR_IGNORE (2U << (MCHP_PS2_CTRL_PAR_POS)) 97 #define MCHP_PS2_CTRL_PAR_RSVD (3U << (MCHP_PS2_CTRL_PAR_POS)) 98 99 /* Protocol stop bit selection */ 100 #define MCHP_PS2_CTRL_STOP_POS 4 101 #define MCHP_PS2_CTRL_STOP_MASK0 0x03u 102 #define MCHP_PS2_CTRL_STOP_MASK ((MCHP_PS2_CTRL_STOP_MASK0) \ 103 << (MCHP_PS2_CTRL_STOP_POS)) 104 #define MCHP_PS2_CTRL_STOP_ACT_HI (0U << (MCHP_PS2_CTRL_STOP_POS)) 105 #define MCHP_PS2_CTRL_STOP_ACT_LO (1U << (MCHP_PS2_CTRL_STOP_POS)) 106 #define MCHP_PS2_CTRL_STOP_IGNORE (2U << (MCHP_PS2_CTRL_STOP_POS)) 107 #define MCHP_PS2_CTRL_STOP_RSVD (3U << (MCHP_PS2_CTRL_STOP_POS)) 108 109 /* 110 * PS2 Status register 111 */ 112 #define MCHP_PS2_STATUS_REG_MASK 0xffu 113 #define MCHP_PS2_STATUS_RW1C_MASK 0xaeu 114 #define MCHP_PS2_STATUS_RO_MASK 0x51u 115 /* RX Data Ready(Read-Only) */ 116 #define MCHP_PS2_STATUS_RXD_RDY_POS 0 117 #define MCHP_PS2_STATUS_RXD_RDY (1U << (MCHP_PS2_STATUS_RXD_RDY_POS)) 118 /* RX Timeout(R/W1C) */ 119 #define MCHP_PS2_STATUS_RX_TMOUT_POS 1 120 #define MCHP_PS2_STATUS_RX_TMOUT (1U << (MCHP_PS2_STATUS_RX_TMOUT_POS)) 121 /* Parity Error(R/W1C) */ 122 #define MCHP_PS2_STATUS_PE_POS 2 123 #define MCHP_PS2_STATUS_PE (1U << (MCHP_PS2_STATUS_PE_POS)) 124 /* Framing Error(R/W1C) */ 125 #define MCHP_PS2_STATUS_FE_POS 3 126 #define MCHP_PS2_STATUS_FE (1U << (MCHP_PS2_STATUS_FE_POS)) 127 /* Transmitter is Idle(Read-Only) */ 128 #define MCHP_PS2_STATUS_TX_IDLE_POS 4 129 #define MCHP_PS2_STATUS_TX_IDLE (1U << (MCHP_PS2_STATUS_TX_IDLE_POS)) 130 /* Transmitter timeout(R/W1C) */ 131 #define MCHP_PS2_STATUS_TX_TMOUT_POS 5 132 #define MCHP_PS2_STATUS_TX_TMOUT (1U << (MCHP_PS2_STATUS_TX_TMOUT_POS)) 133 /* RX is Busy(Read-Only) */ 134 #define MCHP_PS2_STATUS_RX_BUSY_POS 6 135 #define MCHP_PS2_STATUS_RX_BUSY (1U << (MCHP_PS2_STATUS_RX_BUSY_POS)) 136 /* Transmitter start timeout(R/W1C) */ 137 #define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7 138 #define MCHP_PS2_STATUS_TX_ST_TMOUT (1U << (MCHP_PS2_STATUS_TX_ST_TMOUT_POS)) 139 140 /* 141 * PS2 Protocol bit positions 142 */ 143 #define MCHP_PS2_PROT_START_BIT_POS 1 144 #define MCHP_PS2_PROT_DATA_BIT0_POS 2 145 #define MCHP_PS2_PROT_DATA_BIT1_POS 3 146 #define MCHP_PS2_PROT_DATA_BIT2_POS 4 147 #define MCHP_PS2_PROT_DATA_BIT3_POS 5 148 #define MCHP_PS2_PROT_DATA_BIT4_POS 6 149 #define MCHP_PS2_PROT_DATA_BIT5_POS 7 150 #define MCHP_PS2_PROT_DATA_BIT6_POS 8 151 #define MCHP_PS2_PROT_DATA_BIT7_POS 9 152 #define MCHP_PS2_PROT_PARITY_POS 10 153 #define MCHP_PS2_PROT_STOP_BIT_POS 11 154 155 /** 156 * @brief PS/2 Controller Registers (PS2) 157 */ 158 typedef struct ps2_regs 159 { 160 __IOM uint32_t TRX_BUFF; /*!< (@ 0x0000) PS/2 Transmit buffer(WO), Receive buffer(RO) */ 161 __IOM uint32_t CTRL; /*!< (@ 0x0004) PS/2 Control */ 162 __IOM uint32_t STATUS; /*!< (@ 0x0008) PS/2 Status */ 163 } PS2_Type; 164 165 #endif /* #ifndef _PS2_CTRL_H */ 166 /* end ps2_ctrl.h */ 167 /** @} 168 */ 169
