1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file port80cap.h 28 *MEC1501 Port80 Capture Registers 29 */ 30 /** @defgroup MEC1501 Peripherals Port80 Capture 31 */ 32 33 #ifndef _PORT80CAP_H 34 #define _PORT80CAP_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* ========================================================================*/ 42 /* ================ PORT80 Capture ===========*/ 43 /* ========================================================================*/ 44 45 #define MCHP_PORT80_CAP_0_BASE_ADDR 0x400f8000u 46 #define MCHP_PORT80_CAP_1_BASE_ADDR 0x400f8000u 47 48 #define MCHP_PORT80_CAP_0_GIRQ 15u 49 #define MCHP_PORT80_CAP_0_GIRQ_POS 22u 50 #define MCHP_PORT80_CAP_0_GIRQ_VAL (1u << 22) 51 #define MCHP_PORT80_CAP_0_NVIC_AGGR 7u 52 #define MCHP_PORT80_CAP_0_NVIC_DIRECT 62u 53 54 #define MCHP_PORT80_CAP_1_GIRQ 15u 55 #define MCHP_PORT80_CAP_1_GIRQ_POS 23u 56 #define MCHP_PORT80_CAP_1_GIRQ_VAL (1u << 23) 57 #define MCHP_PORT80_CAP_1_NVIC_AGGR 7u 58 #define MCHP_PORT80_CAP_1_NVIC_DIRECT 63u 59 60 /* Port80 Capture receive FIFO number of entries */ 61 #define MCHP_PORT80_CAP_MAX_FIFO_ENTRIES 16u 62 63 /* 64 * HOST_DATA - Write-Only 65 */ 66 #define MCHP_PORT80_CAP_HOST_DATA_REG_MASK 0xffu 67 68 /* 69 * EC_DATA - Read-Only. Read as 32-bit. 70 * b[7:0] = Read captured data byte from FIFO 71 * b[31:8] = Timestamp if enabled. 72 */ 73 #define MCHP_PORT80_CAP_EC_DATA_REG_MASK 0xffffffffu 74 #define MCHP_PORT80_CAP_EC_DATA_POS 0u 75 #define MCHP_PORT80_CAP_EC_DATA_MASK 0xffu 76 #define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_POS 8u 77 #define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_MASK0 0x00ffffffu 78 #define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_MASK 0xffffff00u 79 80 /* 81 * Configuration 82 */ 83 #define MCHP_PORT80_CAP_CFG_REG_MASK 0xffu 84 /* Flush FIFO (Write-Only) */ 85 #define MCHP_PORT80_CAP_CFG_FLUSH_POS 1u 86 #define MCHP_PORT80_CAP_CFG_FLUSH (1u << 1) 87 /* Reset Timestamp (Write-Only) */ 88 #define MCHP_PORT80_CAP_CFG_TSRST_POS 2u 89 #define MCHP_PORT80_CAP_CFG_TSRST (1u << 2u) 90 /* Timestamp clock divider */ 91 #define MCHP_PORT80_CAP_CFG_TSDIV_POS 3u 92 #define MCHP_PORT80_CAP_CFG_TSDIV_MASK0 0x03u 93 #define MCHP_PORT80_CAP_CFG_TSDIV_MASK (0x03u << 3) 94 #define MCHP_PORT80_CAP_CFG_TSDIV_6MHZ (0x00u << 3) 95 #define MCHP_PORT80_CAP_CFG_TSDIV_3MHZ (0x01u << 3) 96 #define MCHP_PORT80_CAP_CFG_TSDIV_1P5MHZ (0x02u << 3) 97 #define MCHP_PORT80_CAP_CFG_TSDIV_750KHZ (0x03u << 3) 98 /* Timestamp Enable */ 99 #define MCHP_PORT80_CAP_CFG_TSEN_POS 5u 100 #define MCHP_PORT80_CAP_CFG_TSEN_MASK (1u << 5) 101 #define MCHP_PORT80_CAP_CFG_TSEN_ENABLE (1u << 5) 102 /* FIFO threshold */ 103 #define MCHP_PORT80_CAP_CFG_FIFO_THR_POS 6u 104 #define MCHP_PORT80_CAP_CFG_FIFO_THR_MASK0 0x03u 105 #define MCHP_PORT80_CAP_CFG_FIFO_THR_MASK (0x03u << 6) 106 #define MCHP_PORT80_CAP_CFG_FIFO_THR_1 (0x00u << 6) 107 #define MCHP_PORT80_CAP_CFG_FIFO_THR_4 (0x01u << 6) 108 #define MCHP_PORT80_CAP_CFG_FIFO_THR_8 (0x02u << 6) 109 #define MCHP_PORT80_CAP_CFG_FIFO_THR_14 (0x03u << 6) 110 111 /* 112 * Status - Read-only does not clear status on read. 113 */ 114 #define MCHP_PORT80_CAP_STS_REG_MASK 0x03u; 115 /* Bit[0] FIFO not empty. Cleared by FW reading all content from FIFO */ 116 #define MCHP_PORT80_CAP_STS_NOT_EMPTY_POS 0u 117 #define MCHP_PORT80_CAP_STS_NOT_EMPTY (1u << 0) 118 /* Bit[1] Overrun. Host wrote data when FIFO is full */ 119 #define MCHP_PORT80_CAP_STS_OVERRUN_POS 1u 120 #define MCHP_PORT80_CAP_STS_OVERRUN (1u << 1) 121 122 /* 123 * Count - R/W access to Port 80 counter 124 */ 125 #define MCHP_PORT80_CAP_CNT_REG_MASK 0xffffff00u 126 #define MCHP_PORT80_CAP_CNT_POS 8u 127 128 /* 129 * Port80 Capture Logical Device Activate register 130 */ 131 #define MCHP_PORT80_CAP_ACTV_MASK 0x01u 132 #define MCHP_PORT80_CAP_ACTV_ENABLE 0x01u 133 134 /** 135 * @brief Fast Port80 Capture Registers (PORT80_CAP_Type) 136 */ 137 typedef struct port80cap_regs 138 { 139 __OM uint32_t HOST_DATA; /*!< (@ 0x0000) Host Data b[7:0] write-only */ 140 uint8_t RSVD1[0x100u - 0x04u]; 141 __IM uint32_t EC_DATA; /*!< (@ 0x0100) EC Data. Read-only. */ 142 __IOM uint32_t CONFIG; /*!< (@ 0x0104) Configuration Mix of R/W and WO */ 143 __IOM uint32_t STATUS; /*!< (@ 0x0108) Status. Read-only */ 144 __IOM uint32_t COUNT; /*!< (@ 0x010c) Counter. R/W */ 145 uint8_t RSVD3[0x0330u - 0x0110u]; 146 __IOM uint32_t ACTV; /*!< (@ 0x0330) Logical device Activate */ 147 } PORT80_CAP_Type; 148 149 #endif /* #ifndef _PORT80CAP_H */ 150 /* end port80cap.h */ 151 /** @} 152 */ 153
