1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file peci.h 28 *MEC1501 Platform Environment Control Interface registers 29 */ 30 /** @defgroup MEC1501 Peripherals PECI 31 */ 32 33 #ifndef _PECI_H 34 #define _PECI_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ PECI =========== */ 43 /* =========================================================================*/ 44 45 #define MCHP_PECI_BASE_ADDR 0x40006400u 46 47 /* 48 * PECI interrupts. 49 */ 50 #define MCHP_PECI_GIRQ 17u 51 52 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 53 #define MCHP_PECI_GIRQ_POS 0 54 55 #define MCHP_PECI_GIRQ_VAL (1u << MCHP_PECI_GIRQ_POS) 56 57 /* PECI GIRQ aggregated NVIC input */ 58 #define MCHP_PECI_NVIC_AGGR 9u 59 60 /* PECI direct NVIC inputs */ 61 #define MCHP_PECI_NVIC_DIRECT 70u 62 63 /* 64 * Write Data register 65 */ 66 #define MCHP_PECI_WR_DATA_REG_OFS 0U 67 #define MCHP_PECI_WR_DATA_MASK 0xffu 68 69 /* 70 * Read Data register 71 */ 72 #define MCHP_PECI_RD_DATA_REG_OFS 4U 73 #define MCHP_PECI_RD_DATA_MASK 0xffu 74 75 /* 76 * Control register 77 */ 78 #define MCHP_PECI_CTRL_REG_OFS 8U 79 #define MCHP_PECI_CTRL_MASK 0xe9u 80 #define MCHP_PECI_CTRL_PD_POS 0 81 #define MCHP_PECI_CTRL_PD (1u << MCHP_PECI_CTRL_PD_POS) 82 #define MCHP_PECI_CTRL_RST_POS 3 83 #define MCHP_PECI_CTRL_RST (1u << MCHP_PECI_CTRL_RST_POS) 84 #define MCHP_PECI_CTRL_FRST_POS 5 85 #define MCHP_PECI_CTRL_FRST (1u << MCHP_PECI_CTRL_FRST_POS) 86 #define MCHP_PECI_CTRL_TXEN_POS 6 87 #define MCHP_PECI_CTRL_TXEN (1u << MCHP_PECI_CTRL_TXEN_POS) 88 #define MCHP_PECI_CTRL_MIEN_POS 7 89 #define MCHP_PECI_CTRL_MIEN (1u << MCHP_PECI_CTRL_MIEN_POS) 90 91 /* 92 * Status 1 register. RW1C and read-only bits. 93 */ 94 #define MCHP_PECI_STS1_REG_OFS 0x0cu 95 #define MCHP_PECI_STS1_MASK 0xbfu 96 #define MCHP_PECI_STS1_BOF_POS 0 97 #define MCHP_PECI_STS1_BOF (1u << MCHP_PECI_STS1_BOF_POS) 98 #define MCHP_PECI_STS1_EOF_POS 1 99 #define MCHP_PECI_STS1_EOF (1u << MCHP_PECI_STS1_EOF_POS) 100 /* Error is read-only */ 101 #define MCHP_PECI_STS1_ERR_POS 2 102 #define MCHP_PECI_STS1_ERR (1u << MCHP_PECI_STS1_ERR_POS) 103 /* Ready is read-only */ 104 #define MCHP_PECI_STS1_RDY_POS 3 105 #define MCHP_PECI_STS1_RDY (1u << MCHP_PECI_STS1_RDY_POS) 106 #define MCHP_PECI_STS1_RDYLO_POS 4 107 #define MCHP_PECI_STS1_RDYLO (1u << MCHP_PECI_STS1_RDYLO_POS) 108 #define MCHP_PECI_STS1_RDYHI_POS 5 109 #define MCHP_PECI_STS1_RDYHI (1u << MCHP_PECI_STS1_RDYHI_POS) 110 /* MINT is read-only */ 111 #define MCHP_PECI_STS1_MINT_POS 7 112 #define MCHP_PECI_STS1_MINT (1u << MCHP_PECI_STS1_MINT_POS) 113 114 /* 115 * Status 2 register. Read-only bits. 116 */ 117 #define MCHP_PECI_STS2_REG_OFS 0x10u 118 #define MCHP_PECI_STS2_MASK 0x8fu 119 #define MCHP_PECI_STS2_WFF_POS 0 120 #define MCHP_PECI_STS2_WFF (1u << MCHP_PECI_STS2_WFF_POS) 121 #define MCHP_PECI_STS2_WFE_POS 1 122 #define MCHP_PECI_STS2_WFE (1u << MCHP_PECI_STS2_WFE_POS) 123 #define MCHP_PECI_STS2_RFF_POS 2 124 #define MCHP_PECI_STS2_RFF (1u << MCHP_PECI_STS2_RFF_POS) 125 #define MCHP_PECI_STS2_RFE_POS 3 126 #define MCHP_PECI_STS2_RFE (1u << MCHP_PECI_STS2_RFE_POS) 127 #define MCHP_PECI_STS2_IDLE_POS 7 128 #define MCHP_PECI_STS2_IDLE (1u << MCHP_PECI_STS2_IDLE_POS) 129 130 /* 131 * Error register. R/W1C bits. 132 */ 133 #define MCHP_PECI_ERR_REG_OFS 0x14u 134 #define MCHP_PECI_ERR_MASK 0xf3u 135 #define MCHP_PECI_ERR_FERR_POS 0 136 #define MCHP_PECI_ERR_FERR (1u << MCHP_PECI_ERR_FERR_POS) 137 #define MCHP_PECI_ERR_BERR_POS 1 138 #define MCHP_PECI_ERR_BERR (1u << MCHP_PECI_ERR_BERR_POS) 139 #define MCHP_PECI_ERR_WROV_POS 4 140 #define MCHP_PECI_ERR_WROV (1u << MCHP_PECI_ERR_WROV_POS) 141 #define MCHP_PECI_ERR_WRUN_POS 5 142 #define MCHP_PECI_ERR_WRUN (1u << MCHP_PECI_ERR_WRUN_POS) 143 #define MCHP_PECI_ERR_RDOV_POS 6 144 #define MCHP_PECI_ERR_RDOV (1u << MCHP_PECI_ERR_RDOV_POS) 145 #define MCHP_PECI_ERR_CLK_POS 7 146 #define MCHP_PECI_ERR_CLK (1u << MCHP_PECI_ERR_CLK_POS) 147 148 /* 149 * Interrupt Enable 1 register. 150 */ 151 #define MCHP_PECI_IEN1_REG_OFS 0x18u 152 #define MCHP_PECI_IEN1_MASK 0x37u 153 #define MCHP_PECI_IEN1_BIEN_POS 0 154 #define MCHP_PECI_IEN1_BIEN (1u << MCHP_PECI_IEN1_BIEN_POS) 155 #define MCHP_PECI_IEN1_EIEN_POS 1 156 #define MCHP_PECI_IEN1_EIEN (1u << MCHP_PECI_IEN1_EIEN_POS) 157 #define MCHP_PECI_IEN1_EREN_POS 2 158 #define MCHP_PECI_IEN1_EREN (1u << MCHP_PECI_IEN1_EREN_POS) 159 #define MCHP_PECI_IEN1_RLEN_POS 4 160 #define MCHP_PECI_IEN1_RLEN (1u << MCHP_PECI_IEN1_RLEN_POS) 161 #define MCHP_PECI_IEN1_RHEN_POS 5 162 #define MCHP_PECI_IEN1_RHEN (1u << MCHP_PECI_IEN1_RHEN_POS) 163 164 /* 165 * Interrupt Enable 2 register. 166 */ 167 #define MCHP_PECI_IEN2_REG_OFS 0x1cu 168 #define MCHP_PECI_IEN2_MASK 0x06u 169 #define MCHP_PECI_IEN2_ENWFE_POS 1 170 #define MCHP_PECI_IEN2_ENWFE (1u << MCHP_PECI_IEN2_ENWFE_POS) 171 #define MCHP_PECI_IEN2_ENRFF_POS 2 172 #define MCHP_PECI_IEN2_ENRFF (1u << MCHP_PECI_IEN2_ENRFF_POS) 173 174 /* 175 * Optimal Bit Time LSB register. 176 */ 177 #define MCHP_PECI_OPT_BT_LSB_REG_OFS 0x20u 178 #define MCHP_PECI_OPT_BT_LSB_MASK 0xffu 179 180 /* 181 * Optimal Bit Time MSB register. 182 */ 183 #define MCHP_PECI_OPT_BT_MSB_REG_OFS 0x24u 184 #define MCHP_PECI_OPT_BT_MSB_MASK 0xffu 185 186 187 /** 188 * @brief Platform Enviroment Control Interface Registers (PECI) 189 */ 190 typedef struct peci_regs { 191 __IOM uint8_t WR_DATA; /*!< (@ 0x0000) PECI Write Data */ 192 uint8_t RSVD1[3]; 193 __IOM uint8_t RD_DATA; /*!< (@ 0x0004) PECI Read data */ 194 uint8_t RSVD2[3]; 195 __IOM uint8_t CONTROL; /*!< (@ 0x0008) PECI Control */ 196 uint8_t RSVD3[3]; 197 __IOM uint8_t STATUS1; /*!< (@ 0x000c) PECI Status 1 */ 198 uint8_t RSVD4[3]; 199 __IOM uint8_t STATUS2; /*!< (@ 0x0010) PECI Status 2 */ 200 uint8_t RSVD5[3]; 201 __IOM uint8_t ERROR; /*!< (@ 0x0014) PECI Error */ 202 uint8_t RSVD6[3]; 203 __IOM uint8_t INT_EN1; /*!< (@ 0x0018) PECI Interrupt Enable 1 */ 204 uint8_t RSVD7[3]; 205 __IOM uint8_t INT_EN2; /*!< (@ 0x001c) PECI Interrupt Enable 2 */ 206 uint8_t RSVD8[3]; 207 __IOM uint8_t OPT_BIT_TIME_LSB; /*!< (@ 0x0020) PECI Optimal Bit Time LSB */ 208 uint8_t RSVD9[3]; 209 __IOM uint8_t OPT_BIT_TIME_MSB; /*!< (@ 0x0024) PECI Optimal Bit Time MSB */ 210 uint8_t RSVD10[87]; /* 0x25 - 0x7c */ 211 } PECI_Type; 212 213 #endif /* #ifndef _PECI_H */ 214 /* end peci.h */ 215 /** @} 216 */ 217
