1 /**
2 *
3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
4 *
5 * \asf_license_start
6 *
7 * \page License
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License"); you may
12 * not use this file except in compliance with the License.
13 * You may obtain a copy of the Licence at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 *
23 * \asf_license_stop
24 *
25 */
26
27 /** @file pcr.h
28 *MEC1501 Power Control Reset definitions
29 */
30 /** @defgroup MEC1501 Peripherals PCR
31 */
32
33 #include <stdint.h>
34 #include <stddef.h>
35
36 #include "regaccess.h"
37
38 #ifndef _PCR_H
39 #define _PCR_H
40
41 #define MCHP_PCR_BASE_ADDR 0x40080100u
42
43 #define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00u
44 #define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04u
45 #define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08u
46 #define MCHP_PCR_OSC_ID_OFS 0x0cu
47 #define MCHP_PCR_PRS_OFS 0x10u
48 #define MCHP_PCR_PR_CTRL_OFS 0x14u
49 #define MCHP_PCR_SYS_RESET_OFS 0x18u
50 #define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1cu
51 #define MCHP_PCR_SLP_EN0_OFS 0x30u
52 #define MCHP_PCR_SLP_EN1_OFS 0x34u
53 #define MCHP_PCR_SLP_EN2_OFS 0x38u
54 #define MCHP_PCR_SLP_EN3_OFS 0x3cu
55 #define MCHP_PCR_SLP_EN4_OFS 0x40u
56 #define MCHP_PCR_CLK_REQ0_OFS 0x50u
57 #define MCHP_PCR_CLK_REQ1_OFS 0x54u
58 #define MCHP_PCR_CLK_REQ2_OFS 0x58u
59 #define MCHP_PCR_CLK_REQ3_OFS 0x5cu
60 #define MCHP_PCR_CLK_REQ4_OFS 0x60u
61 #define MCHP_PCR_PERIPH_RST0_OFS 0x70u
62 #define MCHP_PCR_PERIPH_RST1_OFS 0x74u
63 #define MCHP_PCR_PERIPH_RST2_OFS 0x78u
64 #define MCHP_PCR_PERIPH_RST3_OFS 0x7cu
65 #define MCHP_PCR_PERIPH_RST4_OFS 0x80u
66 #define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84u
67
68 #define MCHP_PCR_SYS_SLP_CTRL_ADDR (MCHP_PCR_BASE_ADDR)
69 #define MCHP_PCR_SYS_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x04u)
70 #define MCHP_PCR_SLOW_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x08u)
71 #define MCHP_PCR_OSC_ID_ADDR (MCHP_PCR_BASE_ADDR + 0x0cu)
72 #define MCHP_PCR_PRS_ADDR (MCHP_PCR_BASE_ADDR + 0x10u)
73 #define MCHP_PCR_PR_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x14u)
74 #define MCHP_PCR_SYS_RESET_ADDR (MCHP_PCR_BASE_ADDR + 0x18u)
75 #define MCHP_PCR_PKE_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x1cu)
76 #define MCHP_PCR_SLP_EN0_ADDR (MCHP_PCR_BASE_ADDR + 0x30u)
77 #define MCHP_PCR_SLP_EN1_ADDR (MCHP_PCR_BASE_ADDR + 0x34u)
78 #define MCHP_PCR_SLP_EN2_ADDR (MCHP_PCR_BASE_ADDR + 0x38u)
79 #define MCHP_PCR_SLP_EN3_ADDR (MCHP_PCR_BASE_ADDR + 0x3cu)
80 #define MCHP_PCR_SLP_EN4_ADDR (MCHP_PCR_BASE_ADDR + 0x40u)
81 #define MCHP_PCR_CLK_REQ0_ADDR (MCHP_PCR_BASE_ADDR + 0x50u)
82 #define MCHP_PCR_CLK_REQ1_ADDR (MCHP_PCR_BASE_ADDR + 0x54u)
83 #define MCHP_PCR_CLK_REQ2_ADDR (MCHP_PCR_BASE_ADDR + 0x58u)
84 #define MCHP_PCR_CLK_REQ3_ADDR (MCHP_PCR_BASE_ADDR + 0x5cu)
85 #define MCHP_PCR_CLK_REQ4_ADDR (MCHP_PCR_BASE_ADDR + 0x60u)
86 #define MCHP_PCR_PERIPH_RST0_ADDR (MCHP_PCR_BASE_ADDR + 0x70u)
87 #define MCHP_PCR_PERIPH_RST1_ADDR (MCHP_PCR_BASE_ADDR + 0x74u)
88 #define MCHP_PCR_PERIPH_RST2_ADDR (MCHP_PCR_BASE_ADDR + 0x78u)
89 #define MCHP_PCR_PERIPH_RST3_ADDR (MCHP_PCR_BASE_ADDR + 0x7cu)
90 #define MCHP_PCR_PERIPH_RST4_ADDR (MCHP_PCR_BASE_ADDR + 0x80u)
91 #define MCHP_PCR_PERIPH_RESET_LOCK_ADDR (MCHP_PCR_BASE_ADDR + 0x84u)
92
93 #define MCHP_PCR_SLP_EN_ADDR(n) \
94 (MCHP_PCR_BASE_ADDR + 0x30u + ((uint32_t)(n) << 2))
95 #define MCHP_PCR_CLK_REQ_ADDR(n) \
96 (MCHP_PCR_BASE_ADDR + 0x50u + ((uint32_t)(n) << 2))
97 #define MCHP_PCR_PERIPH_RESET_ADDR(n) \
98 (MCHP_PCR_BASE_ADDR + 0x70u + ((uint32_t)(n) << 2))
99
100 #define MCHP_PCR_SLEEP_EN (1u)
101 #define MCHP_PCR_SLEEP_DIS (0u)
102
103 /*
104 * MEC1501 PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers.
105 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
106 * clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx
107 * into light or heavy sleep.
108 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
109 * peripherals PCR CLK_REQ bit is 0.
110 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
111 * must be unlocked by writing the unlock code to PCR Peripheral Reset Lock
112 * register.
113 * SLP_EN usage is:
114 * Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as
115 * these IP do not implement internal clock gating.
116 * When firmware wants to enter light or heavy sleep.
117 * Configure wake up source(s)
118 * Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with
119 * SLEEP_ALL bit = 1.
120 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
121 * Cortex-M4 will assert sleep signal to PCR block.
122 * PCR HW will spin until all CLK_REQ==0
123 * PCR will then turn off clocks based on light/heavy sleep.
124 *
125 * RST_EN usage is:
126 * Save and disable maskable interrupts
127 * Write unlock code to PCR Peripheral Reset Lock
128 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
129 * Selected peripherals will be reset.
130 * Write lock code to PCR Peripheral Reset Lock.
131 * Restore interrupts.
132 */
133 #define MCHP_MAX_PCR_SCR_REGS 5u
134
135 /*
136 * VTR Powered PCR registers
137 */
138
139 #define MCHP_PCR_SLP(bitpos) (1u << (bitpos))
140
141 /*
142 * PCR System Sleep Control
143 */
144
145 #define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109u
146 #define MCHP_PCR_SYS_SLP_CTRL_SLP_LIGHT (0u << 0)
147 #define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY (1u << 0)
148 #define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL (1u << 3)
149 /*
150 * bit[8] can be used to prevent entry to heavy sleep unless the
151 * PLL is locked.
152 * bit[8]==0 (POR default) system will allow entry to light or heavy
153 * sleep if and only if PLL is locked.
154 * bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
155 */
156 #define MCHP_PCR_SYS_SLP_CTRL_SLP_PLL_LOCK (0u << 8)
157 #define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK (1u << 8)
158
159 #define MCHP_PCR_SYS_SLP_LIGHT 0x08u
160 #define MCHP_PCR_SYS_SLP_HEAVY 0x09u
161
162 /*
163 * PCR Process Clock Control
164 * Divides 48MHz clock to ARM Cortex-M4 core including
165 * SysTick and NVIC.
166 */
167 #define MCHP_PCR_PROC_CLK_CTRL_MASK 0xffu
168 #define MCHP_PCR_PROC_CLK_CTRL_48MHZ 0x01u
169 #define MCHP_PCR_PROC_CLK_CTRL_16MHZ 0x03u
170 #define MCHP_PCR_PROC_CLK_CTRL_12MHZ 0x04u
171 #define MCHP_PCR_PROC_CLK_CTRL_4MHZ 0x10u
172 #define MCHP_PCR_PROC_CLK_CTRL_1MHZ 0x30u
173
174 /*
175 * PCR Slow Clock Control
176 * Clock divicder for 100KHz clock domain
177 */
178 #define MCHP_PCR_SLOW_CLK_CTRL_MASK 0x3ffu
179 #define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1e0u
180
181 /*
182 * PCR Oscillator ID register (Read-Only)
183 */
184 #define MCHP_PCR_OSC_ID_MASK 0x1ffu
185 #define MCHP_PCR_OSC_ID_PLL_LOCK (1u << 8)
186
187 /*
188 * PCR Power Reset Status Register
189 */
190 #define MCHP_PCR_PRS_MASK 0xcecu
191 #define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO (1u << 2)
192 #define MCHP_PCR_PRS_HOST_RESET_STATE_RO (1u << 3)
193 #define MCHP_PCR_PRS_VBAT_RST_RWC (1u << 5)
194 #define MCHP_PCR_PRS_VTR_RST_RWC (1u << 6)
195 #define MCHP_PCR_PRS_JTAG_RST_RWC (1u << 7)
196 #define MCHP_PCR_PRS_32K_ACTIVE_RO (1u << 10)
197 #define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO (1u << 11)
198
199 /*
200 * PCR Power Reset Control Register
201 */
202 #define MCHP_PCR_PR_CTRL_MASK 0x101u
203 #define MCHP_PCR_PR_CTRL_PWR_INV (1u << 0)
204 #define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST (0u << 8)
205 #define MCHP_PCR_PR_CTRL_USE_PCI_RST (1u << 8)
206
207 /*
208 * PCR System Reset Register
209 */
210 #define MCHP_PCR_SYS_RESET_MASK 0x100u
211 #define MCHP_PCR_SYS_RESET_NOW (1u << 8)
212
213 /*
214 * PCR PKE Clock Register
215 */
216 #define MCHP_PCR_PKE_CLK_CTRL_MASK 0x03u
217 #define MCHP_PCR_PKE_CLK_CTRL_96M 0x00u
218 #define MCHP_PCR_PKE_CLK_CTRL_48M 0x03u
219
220 /*
221 * Sleep Enable Reg 0 (Offset +30h)
222 * Clock Required Reg 0 (Offset +50h)
223 * Reset Enable Reg 3 (Offset +70h)
224 */
225 #define MCHP_PCR0_JTAG_STAP_POS 0u
226
227 /*
228 * Sleep Enable Reg 1 (Offset +34h)
229 * Clock Required Reg 1 (Offset +54h)
230 * Reset Enable Reg 1 (Offset +74h)
231 */
232 #define MCHP_PCR1_ECIA_POS 0u
233 #define MCHP_PCR1_PECI_POS 1u
234 #define MCHP_PCR1_TACH0_POS 2u
235 #define MCHP_PCR1_PWM0_POS 4u
236 #define MCHP_PCR1_PMC_POS 5u
237 #define MCHP_PCR1_DMA_POS 6u
238 #define MCHP_PCR1_TFDP_POS 7u
239 #define MCHP_PCR1_CPU_POS 8u
240 #define MCHP_PCR1_WDT_POS 9u
241 #define MCHP_PCR1_SMB0_POS 10u
242 #define MCHP_PCR1_TACH1_POS 11u
243 #define MCHP_PCR1_TACH2_POS 12u
244 #define MCHP_PCR1_TACH3_POS 13u
245 #define MCHP_PCR1_PWM1_POS 20u
246 #define MCHP_PCR1_PWM2_POS 21u
247 #define MCHP_PCR1_PWM3_POS 22u
248 #define MCHP_PCR1_PWM4_POS 23u
249 #define MCHP_PCR1_PWM5_POS 24u
250 #define MCHP_PCR1_PWM6_POS 25u
251 #define MCHP_PCR1_PWM7_POS 26u
252 #define MCHP_PCR1_PWM8_POS 27u
253 #define MCHP_PCR1_ECS_POS 29u
254 #define MCHP_PCR1_B16TMR0_POS 30u
255 #define MCHP_PCR1_B16TMR1_POS 31u
256
257 /*
258 * Sleep Enable Reg 2 (Offset +38h)
259 * Clock Required Reg 2 (Offset +58h)
260 * Reset Enable Reg 2 (Offset +78h)
261 */
262 #define MCHP_PCR2_EMI0_POS 0u
263 #define MCHP_PCR2_UART0_POS 1u
264 #define MCHP_PCR2_UART1_POS 2u
265 #define MCHP_PCR2_GCFG_POS 12u
266 #define MCHP_PCR2_ACPI_EC0_POS 13u
267 #define MCHP_PCR2_ACPI_EC1_POS 14u
268 #define MCHP_PCR2_ACPI_PM1_POS 15u
269 #define MCHP_PCR2_KBC_POS 16u
270 #define MCHP_PCR2_MBOX_POS 17u
271 #define MCHP_PCR2_RTC_POS 18u
272 #define MCHP_PCR2_ESPI_POS 19u
273 #define MCHP_PCR2_SCR32_POS 20u
274 #define MCHP_PCR2_ACPI_EC2_POS 21u
275 #define MCHP_PCR2_ACPI_EC3_POS 22u
276 #define MCHP_PCR2_PORT80CAP0_POS 25u
277 #define MCHP_PCR2_PORT80CAP1_POS 26u
278 #define MCHP_PCR2_ESPI_SAF_POS 27u
279 #define MCHP_PCR2_UART2_POS 28u
280
281 /*
282 * Sleep Enable Reg 3 (Offset +3Ch)
283 * Clock Required Reg 3 (Offset +5Ch)
284 * Reset Enable Reg 3 (Offset +7Ch)
285 */
286 #define MCHP_PCR3_HDMI_CEC_POS 1u
287 #define MCHP_PCR3_ADC_POS 3u
288 #define MCHP_PCR3_PS2_0_POS 5u
289 #define MCHP_PCR3_PS2_1_POS 6u
290 #define MCHP_PCR3_HTMR0_POS 10u
291 #define MCHP_PCR3_KEYSCAN_POS 11u
292 #define MCHP_PCR3_SMB1_POS 13u
293 #define MCHP_PCR3_SMB2_POS 14u
294 #define MCHP_PCR3_SMB3_POS 15u
295 #define MCHP_PCR3_LED0_POS 16u
296 #define MCHP_PCR3_LED1_POS 17u
297 #define MCHP_PCR3_LED2_POS 18u
298 #define MCHP_PCR3_SMB4_POS 20u
299 #define MCHP_PCR3_B32TMR0_POS 23u
300 #define MCHP_PCR3_B32TMR1_POS 24u
301 #define MCHP_PCR3_PKE_POS 26u
302 #define MCHP_PCR3_RNG_POS 27u
303 #define MCHP_PCR3_AESH_POS 28u
304 #define MCHP_PCR3_HTMR1_POS 29u
305 #define MCHP_PCR3_CCT_POS 30u
306
307 #define MCHP_PCR3_CRYPTO_MASK \
308 ((1u << (MCHP_PCR3_PKE_POS)) +\
309 (1u << (MCHP_PCR3_RNG_POS)) + (1u << (MCHP_PCR3_AESH_POS)))
310
311 /*
312 * Sleep Enable Reg 4 (Offset +40h)
313 * Clock Required Reg 4 (Offset +60h)
314 * Reset Enable Reg 4 (Offset +80h)
315 */
316 #define MCHP_PCR4_RTMR_POS 6u
317 #define MCHP_PCR4_QMSPI_POS 8u
318 #define MCHP_PCR4_I2C0_POS 10u
319 #define MCHP_PCR4_I2C1_POS 11u
320 #define MCHP_PCR4_I2C3_POS 12u
321 #define MCHP_PCR4_SPISLV_POS 16u
322
323 /* Reset Enable Lock (Offset +84h) */
324 #define MCHP_PCR_RSTEN_UNLOCK 0xa6382d4cu
325 #define MCHP_PCR_RSTEN_LOCK 0xa6382d4du
326
327 /*
328 * PCR register access
329 */
330 #define MCHP_PCR_SLP_CTRL() REG32(MCHP_PCR_SYS_SLP_CTRL_ADDR)
331 #define MCHP_PCR_PROC_CLK_DIV() REG8(MCHP_PCR_SYS_CLK_CTRL_ADDR)
332 #define MCHP_PCR_SLOW_CLK_CTRL() REG32(MCHP_PCR_SLOW_CLK_CTRL_ADDR)
333 #define MCHP_PCR_OSC_ID() REG32(MCHP_PCR_OSC_ID_ADDR)
334 #define MCHP_PCR_PRS() REG32(MCHP_PCR_PRS_ADDR)
335 #define MCHP_PCR_PR_CTRL() REG32(MCHP_PCR_PR_CTRL_ADDR)
336 #define MCHP_PCR_SYS_RESET() REG32(MCHP_PCR_SYS_RESET_ADDR)
337 #define MCHP_PCR_PERIPH_RST_LOCK() \
338 REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR)
339 #define MCHP_PCR_SLP_EN(n) REG32(MCHP_PCR_SLP_EN_ADDR(n))
340 #define MCHP_PCR_CLK_REQ_RO(n) REG32(MCHP_PCR_CLK_REQ_ADDR(n))
341 #define MCHP_PCR_SLP_EN0() REG32(MCHP_PCR_SLP_EN_ADDR(0))
342 #define MCHP_PCR_SLP_EN1() REG32(MCHP_PCR_SLP_EN_ADDR(1))
343 #define MCHP_PCR_SLP_EN2() REG32(MCHP_PCR_SLP_EN_ADDR(2))
344 #define MCHP_PCR_SLP_EN3() REG32(MCHP_PCR_SLP_EN_ADDR(3))
345 #define MCHP_PCR_SLP_EN4() REG32(MCHP_PCR_SLP_EN_ADDR(4))
346 #define MCHP_PCR_CLK_REQ0_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(0))
347 #define MCHP_PCR_CLK_REQ1_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(1))
348 #define MCHP_PCR_CLK_REQ2_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(2))
349 #define MCHP_PCR_CLK_REQ3_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(3))
350 #define MCHP_PCR_CLK_REQ4_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(4))
351 #define MCHP_PCR_PERIPH_RST(n) REG32(MCHP_PCR_PERIPH_RESET_ADDR(n))
352
353 #define MCHP_PCR_DEV_SLP_EN_CLR(n, b) \
354 REG32(MCHP_PCR_SLP_EN_ADDR(n)) &= ~(1u << (uint32_t)(b))
355
356 #define MCHP_PCR_DEV_SLP_EN_SET(n, b) \
357 REG32(MCHP_PCR_SLP_EN_ADDR(n)) |= (1u << (uint32_t)(b))
358
359 /*
360 * PCR SleepEn/CLK_REQ/ResetOnSleep register offset from
361 * SlpEn0/CLK_REQ0/ResetOnSleep0 registers in b[7:5]
362 * Bit position in register = b[4:0]
363 */
364 typedef enum pcr_id {
365 PCR_STAP = 0u,
366 PCR_OTP = 1u,
367 PCR_ECIA = (128u + 0u), /* 4 << 5 = 128 */
368 PCR_PECI = (128u + 1u),
369 PCR_TACH0 = (128u + 2u),
370 PCR_PWM0 = (128u + 4u),
371 PCR_PMC = (128u + 5u),
372 PCR_DMA = (128u + 6u),
373 PCR_TFDP = (128u + 7u),
374 PCR_CPU = (128u + 8u),
375 PCR_WDT = (128u + 9u),
376 PCR_SMB0 = (128u + 10u),
377 PCR_TACH1 = (128u + 11u),
378 PCR_TACH2 = (128u + 12u),
379 PCR_TACH3 = (128u + 13u),
380 PCR_PWM1 = (128u + 20u),
381 PCR_PWM2 = (128u + 21u),
382 PCR_PWM3 = (128u + 22u),
383 PCR_PWM4 = (128u + 23u),
384 PCR_PWM5 = (128u + 24u),
385 PCR_PWM6 = (128u + 25u),
386 PCR_PWM7 = (128u + 26u),
387 PCR_PWM8 = (128u + 27u),
388 PCR_ECS = (128u + 29u),
389 PCR_B16TMR0 = (128u + 30u),
390 PCR_B16TMR1 = (128u + 31u),
391 PCR_EMI0 = (256u + 0u), /* 8 << 5 = 256 */
392 PCR_UART0 = (256u + 1u),
393 PCR_UART1 = (256u + 2u),
394 PCR_GCFG = (256u + 12u),
395 PCR_ACPI_EC0 = (256u + 13u),
396 PCR_ACPI_EC1 = (256u + 14u),
397 PCR_ACPI_PM1 = (256u + 15u),
398 PCR_KBC = (256u + 16u),
399 PCR_MBOX = (256u + 17u),
400 PCR_RTC = (256u + 18u),
401 PCR_ESPI = (256u + 19u),
402 PCR_SCR32 = (256u + 20u),
403 PCR_ACPI_EC2 = (256u + 21u),
404 PCR_ACPI_EC3 = (256u + 22u),
405 PCR_P80CAP0 = (256u + 25u),
406 PCR_P80CAP1 = (256u + 26u),
407 PCR_ESPI_SAF = (256u + 27u),
408 PCR_UART2 = (256u + 28u),
409 PCR_HDMI_CEC = (384u + 1u), /* 12 << 5 = 384 */
410 PCR_ADC = (384u + 3u),
411 PCR_PS2_0 = (384u + 5u),
412 PCR_PS2_1 = (384u + 6u),
413 PCR_HTMR0 = (384u + 10u),
414 PCR_KEYSCAN = (384u + 11u),
415 PCR_SMB1 = (384u + 13u),
416 PCR_SMB2 = (384u + 14u),
417 PCR_SMB3 = (384u + 15u),
418 PCR_LED0 = (384u + 16u),
419 PCR_LED1 = (384u + 17u),
420 PCR_LED2 = (384u + 18u),
421 PCR_SMB4 = (384u + 20u),
422 PCR_B32TMR0 = (384u + 23u),
423 PCR_B32TMR1 = (384u + 24u),
424 PCR_PKE = (384u + 26u),
425 PCR_NDRNG = (384u + 27u),
426 PCR_AESH = (384u + 28u),
427 PCR_HTMR1 = (384u + 29u),
428 PCR_CCT = (384u + 30u),
429 PCR_RTMR = (512u + 6u), /* 16 << 5 = 512 */
430 PCR_QMSPI = (512u + 8u),
431 PCR_I2C0 = (512u + 10u),
432 PCR_I2C1 = (512u + 11u),
433 PCR_I2C2 = (512u + 12u),
434 PCR_SPISLV = (512u + 16u),
435 PCR_MAX_ID,
436 } PCR_ID;
437
438 /* =====================================================================*/
439 /* ================ PCR ================ */
440 /* =====================================================================*/
441
442 /**
443 * @brief Power Control Reset (PCR)
444 */
445
446 typedef struct pcr_regs
447 { /*!< (@ 0x40080100) PCR Structure */
448 __IOM uint32_t SYS_SLP_CTRL; /*!< (@ 0x0000) System Sleep Control */
449 __IOM uint32_t PROC_CLK_CTRL; /*!< (@ 0x0004) Processor Clock Control */
450 __IOM uint32_t SLOW_CLK_CTRL; /*!< (@ 0x0008) Slow Clock Control */
451 __IOM uint32_t OSC_ID; /*!< (@ 0x000c) Processor Clock Control */
452 __IOM uint32_t PWR_RST_STS; /*!< (@ 0x0010) Power Reset Status */
453 __IOM uint32_t PWR_RST_CTRL; /*!< (@ 0x0014) Power Reset Control */
454 __IOM uint32_t SYS_RST; /*!< (@ 0x0018) System Reset */
455 __IOM uint32_t TEST1C;
456 __IOM uint32_t TEST20;
457 uint8_t RSVD1[12];
458 __IOM uint32_t SLP_EN0; /*!< (@ 0x0030) Sleep Enable 0 */
459 __IOM uint32_t SLP_EN1; /*!< (@ 0x0034) Sleep Enable 1 */
460 __IOM uint32_t SLP_EN2; /*!< (@ 0x0038) Sleep Enable 2 */
461 __IOM uint32_t SLP_EN3; /*!< (@ 0x003c) Sleep Enable 3 */
462 __IOM uint32_t SLP_EN4; /*!< (@ 0x0040) Sleep Enable 4 */
463 uint8_t RSVD2[12];
464 __IOM uint32_t CLK_REQ0; /*!< (@ 0x0050) Clock Required 0 (RO) */
465 __IOM uint32_t CLK_REQ1; /*!< (@ 0x0054) Clock Required 1 (RO) */
466 __IOM uint32_t CLK_REQ2; /*!< (@ 0x0058) Clock Required 2 (RO) */
467 __IOM uint32_t CLK_REQ3; /*!< (@ 0x005c) Clock Required 3 (RO) */
468 __IOM uint32_t CLK_REQ4; /*!< (@ 0x0060) Clock Required 4 (RO) */
469 uint8_t RSVD3[12];
470 __IOM uint32_t RST_EN0; /*!< (@ 0x0070) Peripheral Reset 0 */
471 __IOM uint32_t RST_EN1; /*!< (@ 0x0074) Peripheral Reset 1 */
472 __IOM uint32_t RST_EN2; /*!< (@ 0x0078) Peripheral Reset 2 */
473 __IOM uint32_t RST_EN3; /*!< (@ 0x007c) Peripheral Reset 3 */
474 __IOM uint32_t RST_EN4; /*!< (@ 0x0080) Peripheral Reset 4 */
475 __IOM uint32_t RST_EN_LOCK; /*!< (@ 0x0084) Peripheral Lock */
476 } PCR_Type;
477
478 static __attribute__ ((always_inline)) inline void
mchp_pcr_periph_slp_ctrl(PCR_ID pcr_id,uint8_t enable)479 mchp_pcr_periph_slp_ctrl(PCR_ID pcr_id, uint8_t enable)
480 {
481 uintptr_t raddr = (uintptr_t) (MCHP_PCR_SLP_EN0_ADDR);
482 uint32_t bitpos = (uint32_t) pcr_id & 0x1f;
483
484 raddr += ((uint32_t) pcr_id >> 5);
485 if (enable) {
486 REG32(raddr) |= (1u << bitpos);
487 } else {
488 REG32(raddr) &= ~(1u << bitpos);
489 }
490 }
491
492 static __attribute__ ((always_inline)) inline void
mchp_pcr_periph_reset(PCR_ID pcr_id)493 mchp_pcr_periph_reset(PCR_ID pcr_id)
494 {
495 uintptr_t raddr = (uintptr_t) (MCHP_PCR_PERIPH_RST0_ADDR);
496 uint32_t bitpos = (uint32_t) pcr_id & 0x1f;
497
498 raddr += ((uint32_t) pcr_id >> 5);
499 REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_UNLOCK;
500 REG32(raddr) = (1u << bitpos);
501 REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_LOCK;
502 }
503
504 #endif // #ifndef _DEFS_H
505 /* end pcr.h */
506 /** @}
507 */
508
