1 /**
2 *
3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
4 *
5 * \asf_license_start
6 *
7 * \page License
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License"); you may
12 * not use this file except in compliance with the License.
13 * You may obtain a copy of the Licence at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 *
23 * \asf_license_stop
24 *
25 */
26
27 /** @file gpio.h
28 *MEC1501 GPIO definitions
29 */
30 /** @defgroup MEC1501 Peripherals GPIO
31 */
32
33 #ifndef _GPIO_H
34 #define _GPIO_H
35
36 #include <stdint.h>
37 #include <stddef.h>
38
39 #define NUM_MCHP_GPIO_PORTS 6u
40 #define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u)
41
42 #define MCHP_GPIO_BASE_ADDR 0x40081000u
43 #define MCHP_GPIO_CTRL_BASE 0x40081000u
44 #define MCHP_GPIO_PARIN_OFS 0x0300u
45 #define MCHP_GPIO_PAROUT_OFS 0x0380u
46 #define MCHP_GPIO_LOCK_OFS 0x03e8u
47 #define MCHP_GPIO_CTRL2_OFS 0x0500u
48
49 #define MCHP_GPIO_PARIN_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_PARIN_OFS)
50 #define MCHP_GPIO_PAROUT_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_PAROUT_OFS)
51 #define MCHP_GPIO_LOCK_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_LOCK_OFS)
52 #define MCHP_GPIO_CTRL2_BASE (MCHP_GPIO_CTRL_BASE + MCHP_GPIO_CTRL2_OFS)
53
54 /*
55 * !!! MEC15xx data sheets pin numbering is octal !!!
56 * n = pin number in octal or the equivalent in decimal or hex
57 * Example: GPIO135
58 * n = 0135 or n = 0x5d or n = 93
59 */
60 #define MCHP_GPIO_CTRL_ADDR(n) \
61 ((uintptr_t)(MCHP_GPIO_CTRL_BASE) + ((uintptr_t)(n) << 2))
62
63 #define MCHP_GPIO_CTRL2_ADDR(n) \
64 ((uintptr_t)(MCHP_GPIO_CTRL_BASE + MCHP_GPIO_CTRL2_OFS) +\
65 ((uintptr_t)(n) << 2))
66
67 /*
68 * GPIO Parallel In registers.
69 * Each register contains 32 GPIO's
70 * PARIN0 for GPIO_0000 - 0037
71 * PARIN1 for GPIO_0040 - 0077
72 * PARIN2 for GPIO_0100 - 0137
73 * PARIN3 for GPIO_0140 - 0177
74 * PARIN4 for GPIO_0200 - 0237
75 * PARIN5 for GPIO_0240 - 0277
76 */
77 #define MCHP_GPIO_PARIN_ADDR(n) ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
78 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + ((n) << 2))
79
80 #define MCHP_GPIO_PARIN0_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
81 (uintptr_t)(MCHP_GPIO_PARIN_OFS))
82
83 #define MCHP_GPIO_PARIN1_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
84 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + 0x04u)
85
86 #define MCHP_GPIO_PARIN2_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
87 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + 0x08u)
88
89 #define MCHP_GPIO_PARIN3_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
90 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + 0x0cu)
91
92 #define MCHP_GPIO_PARIN4_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
93 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + 0x10u)
94
95 #define MCHP_GPIO_PARIN5_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
96 (uintptr_t)(MCHP_GPIO_PARIN_OFS) + 0x14u)
97
98 /*
99 * GPIO Parallel Out registers.
100 * Each register contains 32 GPIO's
101 * PAROUT0 for GPIO_0000 - 0037
102 * PAROUT1 for GPIO_0040 - 0077
103 * PAROUT2 for GPIO_0100 - 0137
104 * PAROUT3 for GPIO_0140 - 0177
105 * PAROUT4 for GPIO_0200 - 0237
106 * PAROUT5 for GPIO_0240 - 0277
107 */
108 #define MCHP_GPIO_PAROUT_ADDR(n) ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
109 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + ((n) << 2))
110
111 #define MCHP_GPIO_PAROUT0_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
112 (uintptr_t)(MCHP_GPIO_PAROUT_OFS))
113
114 #define MCHP_GPIO_PAROUT1_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
115 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + 0x04u)
116
117 #define MCHP_GPIO_PAROUT2_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
118 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + 0x08u)
119
120 #define MCHP_GPIO_PAROUT3_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
121 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + 0x0cu)
122
123 #define MCHP_GPIO_PAROUT4_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
124 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + 0x10u)
125
126 #define MCHP_GPIO_PAROUT5_ADDR ((uintptr_t)(MCHP_GPIO_BASE_ADDR) +\
127 (uintptr_t)(MCHP_GPIO_PAROUT_OFS) + 0x14u)
128
129 /*
130 * MEC1501H-B0-SZ (144-pin)
131 */
132 #define MCHP_GPIO_PORT_A_BITMAP 0x7fffff9du /* GPIO_0000 - 0036 GIRQ11 */
133 #define MCHP_GPIO_PORT_B_BITMAP 0x0ffffffdu /* GPIO_0040 - 0076 GIRQ10 */
134 #define MCHP_GPIO_PORT_C_BITMAP 0x07ff3cf7u /* GPIO_0100 - 0136 GIRQ09 */
135 #define MCHP_GPIO_PORT_D_BITMAP 0x272effffu /* GPIO_0140 - 0176 GIRQ08 */
136 #define MCHP_GPIO_PORT_E_BITMAP 0x00de00ffu /* GPIO_0200 - 0236 GIRQ12 */
137 #define MCHP_GPIO_PORT_F_BITMAP 0x0000397fu /* GPIO_0240 - 0276 GIRQ26 */
138
139 #define MCHP_GPIO_PORT_A_DRVSTR_BITMAP 0x7fffff9du
140 #define MCHP_GPIO_PORT_B_DRVSTR_BITMAP 0x0ffffffdu
141 #define MCHP_GPIO_PORT_C_DRVSTR_BITMAP 0x07ff3cf7u
142 #define MCHP_GPIO_PORT_D_DRVSTR_BITMAP 0x272effffu
143 #define MCHP_GPIO_PORT_E_DRVSTR_BITMAP 0x00de00ffu
144 #define MCHP_GPIO_PORT_F_DRVSTR_BITMAP 0x0000397fu
145
146 /*
147 * GPIO Port to ECIA GIRQ mapping
148 */
149 #define MCHP_GPIO_PORT_A_GIRQ 11u
150 #define MCHP_GPIO_PORT_B_GIRQ 10u
151 #define MCHP_GPIO_PORT_C_GIRQ 9u
152 #define MCHP_GPIO_PORT_D_GIRQ 8u
153 #define MCHP_GPIO_PORT_E_GIRQ 12u
154 #define MCHP_GPIO_PORT_F_GIRQ 26u
155
156 /*
157 * GPIO Port GIRQ to NVIC external input
158 * GPIO GIRQ's are always aggregated.
159 */
160 #define MCHP_GPIO_PORT_A_NVIC 3u
161 #define MCHP_GPIO_PORT_B_NVIC 2u
162 #define MCHP_GPIO_PORT_C_NVIC 1u
163 #define MCHP_GPIO_PORT_D_NVIC 0u
164 #define MCHP_GPIO_PORT_E_NVIC 4u
165 #define MCHP_GPIO_PORT_F_NVIC 17u
166
167 /*
168 * Control
169 */
170 #define MCHP_GPIO_CTRL_MASK 0x0101bfffu
171 /* bits[15:0] of Control register */
172 #define MCHP_GPIO_CTRL_CFG_MASK 0xbfffu
173
174 /* Disable interrupt detect and pad */
175 #define MCHP_GPIO_CTRL_DIS_PIN 0x8040u
176
177 #define MCHP_GPIO_CTRL_DFLT 0x8040u
178 #define MCHP_GPIO_CTRL_DFLT_MASK 0xffffu
179
180 #define GPIO000_CTRL_DFLT 0x1040u
181 #define GPIO161_CTRL_DFLT 0x1040u
182 #define GPIO162_CTRL_DFLT 0x1040u
183 #define GPIO163_CTRL_DFLT 0x1040u
184 #define GPIO172_CTRL_DFLT 0x1040u
185 #define GPIO062_CTRL_DFLT 0x8240u
186 #define GPIO170_CTRL_DFLT 0x0041u /* Boot-ROM JTAG_STRAP_BS */
187 #define GPIO116_CTRL_DFLT 0x0041u
188 #define GPIO250_CTRL_DFLT 0x1240u
189
190 /*
191 * GPIO Control register field definitions.
192 */
193
194 /* bits[1:0] internal pull up/down selection */
195 #define MCHP_GPIO_CTRL_PUD_POS 0u
196 #define MCHP_GPIO_CTRL_PUD_MASK0 0x03u
197 #define MCHP_GPIO_CTRL_PUD_MASK (0x03u << (MCHP_GPIO_CTRL_PUD_POS))
198 #define MCHP_GPIO_CTRL_PUD_NONE 0x00u
199 #define MCHP_GPIO_CTRL_PUD_PU 0x01u
200 #define MCHP_GPIO_CTRL_PUD_PD 0x02u
201 /* Repeater(keeper) mode */
202 #define MCHP_GPIO_CTRL_PUD_RPT 0x03u
203
204 #define MCHP_GPIO_CTRL_PUD_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_PUD_POS)\
205 & MCHP_GPIO_CTRL_PUD_MASK0)
206 #define MCHP_GPIO_CTRL_PUD_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_PUD_MASK0)\
207 << MCHP_GPIO_CTRL_PUD_POS)
208
209 /* bits[3:2] power gating */
210 #define MCHP_GPIO_CTRL_PWRG_POS 2u
211 #define MCHP_GPIO_CTRL_PWRG_MASK0 0x03u
212 #define MCHP_GPIO_CTRL_PWRG_MASK (0x03u << (MCHP_GPIO_CTRL_PWRG_POS))
213 #define MCHP_GPIO_CTRL_PWRG_VTR_IO (0x00u << (MCHP_GPIO_CTRL_PWRG_POS))
214 #define MCHP_GPIO_CTRL_PWRG_VCC_IO (0x01u << (MCHP_GPIO_CTRL_PWRG_POS))
215 #define MCHP_GPIO_CTRL_PWRG_OFF (0x02u << (MCHP_GPIO_CTRL_PWRG_POS))
216 #define MCHP_GPIO_CTRL_PWRG_RSVD (0x03u << (MCHP_GPIO_CTRL_PWRG_POS))
217
218 #define MCHP_GPIO_CTRL_PWRG_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_PWRG_POS)\
219 & MCHP_GPIO_CTRL_PWRG_MASK0)
220 #define MCHP_GPIO_CTRL_PWRG_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_PWRG_MASK0)\
221 << MCHP_GPIO_CTRL_PWRG_POS)
222
223 /* bits[7:4] interrupt detection mode */
224 #define MCHP_GPIO_CTRL_IDET_POS 4u
225 #define MCHP_GPIO_CTRL_IDET_MASK0 0x0fu
226 #define MCHP_GPIO_CTRL_IDET_MASK (0x0fu << (MCHP_GPIO_CTRL_IDET_POS))
227 #define MCHP_GPIO_CTRL_IDET_LVL_LO (0x00u << (MCHP_GPIO_CTRL_IDET_POS))
228 #define MCHP_GPIO_CTRL_IDET_LVL_HI (0x01u << (MCHP_GPIO_CTRL_IDET_POS))
229 #define MCHP_GPIO_CTRL_IDET_DISABLE (0x04u << (MCHP_GPIO_CTRL_IDET_POS))
230 #define MCHP_GPIO_CTRL_IDET_REDGE (0x0du << (MCHP_GPIO_CTRL_IDET_POS))
231 #define MCHP_GPIO_CTRL_IDET_FEDGE (0x0eu << (MCHP_GPIO_CTRL_IDET_POS))
232 #define MCHP_GPIO_CTRL_IDET_BEDGE (0x0fu << (MCHP_GPIO_CTRL_IDET_POS))
233
234 #define MCHP_GPIO_CTRL_IDET_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_IDET_POS)\
235 & MCHP_GPIO_CTRL_IDET_MASK0)
236 #define MCHP_GPIO_CTRL_IDET_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_IDET_MASK0)\
237 << MCHP_GPIO_CTRL_IDET_POS)
238
239 /* bit[8] output buffer type: push-pull or open-drain */
240 #define MCHP_GPIO_CTRL_BUFT_POS 8u
241 #define MCHP_GPIO_CTRL_BUFT_MASK0 0x01u
242 #define MCHP_GPIO_CTRL_BUFT_MASK (1u << (MCHP_GPIO_CTRL_BUFT_POS))
243 #define MCHP_GPIO_CTRL_BUFT_PUSHPULL (0x00u << (MCHP_GPIO_CTRL_BUFT_POS))
244 #define MCHP_GPIO_CTRL_BUFT_OPENDRAIN (0x01u << (MCHP_GPIO_CTRL_BUFT_POS))
245
246 #define MCHP_GPIO_CTRL_BUFT_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_BUFT_POS)\
247 & MCHP_GPIO_CTRL_BUFT_MASK0)
248 #define MCHP_GPIO_CTRL_BUFT_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_BUFT_MASK0)\
249 << MCHP_GPIO_CTRL_BUFT_POS)
250
251 /* bit[9] direction */
252 #define MCHP_GPIO_CTRL_DIR_POS 9u
253 #define MCHP_GPIO_CTRL_DIR_MASK0 0x01u
254 #define MCHP_GPIO_CTRL_DIR_MASK (0x01u << (MCHP_GPIO_CTRL_DIR_POS))
255 #define MCHP_GPIO_CTRL_DIR_INPUT (0x00u << (MCHP_GPIO_CTRL_DIR_POS))
256 #define MCHP_GPIO_CTRL_DIR_OUTPUT (0x01u << (MCHP_GPIO_CTRL_DIR_POS))
257
258 #define MCHP_GPIO_CTRL_DIR_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_DIR_POS)\
259 & MCHP_GPIO_CTRL_DIR_MASK0)
260 #define MCHP_GPIO_CTRL_DIR_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_DIR_MASK0)\
261 << MCHP_GPIO_CTRL_DIR_POS)
262
263 /*
264 * bit[10] Alternate output disable. Default==0(alternate output enabled)
265 * GPIO output value is controlled by bit[16] of this register.
266 * Set bit[10]=1 if you wish to control pin output using the parallel
267 * GPIO output register bit for this pin.
268 */
269 #define MCHP_GPIO_CTRL_AOD_POS 10u
270 #define MCHP_GPIO_CTRL_AOD_MASK0 0x01u
271 #define MCHP_GPIO_CTRL_AOD_MASK (1u << (MCHP_GPIO_CTRL_AOD_POS))
272 #define MCHP_GPIO_CTRL_AOD_DIS (0x01u << (MCHP_GPIO_CTRL_AOD_POS))
273 #define MCHP_GPIO_CTRL_AOD_EN (0x00u << (MCHP_GPIO_CTRL_AOD_POS))
274
275 #define MCHP_GPIO_CTRL_AOD_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_AOD_POS)\
276 & MCHP_GPIO_CTRL_AOD_MASK0)
277 #define MCHP_GPIO_CTRL_AOD_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_AOD_MASK0)\
278 << MCHP_GPIO_CTRL_AOD_POS)
279
280 /* bit[11] GPIO function output polarity */
281 #define MCHP_GPIO_CTRL_POL_POS 11u
282 #define MCHP_GPIO_CTRL_POL_MASK0 0x01u
283 #define MCHP_GPIO_CTRL_POL_MASK (1u << (MCHP_GPIO_CTRL_POL_POS))
284 #define MCHP_GPIO_CTRL_POL_NON_INVERT (0x00u << (MCHP_GPIO_CTRL_POL_POS))
285 #define MCHP_GPIO_CTRL_POL_INVERT (0x01u << (MCHP_GPIO_CTRL_POL_POS))
286
287 #define MCHP_GPIO_CTRL_POL_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_POL_POS)\
288 & MCHP_GPIO_CTRL_POL_MASK0)
289 #define MCHP_GPIO_CTRL_POL_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_POL_MASK0)\
290 << MCHP_GPIO_CTRL_POL_POS)
291
292 /* bits[13:12] pin mux (function) */
293 #define MCHP_GPIO_CTRL_MUX_POS 12u
294 #define MCHP_GPIO_CTRL_MUX_MASK0 0x03u
295 #define MCHP_GPIO_CTRL_MUX_MASK \
296 (MCHP_GPIO_CTRL_MUX_MASK0 << (MCHP_GPIO_CTRL_MUX_POS))
297 #define MCHP_GPIO_CTRL_MUX_F0 (0x00u << (MCHP_GPIO_CTRL_MUX_POS))
298 #define MCHP_GPIO_CTRL_MUX_F1 (0x01u << (MCHP_GPIO_CTRL_MUX_POS))
299 #define MCHP_GPIO_CTRL_MUX_F2 (0x02u << (MCHP_GPIO_CTRL_MUX_POS))
300 #define MCHP_GPIO_CTRL_MUX_F3 (0x03u << (MCHP_GPIO_CTRL_MUX_POS))
301
302 #define MCHP_GPIO_CTRL_MUX_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_MUX_POS)\
303 & MCHP_GPIO_CTRL_MUX_MASK0)
304 #define MCHP_GPIO_CTRL_MUX_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_MUX_MASK0)\
305 << MCHP_GPIO_CTRL_MUX_POS)
306
307 /* bit[14] = read-only 0 reserved */
308
309 /*
310 * bit[15] Disables input pad leaving output pad enabled
311 * Useful for reducing power consumption of output only pins.
312 */
313 #define MCHP_GPIO_CTRL_INPAD_DIS_POS 15u
314 #define MCHP_GPIO_CTRL_INPAD_DIS_MASK0 0x01u
315 #define MCHP_GPIO_CTRL_INPAD_DIS_MASK (0x01u << (MCHP_GPIO_CTRL_INPAD_DIS_POS))
316 #define MCHP_GPIO_CTRL_INPAD_DIS (0x01u << (MCHP_GPIO_CTRL_INPAD_DIS_POS))
317 #define MCHP_GPIO_CTRL_INPAD_EN (0u << (MCHP_GPIO_CTRL_INPAD_DIS_POS))
318
319 #define MCHP_GPIO_CTRL_INPAD_DIS_GET(x) (((uint32_t)(x) >> \
320 MCHP_GPIO_CTRL_INPAD_DIS_POS) & MCHP_GPIO_CTRL_INPAD_DIS_MASK0)
321 #define MCHP_GPIO_CTRL_INPAD_DIS_SET(x) (((uint32_t)(x) & \
322 MCHP_GPIO_CTRL_INPAD_DIS_MASK0) << MCHP_GPIO_CTRL_INPAD_DIS_POS)
323
324 /*
325 * bit[16]: Alternate output pin value. Enabled when bit[10]==0(default)
326 */
327 #define MCHP_GPIO_CTRL_OUTVAL_POS 16u
328 #define MCHP_GPIO_CTRL_OUTVAL_MASK0 0x01u
329 #define MCHP_GPIO_CTRL_OUTVAL_MASK (1u << (MCHP_GPIO_CTRL_OUTVAL_POS))
330 #define MCHP_GPIO_CTRL_OUTV_LO (0x00u << (MCHP_GPIO_CTRL_OUTVAL_POS))
331 #define MCHP_GPIO_CTRL_OUTV_HI (0x01u << (MCHP_GPIO_CTRL_OUTVAL_POS))
332
333 #define MCHP_GPIO_CTRL_OUTVAL_GET(x) (((uint32_t)(x) >> \
334 MCHP_GPIO_CTRL_OUTVAL_POS) & MCHP_GPIO_CTRL_OUTVAL_MASK0)
335 #define MCHP_GPIO_CTRL_OUTVAL_SET(x) (((uint32_t)(x) & \
336 MCHP_GPIO_CTRL_OUTVAL_MASK0) << MCHP_GPIO_CTRL_OUTVAL_POS)
337
338 /* bit[24] Input pad value. Always live unless input pad is powered down */
339 #define MCHP_GPIO_CTRL_INPAD_VAL_POS 24u
340 #define MCHP_GPIO_CTRL_INPAD_VAL_BLEN 1u
341 #define MCHP_GPIO_CTRL_INPAD_VAL_MASK0 0x01u
342 #define MCHP_GPIO_CTRL_INPAD_VAL_MASK (0x01u << (MCHP_GPIO_CTRL_INPAD_VAL_POS))
343 #define MCHP_GPIO_CTRL_INPAD_VAL_LO (0x00u << (MCHP_GPIO_CTRL_INPAD_VAL_POS))
344 #define MCHP_GPIO_CTRL_INPAD_VAL_HI (0x01u << (MCHP_GPIO_CTRL_INPAD_VAL_POS))
345
346 #define MCHP_GPIO_CTRL_INPAD_VAL_GET(x) (((uint32_t)(x) >> \
347 MCHP_GPIO_CTRL_INPAD_VAL_POS) & MCHP_GPIO_CTRL_INPAD_VAL_MASK0)
348
349 #define MCHP_GPIO_CTRL_INPAD_VAL_SET(x) (((uint32_t)(x) & \
350 MCHP_GPIO_CTRL_INPAD_VAL_MASK0) << MCHP_GPIO_CTRL_INPAD_VAL_POS)
351
352 #define MCHP_GPIO_CTRL_DRIVE_OD_HI \
353 (MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT +\
354 MCHP_GPIO_CTRL_AOD_EN + MCHP_GPIO_CTRL_POL_NON_INVERT +\
355 MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTVAL_HI)
356
357 #define MCHP_GPIO_CTRL_DRIVE_OD_HI_MASK \
358 (MCHP_GPIO_CTRL_BUFT_MASK + MCHP_GPIO_CTRL_DIR_MASK +\
359 MCHP_GPIO_CTRL_AOD_MASK + MCHP_GPIO_CTRL_POL_MASK +\
360 MCHP_GPIO_CTRL_MUX_MASK + MCHP_GPIO_CTRL_OUTVAL_MASK)
361
362 /*
363 * Each GPIO pin implements a second control register.
364 * GPIO Control 2 register selects pin drive strength and slew rate.
365 * bit[0] = slew rate: 0=slow, 1=fast
366 * bits[5:4] = drive strength
367 * 00b = 2mA (default)
368 * 01b = 4mA
369 * 10b = 8mA
370 * 11b = 12mA
371 */
372 #define MCHP_GPIO_CTRL2_OFFSET 0x0500u
373 #define MCHP_GPIO_CTRL2_SLEW_POS 0u
374 #define MCHP_GPIO_CTRL2_SLEW_MASK (1u << MCHP_GPIO_CTRL2_SLEW_POS)
375 #define MCHP_GPIO_CTRL2_SLEW_SLOW (0u << MCHP_GPIO_CTRL2_SLEW_POS)
376 #define MCHP_GPIO_CTRL2_SLEW_FAST (1u << MCHP_GPIO_CTRL2_SLEW_POS)
377 #define MCHP_GPIO_CTRL2_DRV_STR_POS 4u
378 #define MCHP_GPIO_CTRL2_DRV_STR_MASK (0x03u << MCHP_GPIO_CTRL2_DRV_STR_POS)
379 #define MCHP_GPIO_CTRL2_DRV_STR_2MA (0u << MCHP_GPIO_CTRL2_DRV_STR_POS)
380 #define MCHP_GPIO_CTRL2_DRV_STR_4MA (1u << MCHP_GPIO_CTRL2_DRV_STR_POS)
381 #define MCHP_GPIO_CTRL2_DRV_STR_8MA (2u << MCHP_GPIO_CTRL2_DRV_STR_POS)
382 #define MCHP_GPIO_CTRL2_DRV_STR_12MA (3u << MCHP_GPIO_CTRL2_DRV_STR_POS)
383
384 /*
385 * GPIO pin numbers
386 */
387 enum mec_gpio_idx {
388 MCHP_GPIO_0000_ID = 0u, /* Port A bit[0] */
389 MCHP_GPIO_0002_ID = 2u,
390 MCHP_GPIO_0003_ID,
391 MCHP_GPIO_0004_ID,
392 MCHP_GPIO_0007_ID = 7u,
393 MCHP_GPIO_0010_ID,
394 MCHP_GPIO_0011_ID,
395 MCHP_GPIO_0012_ID,
396 MCHP_GPIO_0013_ID,
397 MCHP_GPIO_0014_ID,
398 MCHP_GPIO_0015_ID,
399 MCHP_GPIO_0016_ID,
400 MCHP_GPIO_0017_ID,
401 MCHP_GPIO_0020_ID,
402 MCHP_GPIO_0021_ID,
403 MCHP_GPIO_0022_ID,
404 MCHP_GPIO_0023_ID,
405 MCHP_GPIO_0024_ID,
406 MCHP_GPIO_0025_ID,
407 MCHP_GPIO_0026_ID,
408 MCHP_GPIO_0027_ID,
409 MCHP_GPIO_0030_ID,
410 MCHP_GPIO_0031_ID,
411 MCHP_GPIO_0032_ID,
412 MCHP_GPIO_0033_ID,
413 MCHP_GPIO_0034_ID,
414 MCHP_GPIO_0035_ID,
415 MCHP_GPIO_0036_ID, /* Port A bit[30] */
416 MCHP_GPIO_0040_ID = 32u, /* Port B bit[0] */
417 MCHP_GPIO_0042_ID = 34u,
418 MCHP_GPIO_0043_ID,
419 MCHP_GPIO_0044_ID,
420 MCHP_GPIO_0045_ID,
421 MCHP_GPIO_0046_ID,
422 MCHP_GPIO_0047_ID,
423 MCHP_GPIO_0050_ID,
424 MCHP_GPIO_0051_ID,
425 MCHP_GPIO_0052_ID,
426 MCHP_GPIO_0053_ID,
427 MCHP_GPIO_0054_ID,
428 MCHP_GPIO_0055_ID,
429 MCHP_GPIO_0056_ID,
430 MCHP_GPIO_0057_ID,
431 MCHP_GPIO_0060_ID,
432 MCHP_GPIO_0061_ID,
433 MCHP_GPIO_0062_ID,
434 MCHP_GPIO_0063_ID,
435 MCHP_GPIO_0064_ID,
436 MCHP_GPIO_0065_ID,
437 MCHP_GPIO_0066_ID,
438 MCHP_GPIO_0067_ID,
439 MCHP_GPIO_0070_ID,
440 MCHP_GPIO_0071_ID,
441 MCHP_GPIO_0072_ID,
442 MCHP_GPIO_0073_ID, /* Port B bit[27] */
443 MCHP_GPIO_0100_ID = 64u, /* Port C bit[0] */
444 MCHP_GPIO_0101_ID,
445 MCHP_GPIO_0102_ID,
446 MCHP_GPIO_0104_ID = 68u,
447 MCHP_GPIO_0105_ID,
448 MCHP_GPIO_0106_ID,
449 MCHP_GPIO_0107_ID,
450 MCHP_GPIO_0112_ID = 74u,
451 MCHP_GPIO_0113_ID,
452 MCHP_GPIO_0114_ID,
453 MCHP_GPIO_0115_ID,
454 MCHP_GPIO_0120_ID = 80u,
455 MCHP_GPIO_0121_ID,
456 MCHP_GPIO_0122_ID,
457 MCHP_GPIO_0123_ID,
458 MCHP_GPIO_0124_ID,
459 MCHP_GPIO_0125_ID,
460 MCHP_GPIO_0126_ID,
461 MCHP_GPIO_0127_ID,
462 MCHP_GPIO_0130_ID,
463 MCHP_GPIO_0131_ID,
464 MCHP_GPIO_0132_ID, /* Port C bit[26] */
465 MCHP_GPIO_0140_ID = 96u, /* Port D bit[0] */
466 MCHP_GPIO_0141_ID,
467 MCHP_GPIO_0142_ID,
468 MCHP_GPIO_0143_ID,
469 MCHP_GPIO_0144_ID,
470 MCHP_GPIO_0145_ID,
471 MCHP_GPIO_0146_ID,
472 MCHP_GPIO_0147_ID,
473 MCHP_GPIO_0150_ID,
474 MCHP_GPIO_0151_ID,
475 MCHP_GPIO_0152_ID,
476 MCHP_GPIO_0153_ID,
477 MCHP_GPIO_0154_ID,
478 MCHP_GPIO_0155_ID,
479 MCHP_GPIO_0156_ID,
480 MCHP_GPIO_0157_ID,
481 MCHP_GPIO_0161_ID = 113u,
482 MCHP_GPIO_0162_ID,
483 MCHP_GPIO_0163_ID,
484 MCHP_GPIO_0165_ID = 117u,
485 MCHP_GPIO_0170_ID = 120u,
486 MCHP_GPIO_0171_ID,
487 MCHP_GPIO_0172_ID,
488 MCHP_GPIO_0175_ID = 125u, /* Port D bit[29] */
489 MCHP_GPIO_0200_ID = 128u, /* Port E bit[0] */
490 MCHP_GPIO_0201_ID,
491 MCHP_GPIO_0202_ID,
492 MCHP_GPIO_0203_ID,
493 MCHP_GPIO_0204_ID,
494 MCHP_GPIO_0205_ID,
495 MCHP_GPIO_0206_ID,
496 MCHP_GPIO_0207_ID,
497 MCHP_GPIO_0221_ID = 145u,
498 MCHP_GPIO_0222_ID,
499 MCHP_GPIO_0223_ID,
500 MCHP_GPIO_0224_ID,
501 MCHP_GPIO_0226_ID = 150u,
502 MCHP_GPIO_0227_ID, /* Port E bit[22] */
503 MCHP_GPIO_0240_ID = 160u, /* Port F bit[0] */
504 MCHP_GPIO_0241_ID,
505 MCHP_GPIO_0242_ID,
506 MCHP_GPIO_0243_ID,
507 MCHP_GPIO_0244_ID,
508 MCHP_GPIO_0245_ID,
509 MCHP_GPIO_0246_ID,
510 MCHP_GPIO_0250_ID = 168u,
511 MCHP_GPIO_0253_ID = 171u,
512 MCHP_GPIO_0254_ID = 172u,
513 MCHP_GPIO_0255_ID = 173u, /* Port F bit[13] */
514 MCHP_GPIO_MAX_ID
515 };
516
517 #define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5)
518
519 /* =========================================================================*/
520 /* ================ GPIO ================ */
521 /* =========================================================================*/
522
523 /**
524 * @brief GPIO Control (GPIO)
525 */
526 #define MCHP_GPIO_CTRL_BEGIN 0u
527 #define MCHP_GPIO_CTRL_END 0x2c4u
528 #define MCHP_GPIO_PARIN_BEGIN 0x300u
529 #define MCHP_GPIO_PARIN_END 0x318u
530 #define MCHP_GPIO_PAROUT_BEGIN 0x380u
531 #define MCHP_GPIO_PAROUT_END 0x398u
532 #define MCHP_GPIO_LOCK_BEGIN 0x3e8u
533 #define MCHP_GPIO_LOCK_END 0x400u
534 #define MCHP_GPIO_CTRL2_BEGIN 0x500u
535 #define MCHP_GPIO_CTRL2_END 0x7b4u
536
537 #define MAX_MCHP_GPIO_PIN ((MCHP_GPIO_CTRL_END) / 4u)
538 #define MAX_MCHP_GPIO_BANK 6u
539 #define MCHP_GPIO_LOCK5_IDX 0u
540 #define MCHP_GPIO_LOCK4_IDX 1u
541 #define MCHP_GPIO_LOCK3_IDX 2u
542 #define MCHP_GPIO_LOCK2_IDX 3u
543 #define MCHP_GPIO_LOCK1_IDX 4u
544 #define MCHP_GPIO_LOCK0_IDX 5u
545 #define MCHP_GPIO_LOCK_MAX_IDX 6u
546
547 typedef struct gpio_ctrl_regs
548 {
549 __IOM uint32_t CTRL_0000; /*!< (@ 0x0000) GPIO_0000 Control */
550 uint8_t RSVD1[4];
551 __IOM uint32_t CTRL_0002; /*!< (@ 0x0008) GPIO_0002 Control */
552 __IOM uint32_t CTRL_0003; /*!< (@ 0x000c) GPIO_0003 Control */
553 __IOM uint32_t CTRL_0004; /*!< (@ 0x0010) GPIO_0004 Control */
554 uint8_t RSVD2[8];
555 __IOM uint32_t CTRL_0007; /*!< (@ 0x001c) GPIO_0007 Control */
556 __IOM uint32_t CTRL_0010; /*!< (@ 0x0020) GPIO_0010 Control */
557 __IOM uint32_t CTRL_0011;
558 __IOM uint32_t CTRL_0012;
559 __IOM uint32_t CTRL_0013;
560 __IOM uint32_t CTRL_0014; /*!< (@ 0x0030) GPIO_0014 Control */
561 __IOM uint32_t CTRL_0015;
562 __IOM uint32_t CTRL_0016;
563 __IOM uint32_t CTRL_0017;
564 __IOM uint32_t CTRL_0020; /*!< (@ 0x0040) GPIO_0020 Control */
565 __IOM uint32_t CTRL_0021;
566 __IOM uint32_t CTRL_0022;
567 __IOM uint32_t CTRL_0023;
568 __IOM uint32_t CTRL_0024; /*!< (@ 0x0050) GPIO_0024 Control */
569 __IOM uint32_t CTRL_0025;
570 __IOM uint32_t CTRL_0026;
571 __IOM uint32_t CTRL_0027;
572 __IOM uint32_t CTRL_0030; /*!< (@ 0x0060) GPIO_0030 Control */
573 __IOM uint32_t CTRL_0031;
574 __IOM uint32_t CTRL_0032;
575 __IOM uint32_t CTRL_0033;
576 __IOM uint32_t CTRL_0034;
577 __IOM uint32_t CTRL_0035;
578 __IOM uint32_t CTRL_0036; /*!< (@ 0x0078) GPIO_0036 Control */
579 uint8_t RSVD3[4];
580 __IOM uint32_t CTRL_0040; /*!< (@ 0x0080) GPIO_0040 Control */
581 uint8_t RSVD4[4];
582 __IOM uint32_t CTRL_0042; /*!< (@ 0x0088) GPIO_0042 Control */
583 __IOM uint32_t CTRL_0043; /*!< (@ 0x008c) GPIO_0043 Control */
584 __IOM uint32_t CTRL_0044; /*!< (@ 0x0090) GPIO_0044 Control */
585 __IOM uint32_t CTRL_0045;
586 __IOM uint32_t CTRL_0046;
587 __IOM uint32_t CTRL_0047;
588 __IOM uint32_t CTRL_0050; /*!< (@ 0x00a0) GPIO_0050 Control */
589 __IOM uint32_t CTRL_0051;
590 __IOM uint32_t CTRL_0052;
591 __IOM uint32_t CTRL_0053;
592 __IOM uint32_t CTRL_0054; /*!< (@ 0x00b0) GPIO_0054 Control */
593 __IOM uint32_t CTRL_0055;
594 __IOM uint32_t CTRL_0056;
595 __IOM uint32_t CTRL_0057;
596 __IOM uint32_t CTRL_0060; /*!< (@ 0x00c0) GPIO_0060 Control */
597 __IOM uint32_t CTRL_0061;
598 __IOM uint32_t CTRL_0062;
599 __IOM uint32_t CTRL_0063;
600 __IOM uint32_t CTRL_0064; /*!< (@ 0x00d0) GPIO_0064 Control */
601 __IOM uint32_t CTRL_0065;
602 __IOM uint32_t CTRL_0066;
603 __IOM uint32_t CTRL_0067;
604 __IOM uint32_t CTRL_0070; /*!< (@ 0x00e0) GPIO_0070 Control */
605 __IOM uint32_t CTRL_0071;
606 __IOM uint32_t CTRL_0072;
607 __IOM uint32_t CTRL_0073; /*!< (@ 0x00ec) GPIO_0073 Control */
608 uint8_t RSVD5[16];
609 __IOM uint32_t CTRL_0100; /*!< (@ 0x0100) GPIO_0100 Control */
610 __IOM uint32_t CTRL_0101;
611 __IOM uint32_t CTRL_0102;
612 uint8_t RSVD6[4];
613 __IOM uint32_t CTRL_0104; /*!< (@ 0x0110) GPIO_0104 Control */
614 __IOM uint32_t CTRL_0105;
615 __IOM uint32_t CTRL_0106;
616 __IOM uint32_t CTRL_0107; /*!< (@ 0x011c) GPIO_0107 Control */
617 uint8_t RSVD7[8];
618 __IOM uint32_t CTRL_0112; /*!< (@ 0x0128) GPIO_0112 Control */
619 __IOM uint32_t CTRL_0113;
620 __IOM uint32_t CTRL_0114;
621 __IOM uint32_t CTRL_0115; /*!< (@ 0x0134) GPIO_0115 Control */
622 uint8_t RSVD8[8];
623 __IOM uint32_t CTRL_0120; /*!< (@ 0x0140) GPIO_0120 Control */
624 __IOM uint32_t CTRL_0121;
625 __IOM uint32_t CTRL_0122;
626 __IOM uint32_t CTRL_0123;
627 __IOM uint32_t CTRL_0124; /*!< (@ 0x0150) GPIO_0124 Control */
628 __IOM uint32_t CTRL_0125;
629 __IOM uint32_t CTRL_0126;
630 __IOM uint32_t CTRL_0127; /*!< (@ 0x015c) GPIO_0127 Control */
631 __IOM uint32_t CTRL_0130; /*!< (@ 0x0160) GPIO_0130 Control */
632 __IOM uint32_t CTRL_0131; /*!< (@ 0x0164) GPIO_0131 Control */
633 __IOM uint32_t CTRL_0132; /*!< (@ 0x0168) GPIO_0132 Control */
634 uint8_t RSVD9[20];
635 __IOM uint32_t CTRL_0140; /*!< (@ 0x0180) GPIO_0140 Control */
636 __IOM uint32_t CTRL_0141;
637 __IOM uint32_t CTRL_0142;
638 __IOM uint32_t CTRL_0143;
639 __IOM uint32_t CTRL_0144; /*!< (@ 0x0190) GPIO_0144 Control */
640 __IOM uint32_t CTRL_0145;
641 __IOM uint32_t CTRL_0146;
642 __IOM uint32_t CTRL_0147; /*!< (@ 0x019c) GPIO_0147 Control */
643 __IOM uint32_t CTRL_0150; /*!< (@ 0x01a0) GPIO_0150 Control */
644 __IOM uint32_t CTRL_0151;
645 __IOM uint32_t CTRL_0152;
646 __IOM uint32_t CTRL_0153;
647 __IOM uint32_t CTRL_0154; /*!< (@ 0x01b0) GPIO_0154 Control */
648 __IOM uint32_t CTRL_0155;
649 __IOM uint32_t CTRL_0156;
650 __IOM uint32_t CTRL_0157; /*!< (@ 0x01bc) GPIO_0157 Control */
651 uint8_t RSVD10[4];
652 __IOM uint32_t CTRL_0161; /*!< (@ 0x01c4) GPIO_0161 Control */
653 __IOM uint32_t CTRL_0162;
654 __IOM uint32_t CTRL_0163;
655 uint8_t RSVD11[4];
656 __IOM uint32_t CTRL_0165; /*!< (@ 0x01d4) GPIO_0165 Control */
657 uint8_t RSVD12[8];
658 __IOM uint32_t CTRL_0170; /*!< (@ 0x01e0) GPIO_0170 Control */
659 __IOM uint32_t CTRL_0171; /*!< (@ 0x01e4) GPIO_0171 Control */
660 __IOM uint32_t CTRL_0172; /*!< (@ 0x01e8) GPIO_0172 Control */
661 uint8_t RSVD13[8];
662 __IOM uint32_t CTRL_0175; /*!< (@ 0x01f4) GPIO_0175 Control */
663 uint8_t RSVD14[8];
664 __IOM uint32_t CTRL_0200; /*!< (@ 0x0200) GPIO_0200 Control */
665 __IOM uint32_t CTRL_0201;
666 __IOM uint32_t CTRL_0202;
667 __IOM uint32_t CTRL_0203;
668 __IOM uint32_t CTRL_0204; /*!< (@ 0x0210) GPIO_0204 Control */
669 __IOM uint32_t CTRL_0205;
670 __IOM uint32_t CTRL_0206;
671 __IOM uint32_t CTRL_0207; /*!< (@ 0x021c) GPIO_0207 Control */
672 uint8_t RSVD15[36];
673 __IOM uint32_t CTRL_0221; /*!< (@ 0x0244) GPIO_0221 Control */
674 __IOM uint32_t CTRL_0222;
675 __IOM uint32_t CTRL_0223;
676 __IOM uint32_t CTRL_0224; /*!< (@ 0x0250) GPIO_0224 Control */
677 uint8_t RSVD16[4];
678 __IOM uint32_t CTRL_0226;
679 __IOM uint32_t CTRL_0227; /*!< (@ 0x025c) GPIO_0227 Control */
680 uint8_t RSVD17[32];
681 __IOM uint32_t CTRL_0240; /*!< (@ 0x0280) GPIO_0240 Control */
682 __IOM uint32_t CTRL_0241;
683 __IOM uint32_t CTRL_0242;
684 __IOM uint32_t CTRL_0243; /*!< (@ 0x028c) GPIO_0243 Control */
685 __IOM uint32_t CTRL_0244; /*!< (@ 0x0290) GPIO_0244 Control */
686 __IOM uint32_t CTRL_0245; /*!< (@ 0x0294) GPIO_0245 Control */
687 __IOM uint32_t CTRL_0246; /*!< (@ 0x0298) GPIO_0246 Control */
688 uint8_t RSVD18[4];
689 __IOM uint32_t CTRL_0250; /*!< (@ 0x02a0) GPIO_0250 Control */
690 uint8_t RSVD19[8];
691 __IOM uint32_t CTRL_0253; /*!< (@ 0x02ac) GPIO_0253 Control */
692 __IOM uint32_t CTRL_0254; /*!< (@ 0x02b0) GPIO_0254 Control */
693 __IOM uint32_t CTRL_0255; /*!< (@ 0x02b4) GPIO_0255 Control */
694 } GPIO_CTRL_Type;
695
696 typedef struct gpio_ctrl2_regs {
697 __IOM uint32_t CTRL2_0000; /*!< (@ 0x0000) GPIO_0000 Control */
698 uint8_t RSVD1[4];
699 __IOM uint32_t CTRL2_0002; /*!< (@ 0x0008) GPIO_0002 Control */
700 __IOM uint32_t CTRL2_0003; /*!< (@ 0x000c) GPIO_0003 Control */
701 __IOM uint32_t CTRL2_0004; /*!< (@ 0x0010) GPIO_0004 Control */
702 uint8_t RSVD2[8];
703 __IOM uint32_t CTRL2_0007; /*!< (@ 0x001c) GPIO_0007 Control */
704 __IOM uint32_t CTRL2_0010; /*!< (@ 0x0020) GPIO_0010 Control */
705 __IOM uint32_t CTRL2_0011;
706 __IOM uint32_t CTRL2_0012;
707 __IOM uint32_t CTRL2_0013;
708 __IOM uint32_t CTRL2_0014; /*!< (@ 0x0030) GPIO_0014 Control */
709 __IOM uint32_t CTRL2_0015;
710 __IOM uint32_t CTRL2_0016;
711 __IOM uint32_t CTRL2_0017;
712 __IOM uint32_t CTRL2_0020; /*!< (@ 0x0040) GPIO_0020 Control */
713 __IOM uint32_t CTRL2_0021;
714 __IOM uint32_t CTRL2_0022;
715 __IOM uint32_t CTRL2_0023;
716 __IOM uint32_t CTRL2_0024; /*!< (@ 0x0050) GPIO_0024 Control */
717 __IOM uint32_t CTRL2_0025;
718 __IOM uint32_t CTRL2_0026;
719 __IOM uint32_t CTRL2_0027;
720 __IOM uint32_t CTRL2_0030; /*!< (@ 0x0060) GPIO_0030 Control */
721 __IOM uint32_t CTRL2_0031;
722 __IOM uint32_t CTRL2_0032;
723 __IOM uint32_t CTRL2_0033;
724 __IOM uint32_t CTRL2_0034;
725 __IOM uint32_t CTRL2_0035;
726 __IOM uint32_t CTRL2_0036; /*!< (@ 0x0078) GPIO_0036 Control */
727 uint8_t RSVD3[4];
728 __IOM uint32_t CTRL2_0040; /*!< (@ 0x0080) GPIO_0040 Control */
729 uint8_t RSVD4[4];
730 __IOM uint32_t CTRL2_0042; /*!< (@ 0x0088) GPIO_0042 Control */
731 __IOM uint32_t CTRL2_0043; /*!< (@ 0x008c) GPIO_0043 Control */
732 __IOM uint32_t CTRL2_0044; /*!< (@ 0x0090) GPIO_0044 Control */
733 __IOM uint32_t CTRL2_0045;
734 __IOM uint32_t CTRL2_0046;
735 __IOM uint32_t CTRL2_0047;
736 __IOM uint32_t CTRL2_0050; /*!< (@ 0x00a0) GPIO_0050 Control */
737 __IOM uint32_t CTRL2_0051;
738 __IOM uint32_t CTRL2_0052;
739 __IOM uint32_t CTRL2_0053;
740 __IOM uint32_t CTRL2_0054; /*!< (@ 0x00b0) GPIO_0054 Control */
741 __IOM uint32_t CTRL2_0055;
742 __IOM uint32_t CTRL2_0056;
743 __IOM uint32_t CTRL2_0057;
744 __IOM uint32_t CTRL2_0060; /*!< (@ 0x00c0) GPIO_0060 Control */
745 __IOM uint32_t CTRL2_0061;
746 __IOM uint32_t CTRL2_0062;
747 __IOM uint32_t CTRL2_0063;
748 __IOM uint32_t CTRL2_0064; /*!< (@ 0x00d0) GPIO_0064 Control */
749 __IOM uint32_t CTRL2_0065;
750 __IOM uint32_t CTRL2_0066;
751 __IOM uint32_t CTRL2_0067;
752 __IOM uint32_t CTRL2_0070; /*!< (@ 0x00e0) GPIO_0070 Control */
753 __IOM uint32_t CTRL2_0071;
754 __IOM uint32_t CTRL2_0072;
755 __IOM uint32_t CTRL2_0073; /*!< (@ 0x00ec) GPIO_0073 Control */
756 uint8_t RSVD5[16];
757 __IOM uint32_t CTRL2_0100; /*!< (@ 0x0100) GPIO_0100 Control */
758 __IOM uint32_t CTRL2_0101;
759 __IOM uint32_t CTRL2_0102;
760 uint8_t RSVD6[4];
761 __IOM uint32_t CTRL2_0104; /*!< (@ 0x0110) GPIO_0104 Control */
762 __IOM uint32_t CTRL2_0105;
763 __IOM uint32_t CTRL2_0106;
764 __IOM uint32_t CTRL2_0107; /*!< (@ 0x011c) GPIO_0107 Control */
765 uint8_t RSVD7[8];
766 __IOM uint32_t CTRL2_0112; /*!< (@ 0x0128) GPIO_0112 Control */
767 __IOM uint32_t CTRL2_0113;
768 __IOM uint32_t CTRL2_0114;
769 __IOM uint32_t CTRL2_0115; /*!< (@ 0x0134) GPIO_0115 Control */
770 uint8_t RSVD8[8];
771 __IOM uint32_t CTRL2_0120; /*!< (@ 0x0140) GPIO_0120 Control */
772 __IOM uint32_t CTRL2_0121;
773 __IOM uint32_t CTRL2_0122;
774 __IOM uint32_t CTRL2_0123;
775 __IOM uint32_t CTRL2_0124; /*!< (@ 0x0150) GPIO_0124 Control */
776 __IOM uint32_t CTRL2_0125;
777 __IOM uint32_t CTRL2_0126;
778 __IOM uint32_t CTRL2_0127; /*!< (@ 0x015c) GPIO_0127 Control */
779 __IOM uint32_t CTRL2_0130; /*!< (@ 0x0160) GPIO_0130 Control */
780 __IOM uint32_t CTRL2_0131; /*!< (@ 0x0164) GPIO_0131 Control */
781 __IOM uint32_t CTRL2_0132; /*!< (@ 0x0168) GPIO_0132 Control */
782 uint8_t RSVD9[20];
783 __IOM uint32_t CTRL2_0140; /*!< (@ 0x0180) GPIO_0140 Control */
784 __IOM uint32_t CTRL2_0141;
785 __IOM uint32_t CTRL2_0142;
786 __IOM uint32_t CTRL2_0143;
787 __IOM uint32_t CTRL2_0144; /*!< (@ 0x0190) GPIO_0144 Control */
788 __IOM uint32_t CTRL2_0145;
789 __IOM uint32_t CTRL2_0146;
790 __IOM uint32_t CTRL2_0147; /*!< (@ 0x019c) GPIO_0147 Control */
791 __IOM uint32_t CTRL2_0150; /*!< (@ 0x01a0) GPIO_0150 Control */
792 __IOM uint32_t CTRL2_0151;
793 __IOM uint32_t CTRL2_0152;
794 __IOM uint32_t CTRL2_0153;
795 __IOM uint32_t CTRL2_0154; /*!< (@ 0x01b0) GPIO_0154 Control */
796 __IOM uint32_t CTRL2_0155;
797 __IOM uint32_t CTRL2_0156;
798 __IOM uint32_t CTRL2_0157; /*!< (@ 0x01bc) GPIO_0157 Control */
799 uint8_t RSVD10[4];
800 __IOM uint32_t CTRL2_0161; /*!< (@ 0x01c4) GPIO_0161 Control */
801 __IOM uint32_t CTRL2_0162;
802 __IOM uint32_t CTRL2_0163;
803 uint8_t RSVD11[4];
804 __IOM uint32_t CTRL2_0165; /*!< (@ 0x01d4) GPIO_0165 Control */
805 uint8_t RSVD12[8];
806 __IOM uint32_t CTRL2_0170; /*!< (@ 0x01e0) GPIO_0170 Control */
807 __IOM uint32_t CTRL2_0171; /*!< (@ 0x01e4) GPIO_0171 Control */
808 __IOM uint32_t CTRL2_0172; /*!< (@ 0x01e8) GPIO_0172 Control */
809 uint8_t RSVD13[8];
810 __IOM uint32_t CTRL2_0175; /*!< (@ 0x01f4) GPIO_0175 Control */
811 uint8_t RSVD14[8];
812 __IOM uint32_t CTRL2_0200; /*!< (@ 0x0200) GPIO_0200 Control */
813 __IOM uint32_t CTRL2_0201;
814 __IOM uint32_t CTRL2_0202;
815 __IOM uint32_t CTRL2_0203;
816 __IOM uint32_t CTRL2_0204; /*!< (@ 0x0210) GPIO_0204 Control */
817 __IOM uint32_t CTRL2_0205;
818 __IOM uint32_t CTRL2_0206;
819 __IOM uint32_t CTRL2_0207; /*!< (@ 0x021c) GPIO_0207 Control */
820 uint8_t RSVD15[36];
821 __IOM uint32_t CTRL2_0221; /*!< (@ 0x0244) GPIO_0221 Control */
822 __IOM uint32_t CTRL2_0222;
823 __IOM uint32_t CTRL2_0223;
824 __IOM uint32_t CTRL2_0224; /*!< (@ 0x0250) GPIO_0224 Control */
825 uint8_t RSVD16[4];
826 __IOM uint32_t CTRL2_0226;
827 __IOM uint32_t CTRL2_0227; /*!< (@ 0x025c) GPIO_0227 Control */
828 uint8_t RSVD17[32];
829 __IOM uint32_t CTRL2_0240; /*!< (@ 0x0280) GPIO_0240 Control */
830 __IOM uint32_t CTRL2_0241;
831 __IOM uint32_t CTRL2_0242;
832 __IOM uint32_t CTRL2_0243; /*!< (@ 0x028c) GPIO_0243 Control */
833 __IOM uint32_t CTRL2_0244; /*!< (@ 0x0290) GPIO_0244 Control */
834 __IOM uint32_t CTRL2_0245; /*!< (@ 0x0294) GPIO_0245 Control */
835 __IOM uint32_t CTRL2_0246; /*!< (@ 0x0298) GPIO_0246 Control */
836 uint8_t RSVD18[4];
837 __IOM uint32_t CTRL2_0250; /*!< (@ 0x02a0) GPIO_0250 Control */
838 uint8_t RSVD19[8];
839 __IOM uint32_t CTRL2_0253; /*!< (@ 0x02ac) GPIO_0253 Control */
840 __IOM uint32_t CTRL2_0254; /*!< (@ 0x02b0) GPIO_0254 Control */
841 __IOM uint32_t CTRL2_0255; /*!< (@ 0x02b4) GPIO_0255 Control */
842 } GPIO_CTRL2_Type;
843
844 typedef struct gpio_parin_regs {
845 __IOM uint32_t PARIN0; /*!< (@ 0x0000) GPIO Parallel Input [0000:0036] */
846 __IOM uint32_t PARIN1; /*!< (@ 0x0004) GPIO Parallel Input [0040:0076] */
847 __IOM uint32_t PARIN2; /*!< (@ 0x0008) GPIO Parallel Input [0100:0136] */
848 __IOM uint32_t PARIN3; /*!< (@ 0x000c) GPIO Parallel Input [0140:0176] */
849 __IOM uint32_t PARIN4; /*!< (@ 0x0010) GPIO Parallel Input [0200:0236] */
850 __IOM uint32_t PARIN5; /*!< (@ 0x0014) GPIO Parallel Input [0240:0276] */
851 } GPIO_PARIN_Type;
852
853 typedef struct gpio_parout_regs {
854 __IOM uint32_t PAROUT0; /*!< (@ 0x0000) GPIO Parallel Output [0000:0036] */
855 __IOM uint32_t PAROUT1; /*!< (@ 0x0004) GPIO Parallel Output [0040:0076] */
856 __IOM uint32_t PAROUT2; /*!< (@ 0x0008) GPIO Parallel Output [0100:0136] */
857 __IOM uint32_t PAROUT3; /*!< (@ 0x000c) GPIO Parallel Output [0140:0176] */
858 __IOM uint32_t PAROUT4; /*!< (@ 0x0010) GPIO Parallel Output [0200:0236] */
859 __IOM uint32_t PAROUT5; /*!< (@ 0x0014) GPIO Parallel Output [0240:0276] */
860 } GPIO_PAROUT_Type;
861
862 typedef struct gpio_lock_regs {
863 __IOM uint32_t LOCK5; /*!< (@ 0x0000) GPIO Lock 5 */
864 __IOM uint32_t LOCK4; /*!< (@ 0x0004) GPIO Lock 4 */
865 __IOM uint32_t LOCK3; /*!< (@ 0x0008) GPIO Lock 3 */
866 __IOM uint32_t LOCK2; /*!< (@ 0x000c) GPIO Lock 2 */
867 __IOM uint32_t LOCK1; /*!< (@ 0x0010) GPIO Lock 1 */
868 __IOM uint32_t LOCK0; /*!< (@ 0x0014) GPIO Lock 0 */
869 } GPIO_LOCK_Type;
870
871 /*
872 * Helper functions
873 */
874 enum mchp_gpio_pud {
875 MCHP_GPIO_NO_PUD = 0u,
876 MCHP_GPIO_PU_EN = 1u,
877 MCHP_GPIO_PD_EN = 2u,
878 MCHP_GPIO_RPT_EN = 3u,
879 };
880
881 enum mchp_gpio_pwrgate {
882 MCHP_GPIO_PWRGT_VTR = 0u,
883 MCHP_GPIO_PWRGT_VCC = 1u,
884 MCHP_GPIO_PWRGD_OFF = 2u,
885 };
886
887 enum mchp_gpio_idet {
888 MCHP_GPIO_IDET_LO_LVL = 0x00u,
889 MCHP_GPIO_IDET_HI_LVL = 0x01u,
890 MCHP_GPIO_IDET_DIS = 0x04u,
891 MCHP_GPIO_IDET_RISING_EDGE = 0x0du,
892 MCHP_GPIO_IDET_FALLING_EDGE = 0x0eu,
893 MCHP_GPIO_IDET_BOTH_EDGES = 0x0fu
894 };
895
896 enum mchp_gpio_outbuf {
897 MCHP_GPIO_PUSH_PULL = 0u,
898 MCHP_GPIO_OPEN_DRAIN = 1u,
899 };
900
901 enum mchp_gpio_dir {
902 MCHP_GPIO_DIR_IN = 0u,
903 MCHP_GPIO_DIR_OUT = 1u,
904 };
905
906 enum mchp_gpio_parout_en {
907 MCHP_GPIO_PAROUT_DIS = 0u,
908 MCHP_GPIO_PAROUT_EN = 1u,
909 };
910
911 enum mchp_gpio_pol {
912 MCHP_GPIO_POL_NORM = 0u,
913 MCHP_GPIO_POL_INV = 1u,
914 };
915
916 enum mchp_gpio_mux {
917 MCHP_GPIO_MUX_GPIO = 0u,
918 MCHP_GPIO_MUX_FUNC1,
919 MCHP_GPIO_MUX_FUNC2,
920 MCHP_GPIO_MUX_FUNC3,
921 MCHP_GPIO_MUX_MAX
922 };
923
924 enum mchp_gpio_inpad_ctrl {
925 MCHP_GPIO_INPAD_CTRL_EN = 0u,
926 MCHP_GPIO_INPAD_CTRL_DIS = 1u,
927 };
928
929 enum mchp_gpio_alt_out {
930 MCHP_GPIO_ALT_OUT_LO = 0u,
931 MCHP_GPIO_ALT_OUT_HI = 1u,
932 };
933
934 enum mchp_gpio_slew {
935 MCHP_GPIO_SLEW_SLOW = 0u,
936 MCHP_GPIO_SLEW_FAST = 1u,
937 };
938
939 enum mchp_gpio_drv_str {
940 MCHP_GPIO_DRV_STR_2MA = 0u,
941 MCHP_GPIO_DRV_STR_4MA = 1u,
942 MCHP_GPIO_DRV_STR_8MA = 2u,
943 MCHP_GPIO_DRV_STR_12MA = 3u,
944 };
945
946 static __attribute__ ((always_inline)) inline void
mchp_gpio_pud_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_pud pud)947 mchp_gpio_pud_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_pud pud)
948 {
949 REG32(gp_ctrl_addr) =
950 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_PUD_MASK))
951 | (((uint32_t) pud << MCHP_GPIO_CTRL_PUD_POS)
952 & MCHP_GPIO_CTRL_PUD_MASK);
953 }
954
955 static __attribute__ ((always_inline)) inline void
mchp_gpio_pwrgt_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_pwrgate pwrgt)956 mchp_gpio_pwrgt_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_pwrgate pwrgt)
957 {
958 REG32(gp_ctrl_addr) =
959 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_PWRG_MASK))
960 | (((uint32_t) pwrgt << MCHP_GPIO_CTRL_PWRG_POS)
961 & MCHP_GPIO_CTRL_PWRG_MASK);
962 }
963
964 static __attribute__ ((always_inline)) inline void
mchp_gpio_idet_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_idet idet)965 mchp_gpio_idet_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_idet idet)
966 {
967 REG32(gp_ctrl_addr) =
968 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_IDET_MASK))
969 | (((uint32_t) idet << MCHP_GPIO_CTRL_IDET_POS)
970 & MCHP_GPIO_CTRL_IDET_MASK);
971 }
972
973 static __attribute__ ((always_inline)) inline void
mchp_gpio_outbuf_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_outbuf outbuf)974 mchp_gpio_outbuf_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_outbuf outbuf)
975 {
976 REG32(gp_ctrl_addr) =
977 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_BUFT_MASK))
978 | (((uint32_t) outbuf << MCHP_GPIO_CTRL_BUFT_POS)
979 & MCHP_GPIO_CTRL_BUFT_MASK);
980 }
981
982 static __attribute__ ((always_inline)) inline void
mchp_gpio_dir_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_dir dir)983 mchp_gpio_dir_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_dir dir)
984 {
985 REG32(gp_ctrl_addr) =
986 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_DIR_MASK))
987 | (((uint32_t) dir << MCHP_GPIO_CTRL_DIR_POS)
988 & MCHP_GPIO_CTRL_DIR_MASK);
989 }
990
991 static __attribute__ ((always_inline)) inline void
mchp_gpio_parout_en_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_parout_en parout_en)992 mchp_gpio_parout_en_set(uintptr_t gp_ctrl_addr,
993 enum mchp_gpio_parout_en parout_en)
994 {
995 REG32(gp_ctrl_addr) =
996 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_AOD_MASK))
997 | (((uint32_t) parout_en << MCHP_GPIO_CTRL_AOD_POS)
998 & MCHP_GPIO_CTRL_AOD_MASK);
999 }
1000
1001 static __attribute__ ((always_inline)) inline void
mchp_gpio_pol_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_pol pol)1002 mchp_gpio_pol_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_pol pol)
1003 {
1004 REG32(gp_ctrl_addr) =
1005 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_POL_MASK))
1006 | (((uint32_t) pol << MCHP_GPIO_CTRL_POL_POS)
1007 & MCHP_GPIO_CTRL_POL_MASK);
1008 }
1009
1010 static __attribute__ ((always_inline)) inline void
mchp_gpio_mux_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_mux mux)1011 mchp_gpio_mux_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_mux mux)
1012 {
1013 REG32(gp_ctrl_addr) =
1014 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_MUX_MASK))
1015 | (((uint32_t) mux << MCHP_GPIO_CTRL_MUX_POS)
1016 & MCHP_GPIO_CTRL_MUX_MASK);
1017 }
1018
1019 static __attribute__ ((always_inline)) inline void
mchp_gpio_inpad_ctrl_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_inpad_ctrl inpad_ctrl)1020 mchp_gpio_inpad_ctrl_set(uintptr_t gp_ctrl_addr,
1021 enum mchp_gpio_inpad_ctrl inpad_ctrl)
1022 {
1023 REG32(gp_ctrl_addr) =
1024 (REG32(gp_ctrl_addr) & ~(MCHP_GPIO_CTRL_INPAD_DIS_MASK))
1025 | (((uint32_t) inpad_ctrl << MCHP_GPIO_CTRL_INPAD_DIS_POS)
1026 & MCHP_GPIO_CTRL_INPAD_DIS_MASK);
1027 }
1028
1029 static __attribute__ ((always_inline)) inline void
mchp_gpio_alt_out_set(uintptr_t gp_ctrl_addr,enum mchp_gpio_alt_out aout_state)1030 mchp_gpio_alt_out_set(uintptr_t gp_ctrl_addr, enum mchp_gpio_alt_out aout_state)
1031 {
1032 REG8(gp_ctrl_addr + 2u) =
1033 (uint8_t) aout_state & MCHP_GPIO_CTRL_OUTVAL_MASK0;
1034 }
1035
1036 static __attribute__ ((always_inline)) inline uint8_t
mchp_gpio_inpad_val_get(uintptr_t gp_ctrl_addr,enum mchp_gpio_alt_out aout_state)1037 mchp_gpio_inpad_val_get(uintptr_t gp_ctrl_addr, enum mchp_gpio_alt_out aout_state)
1038 {
1039 return REG8(gp_ctrl_addr + 3u) & MCHP_GPIO_CTRL_INPAD_VAL_MASK0;
1040 }
1041
1042 #endif /* #ifndef _GPIO_H */
1043 /* end gpio.h */
1044 /** @}
1045 */
1046
