1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file global_cfg.h 28 *MEC1501 Global Configuration Registers 29 */ 30 /** @defgroup MEC1501 Peripherals GlobalConfig 31 */ 32 33 #ifndef _GLOBAL_CFG_H 34 #define _GLOBAL_CFG_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* ===================================================================*/ 42 /* ================ Global Config ============= */ 43 /* ===================================================================*/ 44 45 #define MCHP_GCFG_BASE_ADDR 0x400fff00u 46 47 /* 48 * Device and Revision ID 32-bit register 49 * b[7:0] = Revision 50 * b[15:8] = Device Sub-ID 51 * b[31:16] = Device ID 52 * This register can be accesses as bytes or a single 32-bit read from 53 * the EC. Host access byte access via the Host visible configuration 54 * register space at 0x2e/0x2f(default). 55 */ 56 #define MCHP_GCFG_DEV_ID_REG32_OFS 0x1c 57 #define MCHP_GCFG_DEV_ID_REG_MASK 0xffffffffu 58 #define MCHP_GCFG_REV_ID_POS 0 59 #define MCHP_GCFG_DID_REV_MASK0 0xffu 60 #define MCHP_GCFG_DID_REV_MASK 0xffu 61 #define MCHP_GCFG_DID_SUB_ID_POS 8 62 #define MCHP_GCFG_DID_SUB_ID_MASK0 0xffu 63 #define MCHP_GCFG_DID_SUB_ID_MASK (0xffu << 8) 64 #define MCHP_GCFG_DID_DEV_ID_POS 16 65 #define MCHP_GCFG_DID_DEV_ID_MASK0 0xffffu 66 #define MCHP_GCFG_DID_DEV_ID_MASK (0xffffu << 16) 67 68 /* Byte[0] at offset 0x1c is the 8-bit revision ID */ 69 #define MCHP_GCFG_REV_ID_REG_OFS 0x1c 70 #define MCHP_GCFG_REV_A1 0x02 71 #define MCHP_GCFG_REV_B0 0x03 72 73 /* 74 * Byte[1] at offset 0x1d is the 8-bit Sub-ID 75 * bits[3:0] = package type 76 * bits[7:4] = chip family 77 */ 78 #define MCHP_GCFG_SUB_ID_OFS 0x1d 79 #define MCHP_GCFG_SUB_ID_PKG_POS 0 80 #define MCHP_GCFG_SUB_ID_PKG_MASK0 0x0f 81 #define MCHP_GCFG_SUB_ID_PKG_MASK 0x0f 82 #define MCHP_GCFG_SUB_ID_PKG_UNDEF 0x00 83 #define MCHP_GCFG_SUB_ID_PKG_64_PIN 0x01 84 #define MCHP_GCFG_SUB_ID_PKG_84_PIN 0x02 85 #define MCHP_GCFG_SUB_ID_PKG_128_PIN 0x03 86 #define MCHP_GCFG_SUB_ID_PKG_144_PIN 0x04 87 /* chip family field */ 88 #define MCHP_GCFG_SUB_ID_FAM_POS 4 89 #define MCHP_GCFG_SUB_ID_FAM_MASK0 0x0f 90 #define MCHP_GCFG_SUB_ID_FAM_MASK 0xf0 91 #define MCHP_GCFG_SUB_ID_FAM_UNDEF 0x00 92 #define MCHP_GCFG_SUB_ID_FAM_MEC 0x01 93 #define MCHP_GCFG_SUB_ID_FAM_2 0x02 94 #define MCHP_GCFG_SUB_ID_FAM_3 0x03 95 #define MCHP_GCFG_SUB_ID_FAM_4 0x04 96 #define MCHP_GCFG_SUB_ID_FAM_5 0x05 97 98 #define MCHP_GCFG_DEV_ID_LSB_OFS 0x1e 99 #define MCHP_GCFG_DEV_ID_MSB_OFS 0x1f 100 #define MCHP_GCFG_DEV_ID_15XX 0x0020 101 #define MCHP_GCFG_DEV_ID_15XX_LSB 0x20 102 #define MCHP_GCFG_DEV_ID_15XX_MSB 0x00 103 104 /* Legacy Device ID value */ 105 #define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20 106 #define MCHP_GCFG_LEGACY_DEV_ID 0xfe 107 108 /* 109 * Host access via configuration port (default I/O locations 0x2e/0x2f) 110 */ 111 #define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2e 112 #define MCHP_HOST_CFG_DATA_IO_DFLT 0x2f 113 #define MCHP_HOST_CFG_UNLOCK 0x55 114 #define MCHP_HOST_CFG_LOCK 0xaa 115 /* 116 * Logical Device Configuration Indices. 117 */ 118 #define MCHP_HOST_CFG_LDN_IDX 0x07 119 #define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30 120 #define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34 121 #define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xf0 122 123 124 /* Read 32-bit Device, Sub, and Revision ID */ 125 #define MCHP_DEVICE_REV_ID() \ 126 REG32(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_REG32_OFS) 127 128 /* Read 16-bit Device ID */ 129 #define MCHP_DEVICE_ID() \ 130 REG16(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_LSB_OFS) 131 132 /* Read 8-bit Sub ID */ 133 #define MCHP_DEV_SUB_ID() \ 134 REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_SUB_ID_OFS) 135 136 /* Read 8-bit Revision ID */ 137 #define MCHP_REVISION_ID() \ 138 REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_REV_ID_REG_OFS) 139 140 /** 141 * @brief Glocal Configuration Registers (GLOBAL_CFG) 142 */ 143 typedef struct global_cfg_regs 144 { 145 __IOM uint8_t RSVD0[2]; 146 __IOM uint8_t TEST02; /*!< (@ 0x0002) MCHP Test */ 147 __IOM uint8_t RSVD1[4]; 148 __IOM uint8_t LOG_DEV_NUM; /*!< (@ 0x0007) Global Config Logical Device Number */ 149 __IOM uint8_t RSVD2[20]; 150 __IOM uint32_t DEV_REV_ID; /*!< (@ 0x001c) Device and revision ID */ 151 __IOM uint8_t LEGACY_DEV_ID; /*!< (@ 0x0020) Legacy Device ID */ 152 __IOM uint8_t RSVD3[14]; 153 } GLOBAL_CFG_Type; 154 155 #endif /* #ifndef _GLOBAL_CFG_H */ 156 /* end global_cfg.h */ 157 /** @} 158 */ 159
