1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file ecs.h 28 *MEC1501 EC Subsystem (ECS) registers 29 */ 30 /** @defgroup MEC1501 Peripherals ECS 31 */ 32 33 #include <stdint.h> 34 #include <stddef.h> 35 36 #include "regaccess.h" 37 38 #ifndef _ECS_H 39 #define _ECS_H 40 41 /* =========================================================================*/ 42 /* ================ ECS ================ */ 43 /* =========================================================================*/ 44 45 #define MCHP_ECS_BASE_ADDR 0x4000fc00u 46 47 /* AHB Error Address, write any value to clear */ 48 #define MCHP_ECS_AHB_ERR_ADDR_OFS 0x04u 49 50 /* AHB Error Control */ 51 #define MCHP_ECS_AHB_ERR_CTRL_OFS 0x14u 52 #define MCHP_ECS_AHB_ERR_CTRL_DIS_POS 0u 53 #define MCHP_ECS_AHB_ERR_CTRL_DIS BIT(MCHP_ECS_AHB_ERR_CTRL_DIS_POS) 54 55 /* Interrupt Control */ 56 #define MCHP_ECS_ICTRL_OFS 0x18u 57 #define MCHP_ECS_ICTRL_DIRECT_POS 0 58 #define MCHP_ECS_ICTRL_DIRECT_EN BIT(MCHP_ECS_ICTRL_DIRECT_POS) 59 60 /* ETM Control Register */ 61 #define MCHP_ECS_ETM_CTRL_OFS 0x1cu 62 #define MCHP_ECS_ETM_CTRL_EN_POS 0 63 #define MCHP_ECS_ETM_CTRL_EN BIT(MCHP_ECS_ETM_CTRL_EN_POS) 64 65 /* Debug Control Register */ 66 #define MCHP_ECS_DCTRL_OFS 0x20u 67 #define MCHP_ECS_DCTRL_MASK 0x1fu 68 #define MCHP_ECS_DCTRL_DBG_EN_POS 0u 69 #define MCHP_ECS_DCTRL_DBG_EN BIT(MCHP_ECS_DCTRL_DBG_EN_POS) 70 #define MCHP_ECS_DCTRL_MODE_POS 1u 71 #define MCHP_ECS_DCTRL_MODE_MASK0 0x03u 72 #define MCHP_ECS_DCTRL_MODE_MASK \ 73 ((MCHP_ECS_DCTRL_DBG_MODE_MASK0) << (MCHP_ECS_DCTRL_DBG_MODE_POS)) 74 75 #define MCHP_ECS_DCTRL_DBG_MODE_POS 1u 76 #define MCHP_ECS_DCTRL_MODE_JTAG (0x00 << (MCHP_ECS_DCTRL_DBG_MODE_POS)) 77 #define MCHP_ECS_DCTRL_MODE_SWD (0x02 << (MCHP_ECS_DCTRL_DBG_MODE_POS)) 78 #define MCHP_ECS_DCTRL_MODE_SWD_SWV (0x01 << (MCHP_ECS_DCTRL_DBG_MODE_POS)) 79 #define MCHP_ECS_DCTRL_PUEN_POS 3u 80 #define MCHP_ECS_DCTRL_PUEN BIT(MCHP_ECS_DCTRL_PUEN_POS) 81 #define MCHP_ECS_DCTRL_BSCAN_POS 4u 82 #define MCHP_ECS_DCTRL_BSCAN_EN BIT(MCHP_ECS_DCTRL_BSCAN_POS) 83 84 /* AES Hash Byte Swap Control Register */ 85 #define MCHP_ECS_AHSW_OFS 0x2cu 86 #define MCHP_ECS_AHSW_MASK 0xffu 87 #define MCHP_ECS_DW_SWAP_IN_POS 0u 88 #define MCHP_ECS_DW_SWAP_IN_EN BIT(MCHP_ECS_DW_SWAP_IN_POS) 89 #define MCHP_ECS_DW_SWAP_OUT_POS 1u 90 #define MCHP_ECS_DW_SWAP_OUT_EN BIT(MCHP_ECS_DW_SWAP_OUT_POS) 91 #define MCHP_ECS_BLK_SWAP_IN_POS 2u 92 #define MCHP_ECS_BLK_SWAP_IN_MASK (0x07u << (MCHP_ECS_BLK_SWAP_IN_POS)) 93 #define MCHP_ECS_BLK_SWAP_IN_DIS (0x00u << (MCHP_ECS_BLK_SWAP_IN_POS)) 94 #define MCHP_ECS_BLK_SWAP_IN_8B (0x01u << (MCHP_ECS_BLK_SWAP_IN_POS)) 95 #define MCHP_ECS_BLK_SWAP_IN_16B (0x02u << (MCHP_ECS_BLK_SWAP_IN_POS)) 96 #define MCHP_ECS_BLK_SWAP_IN_64B (0x03u << (MCHP_ECS_BLK_SWAP_IN_POS)) 97 #define MCHP_ECS_BLK_SWAP_IN_128B (0x04u << (MCHP_ECS_BLK_SWAP_IN_POS)) 98 #define MCHP_ECS_BLK_SWAP_OUT_POS 5u 99 #define MCHP_ECS_BLK_SWAP_OUT_MASK (0x07u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 100 #define MCHP_ECS_BLK_SWAP_OUT_DIS (0x00u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 101 #define MCHP_ECS_BLK_SWAP_OUT_8B (0x01u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 102 #define MCHP_ECS_BLK_SWAP_OUT_16B (0x02u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 103 #define MCHP_ECS_BLK_SWAP_OUT_64B (0x03u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 104 #define MCHP_ECS_BLK_SWAP_OUT_128B (0x04u << (MCHP_ECS_BLK_SWAP_OUT_POS)) 105 106 /* ECS PECI disable register */ 107 #define MCHP_ECS_PECI_DIS_REG_OFS 0x40u 108 #define MCHP_ECS_PECI_DIS_POS 0u 109 #define MCHP_ECS_PECI_DISABLE BIT(MCHP_ECS_PECI_DIS_POS) 110 111 /* ECS VCI FW Override */ 112 #define MCHP_ECS_VCI_FWO_OFS 0x50u 113 #define MCHP_ECS_VCI_FWO_SYS_SHDN_POS 0u 114 #define MCHP_ECS_VCI_FWO_SYS_SHDN BIT(MCHP_ECS_VCI_FWO_SYS_SHDN_POS) 115 116 /* EC Subystem GPIO Bank Power */ 117 #define MCHP_ECS_GBPWR_OFS 0x64u 118 #define MCHP_ECS_GBPWR_LOCK_POS 7u 119 #define MCHP_ECS_GBPWR_LOCK BIT(MCHP_ECS_GBPWR_LOCK_POS) 120 #define MCHP_ECS_VTR3_LVL_POS 2u 121 #define MCHP_ECS_VTR3_LVL_18 BIT(MCHP_ECS_VTR3_LVL_POS) 122 #define MCHP_ECS_VTR2_LVL_POS 1u 123 #define MCHP_ECS_VTR2_LVL_18 BIT(MCHP_ECS_VTR2_LVL_POS) 124 125 /* ECS Virtual Wire Source Configuration */ 126 #define MCHP_ECS_VWSC_OFS 0x90u 127 #define MCHP_ECS_VWSC_MASK 0x07u 128 #define MCHP_ECS_VWSC_DFLT 0x07u 129 #define MCHP_ECS_VWSC_EC_SCI_DIS BIT(0) 130 #define MCHP_ECS_VWSC_MBH_SMI_DIS BIT(1) 131 132 /* ECS Analog Comparator Control register */ 133 #define MCHP_ECS_ACC_OFS 0x94u 134 #define MCHP_ECS_ACC_MASK 0x15u 135 #define MCHP_ECS_ACC_EN0 BIT(0) 136 #define MCHP_ECS_ACC_CFG_LOCK0 BIT(2) 137 #define MCHP_ECS_ACC_EN1 BIT(4) 138 139 /* ECS Analog Comparator Sleep Control register */ 140 #define MCHP_ECS_ACSC_OFS 0x98u 141 #define MCHP_ECS_ACSC_MASK 0x03u 142 #define MCHP_ECS_ACSC_DSLP_EN0 BIT(0) 143 #define MCHP_ECS_ACSC_DSLP_EN1 BIT(1) 144 145 /* Register Access */ 146 #define MCHP_ECS_AHB_ERR() \ 147 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_ADDR_OFS) 148 149 #define MCHP_ECS_AHB_ERR_CTRL() \ 150 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_CTRL_OFS) 151 152 #define MCHP_ECS_ICTRL() \ 153 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ICTRL_OFS) 154 155 #define MCHP_ECS_ETM_CTRL() \ 156 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ETM_CTRL_OFS) 157 158 #define MCHP_ECS_DCTRL() \ 159 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_DCTRL_OFS) 160 161 #define MCHP_ECS_AHSW_CTRL() \ 162 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHSW_OFS) 163 164 #define MCHP_ECS_GBPWR() \ 165 REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_GBPWR_OFS) 166 167 /** 168 * @brief EC Subsystem (ECS) 169 */ 170 typedef struct ecs_regs 171 { /*!< (@ 0x4000fc00) ECS Structure */ 172 __IOM uint8_t RSVD1[4]; 173 __IOM uint32_t AHB_ERR_ADDR; /*!< (@ 0x0004) ECS AHB Error Address */ 174 __IOM uint32_t TEST08; 175 __IOM uint32_t TEST0C; 176 __IOM uint32_t TEST10; 177 __IOM uint32_t AHB_ERR_CTRL; /*!< (@ 0x0014) ECS AHB Error Control */ 178 __IOM uint32_t INTR_CTRL; /*!< (@ 0x0018) ECS Interupt Control */ 179 __IOM uint32_t ETM_CTRL; /*!< (@ 0x001c) ECS ETM Trace Control */ 180 __IOM uint32_t DEBUG_CTRL; /*!< (@ 0x0020) ECS Debug Control */ 181 __IOM uint32_t OTP_LOCK; /*!< (@ 0x0024) ECS OTP Lock Enable */ 182 __IOM uint32_t WDT_CNT; /*!< (@ 0x0028) ECS WDT Event Count */ 183 __IOM uint32_t AESH_BSWAP_CTRL; /*!< (@ 0x002c) ECS AES-Hash Byte Swap Control */ 184 __IOM uint32_t TEST30; 185 __IOM uint32_t TEST34; 186 __IOM uint32_t RSVD38; 187 __IOM uint32_t TEST3C; 188 __IOM uint32_t PECI_DIS; /*!< (@ 0x0040) ECS PECI Disable */ 189 __IOM uint32_t RSVD44; 190 __IOM uint32_t RSVD48; 191 __IOM uint32_t RSVD4C; 192 __IOM uint32_t VCI_FW_OVR; /*!< (@ 0x0050) ECS VCI FW Override */ 193 __IOM uint32_t BROM_STS; /*!< (@ 0x0054) ECS Boot-ROM Status */ 194 uint8_t RSVD2[4]; 195 __IOM uint32_t CRYPTO_SRST; /*!< (@ 0x005c) ECS Crypto HW Soft Reset */ 196 __IOM uint32_t TEST60; 197 __IOM uint32_t GPIO_BANK_PWR; /*!< (@ 0x0064) ECS GPIO Bank Power Select */ 198 __IOM uint32_t TEST68; 199 __IOM uint32_t TEST6C; 200 __IOM uint32_t JTAG_MCFG; /*!< (@ 0x0070) ECS JTAG Master Config */ 201 __IOM uint32_t JTAG_MSTS; /*!< (@ 0x0074) ECS JTAG Master Status */ 202 __IOM uint32_t JTAG_MTDO; /*!< (@ 0x0078) ECS JTAG Master TDO */ 203 __IOM uint32_t JTAG_MTDI; /*!< (@ 0x007c) ECS JTAG Master TDI */ 204 __IOM uint32_t JTAG_MTMS; /*!< (@ 0x0080) ECS JTAG Master TMS */ 205 __IOM uint32_t JTAG_MCMD; /*!< (@ 0x0084) ECS JTAG Master Command */ 206 uint8_t RSVD3[8]; 207 __IOM uint32_t VW_FW_OVR; /*!< (@ 0x0090) ECS VWire Source Config */ 208 __IOM uint32_t CMP_CTRL; /*!< (@ 0x0094) ECS Analog Comparator Control */ 209 __IOM uint32_t CMP_SLP_CTRL; /*!< (@ 0x0098) ECS Analog Comparator Sleep Control */ 210 uint8_t RSVD4[(0x144 - 0x9c)]; 211 __IOM uint32_t SLP_STS_MIRROR; /*!< (@ 0x0144) ECS Sleep Status Mirror (RO) */ 212 uint8_t RSVD5[(0x180 - 0x148)]; 213 __IOM uint32_t BROM_SCR0; /*!< (@ 0x0180) ECS Boot-ROM Scratch 0 */ 214 __IOM uint32_t BROM_SCR1; /*!< (@ 0x0184) ECS Boot-ROM Scratch 1 */ 215 __IOM uint32_t BROM_SCR2; /*!< (@ 0x0188) ECS Boot-ROM Scratch 2 */ 216 __IOM uint32_t BROM_SCR3; /*!< (@ 0x018c) ECS Boot-ROM Scratch 3 */ 217 } ECS_Type; 218 219 #endif /* #ifndef _ECS_H */ 220 /* end ecs.h */ 221 /** @} 222 */ 223
