1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file dma.h 28 *MEC1501 DMA controller definitions 29 */ 30 /** @defgroup MEC1501 Peripherals DMA 31 */ 32 33 #ifndef _DMA_H 34 #define _DMA_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 #include <stdbool.h> 39 40 #include "regaccess.h" 41 42 #define MCHP_NUM_DMA_CHANNELS 12u 43 44 #define MCHP_DMA_BLOCK_BASE_ADDR 0x40002400u 45 #define MCHP_DMA_CHAN_OFFSET 0x40u 46 #define MCHP_DMA_OFFSET_POF2 6u 47 #define MCHP_DMA_CHAN0_ADDR \ 48 ((MCHP_DMA_BLOCK_BASE_ADDR) + (MCHP_DMA_CHAN_OFFSET)) 49 50 #define MCHP_DMA_CHAN_ADDR(n) ((uintptr_t)(MCHP_DMA_CHAN0_ADDR) +\ 51 ((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2)) 52 53 /* 54 * DMA block PCR register and bit 55 * Bit position applied to PCR Sleep Enable, Clock Req(RO), and Reset 56 * registers. 57 */ 58 #define MCHP_DMA_PCR_SLP_EN_ADDR 0x40080134u 59 #define MCHP_DMA_PCR_CLK_REQ_ADDR 0x40080154u 60 #define MCHP_DMA_PCR_RST_ADDR 0x40080174u 61 #define MCHP_DMA_PCR_SCR_POS 6u 62 #define MCHP_DMA_PCR_SCR_VAL BIT(6) 63 64 #define MCHP_DMA_GIRQ_ID 14u 65 #define MCHP_DMA_GIRQ_SRC_ADDR 0x4000e078u 66 #define MCHP_DMA_GIRQ_EN_SET_ADDR 0x4000e07cu 67 #define MCHP_DMA_GIRQ_RESULT_ADDR 0x4000e080u 68 #define MCHP_DMA_GIRQ_EN_CLR_ADDR 0x4000e084u 69 70 #define MCHP_DMA_GIRQ_NUM 14u 71 #define MCHP_DMA_GIRQ_IDX ((MCHP_DMA_GIRQ_NUM) - 8u) 72 73 /* Aggregated GIRQ14 NVIC input */ 74 #define MCHP_DMA_AGGR_NVIC 6u 75 76 /* 77 * Value used for GIRQ Source, Set Enable, 78 * Result, and Clear Enable registers. 79 * 0 <= ch < MCHP_NUM_DMA_CHANNELS 80 */ 81 #define MCHP_DMA_GIRQ_VAL(ch) BIT(ch) 82 83 /* 84 * DMA channel direct NVIC external interrupt inputs 85 * 0 <= ch < 12 86 */ 87 #define MCHP_DMA_DIRECT_NVIC_NUM(ch) (24u + (ch)) 88 89 /* 90 * DMA channel direct NVIC external interrupt input from channel address. 91 * Channels are located starting at offset 0x40 from DMA block base address. 92 * Channels are spaced every 0x40 bytes. 93 * DMA block has 1KB total register space. 94 */ 95 #define MCHP_DMA_DIRECT_NVIC_NUM_BA(chba) \ 96 (24u + (((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6)) 97 98 #define MCHP_DMA0_GIRQ_NVIC (24u + 0u) 99 #define MCHP_DMA1_GIRQ_NVIC (24u + 1u) 100 #define MCHP_DMA2_GIRQ_NVIC (24u + 2u) 101 #define MCHP_DMA3_GIRQ_NVIC (24u + 3u) 102 #define MCHP_DMA4_GIRQ_NVIC (24u + 4u) 103 #define MCHP_DMA5_GIRQ_NVIC (24u + 5u) 104 #define MCHP_DMA6_GIRQ_NVIC (24u + 6u) 105 #define MCHP_DMA7_GIRQ_NVIC (24u + 7u) 106 #define MCHP_DMA8_GIRQ_NVIC (24u + 8u) 107 #define MCHP_DMA9_GIRQ_NVIC (24u + 9u) 108 #define MCHP_DMA10_GIRQ_NVIC (24u + 10u) 109 #define MCHP_DMA11_GIRQ_NVIC (24u + 11u) 110 111 /* 112 * GIRQ bit position from channel base address 113 */ 114 #define MCHP_DMA_GIRQ_POS_BA(chba) \ 115 (((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6) 116 117 #define MCHP_DMA_GIRQ_VAL_BA(chba) \ 118 (1u << MCHP_DMA_GIRQ_POS_BA(chba)) 119 120 #define MCHP_DMA0_GIRQ_POS 0u 121 #define MCHP_DMA1_GIRQ_POS 1u 122 #define MCHP_DMA2_GIRQ_POS 2u 123 #define MCHP_DMA3_GIRQ_POS 3u 124 #define MCHP_DMA4_GIRQ_POS 4u 125 #define MCHP_DMA5_GIRQ_POS 5u 126 #define MCHP_DMA6_GIRQ_POS 6u 127 #define MCHP_DMA7_GIRQ_POS 7u 128 #define MCHP_DMA8_GIRQ_POS 8u 129 #define MCHP_DMA9_GIRQ_POS 9u 130 #define MCHP_DMA10_GIRQ_POS 10u 131 #define MCHP_DMA11_GIRQ_POS 11u 132 133 #define MCHP_DMA0_GIRQ_VAL BIT(0) 134 #define MCHP_DMA1_GIRQ_VAL BIT(1) 135 #define MCHP_DMA2_GIRQ_VAL BIT(2) 136 #define MCHP_DMA3_GIRQ_VAL BIT(3) 137 #define MCHP_DMA4_GIRQ_VAL BIT(4) 138 #define MCHP_DMA5_GIRQ_VAL BIT(5) 139 #define MCHP_DMA6_GIRQ_VAL BIT(6) 140 #define MCHP_DMA7_GIRQ_VAL BIT(7) 141 #define MCHP_DMA8_GIRQ_VAL BIT(8) 142 #define MCHP_DMA9_GIRQ_VAL BIT(9) 143 #define MCHP_DMA10_GIRQ_VAL BIT(10) 144 #define MCHP_DMA11_GIRQ_VAL BIT(11) 145 146 /* 147 * Device Numbers for Channel Control Reg Device Number Field 148 */ 149 #define MCHP_DMA_DEVNUM_SMB0_SLV 0u 150 #define MCHP_DMA_DEVNUM_SMB0_MTR 1u 151 #define MCHP_DMA_DEVNUM_SMB1_SLV 2u 152 #define MCHP_DMA_DEVNUM_SMB1_MTR 3u 153 #define MCHP_DMA_DEVNUM_SMB2_SLV 4u 154 #define MCHP_DMA_DEVNUM_SMB2_MTR 5u 155 #define MCHP_DMA_DEVNUM_SMB3_SLV 6u 156 #define MCHP_DMA_DEVNUM_SMB3_MTR 7u 157 #define MCHP_DMA_DEVNUM_SMB4_SLV 8u 158 #define MCHP_DMA_DEVNUM_SMB4_RX 9u 159 #define MCHP_DMA_DEVNUM_QMSPI_TX 10u 160 #define MCHP_DMA_DEVNUM_QMSPI_RX 11u 161 #define MCHP_DMA_DEVNUM_MAX 12u 162 163 #define MCHP_DMA_CHAN_REG_BLEN 0x40u 164 165 /* DMA Block Layout 166 * DMA Main registers start at block base 167 * Three registers located at word boundaries (0, 4, 8) 168 * Each channel starts at base + ((channel_number + 1) * DMA_CHAN_REG_BLEN) 169 * DMA Main @ base 170 * DMA Channel 0 @ base + DMA_CHAN_REG_BLEN 171 * DMA Channel 1 @ base + (2 * DMA_CHAN_REG_BLEN) 172 * 173 */ 174 175 /* 176 * DMA Main Registers 177 */ 178 #define MCHP_DMAM_CTRL_OFS 0x00u 179 #define MCHP_DMAM_PKT_RO_OFS 0x04u 180 #define MCHP_DMAM_FSM_RO_OFS 0x08u 181 182 #define MCHP_DMAM_CTRL_OFFSET 0u 183 #define MCHP_DMAM_CTRL_MASK 0x03u 184 #define MCHP_DMAM_CTRL_ENABLE BIT(0) 185 #define MCHP_DMAM_CTRL_SOFT_RESET BIT(1) 186 187 /* 188 * DMA Main Register Access 189 */ 190 #define MCHP_DMAM_CTRL() \ 191 REG8_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_CTRL_OFS) 192 193 #define MCHP_DMAM_PKT_RO() \ 194 REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_PKT_RO_OFS) 195 196 #define MCHP_DMAM_FSM_RO() \ 197 REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_FSM_RO_OFS) 198 199 /* 200 * DMA channel register offsets 201 */ 202 #define MCHP_DMA_ACTV_OFS 0x00u 203 #define MCHP_DMA_MSTART_OFS 0x04u 204 #define MCHP_DMA_MEND_OFS 0x08u 205 #define MCHP_DMA_DSTART_OFS 0x0cu 206 #define MCHP_DMA_CTRL_OFS 0x10u 207 #define MCHP_DMA_ISTS_OFS 0x14u 208 #define MCHP_DMA_IEN_OFS 0x18u 209 #define MCHP_DMA_FSM_RO_OFS 0x1cu 210 /* Channels 0 and 1 include optional ALU */ 211 #define MCHP_DMA_ALU_CTRL_OFS 0x20u 212 #define MCHP_DMA_ALU_DATA_OFS 0x24u 213 #define MCHP_DMA_ALU_STS_RO_OFS 0x28u 214 215 /* 216 * DMA Channel register addresses 217 */ 218 #define MCHP_DMA_ACTV_ADDR(ch) \ 219 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ACTV_OFS)) 220 221 #define MCHP_DMA_MSTART_ADDR(ch) \ 222 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MSTART_OFS)) 223 224 #define MCHP_DMA_MEND_ADDR(ch) \ 225 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MEND_OFS)) 226 227 #define MCHP_DMA_DSTART_ADDR(ch) \ 228 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_DSTART_OFS)) 229 230 #define MCHP_DMA_CTRL_ADDR(ch) \ 231 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_CTRL_OFS)) 232 233 #define MCHP_DMA_ISTS_ADDR(ch) \ 234 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ISTS_OFS)) 235 236 #define MCHP_DMA_IEND_ADDR(ch) \ 237 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_IEN_OFS)) 238 239 #define MCHP_DMA_FSM_ADDR(ch) \ 240 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_FSM_RO_OFS)) 241 242 /* Channels 0 and 1 include optional ALU */ 243 #define MCHP_DMA_ALU_CTRL_ADDR(ch) \ 244 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_CTRL_OFS)) 245 246 #define MCHP_DMA_ALU_DATA_ADDR(ch) \ 247 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_DATA_OFS)) 248 249 #define MCHP_DMA_ALU_STS_RO_ADDR(ch) \ 250 (uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_STS_RO_OFS)) 251 252 /* 253 * DMA Channel Register Access 254 * ch = channel ID: 0 <= ch < MCHP_NUM_DMA_CHANNELS 255 */ 256 #define MCHP_DMA_ACTV(ch) \ 257 REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ACTV_OFS) 258 259 #define MCHP_DMA_MSTART(ch) \ 260 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MSTART_OFS) 261 262 #define MCHP_DMA_MEND(ch) \ 263 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MEND_OFS) 264 265 #define MCHP_DMA_DSTART(ch) \ 266 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_DSTART_OFS) 267 268 #define MCHP_DMA_CTRL(ch) \ 269 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_CTRL_OFS) 270 271 #define MCHP_DMA_ISTS(ch) \ 272 REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ISTS_OFS) 273 274 #define MCHP_DMA_IEN(ch) \ 275 REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_IEN_OFS) 276 277 #define MCHP_DMA_FSM(ch) \ 278 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_FSM_RO_OFS) 279 280 #define MCHP_DMA_ALU_EN(ch) \ 281 REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_CTRL_OFS) 282 283 #define MCHP_DMA_ALU_DATA(ch) \ 284 REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_DATA_OFS) 285 286 #define MCHP_DMA_ALU_STS_RO(ch) \ 287 REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_STS_RO_OFS) 288 289 /* 290 * DMA Channel Register Access by base address 291 * chba = channel base address (start of channel registers) 292 */ 293 #define MCHP_DMA_ACTV_BA(chba) \ 294 REG8_OFS(chba, MCHP_DMA_ACTV_OFS) 295 296 #define MCHP_DMA_MSTART_BA(chba) \ 297 REG32_OFS(chba, MCHP_DMA_MSTART_OFS) 298 299 #define MCHP_DMA_MEND_BA(chba) \ 300 REG32_OFS(chba, MCHP_DMA_MEND_OFS) 301 302 #define MCHP_DMA_DSTART_BA(chba) \ 303 REG32_OFS(chba, MCHP_DMA_DSTART_OFS) 304 305 #define MCHP_DMA_CTRL_BA(chba) \ 306 REG32_OFS(chba, MCHP_DMA_CTRL_OFS) 307 308 #define MCHP_DMA_ISTS_BA(chba) \ 309 REG8_OFS(chba, MCHP_DMA_ISTS_OFS) 310 311 #define MCHP_DMA_IEN_BA(chba) \ 312 REG8_OFS(chba, MCHP_DMA_IEN_OFS) 313 314 #define MCHP_DMA_FSM_BA(chba) \ 315 REG32_OFS(chba, MCHP_DMA_FSM_RO_OFS) 316 317 #define MCHP_DMA_ALU_EN_BA(chba) \ 318 REG8_OFS(chba, MCHP_DMA_ALU_CTRL_OFS) 319 320 #define MCHP_DMA_ALU_DATA_BA(chba) \ 321 REG32_OFS(chba, MCHP_DMA_ALU_DATA_OFS) 322 323 #define MCHP_DMA_ALU_STS_RO_BA(chba) \ 324 REG8_OFS(chba, MCHP_DMA_ALU_STS_RO_OFS) 325 326 /* 327 * Channel Activate, Offset 0x00, R/W 328 */ 329 #define MCHP_DMA_ACTV_REG_MASK 0x01u 330 #define MCHP_DMA_ACTV_VAL BIT(0) 331 332 /* 333 * Target (destination) Start Memory Address, Offset 0x04 334 */ 335 #define MCHP_DMA_MSTART_REG_MASK 0xffffffffu 336 337 /* 338 * Target (destination) End Memory Address, Offset 0x08 339 */ 340 #define MCHP_DMA_MEND_REG_MASK 0xffffffffu 341 342 /* 343 * Source (device) Address, Offset 0x0C 344 */ 345 #define MCHP_DMA_DSTART_REG_MASK 0xffffffffu 346 347 /* 348 * Control, Offset 0x10 349 */ 350 #define MCHP_DMA_C_REG_MASK 0x037fff3fu 351 #define MCHP_DMA_C_RUN BIT(0) 352 #define MCHP_DMA_C_REQ_STS_RO BIT(1) 353 #define MCHP_DMA_C_DONE_STS_RO BIT(2) 354 #define MCHP_DMA_C_CHAN_STS_MASK (0x03u << 3) 355 #define MCHP_DMA_C_BUSY_STS_POS 5u 356 #define MCHP_DMA_C_BUSY_STS BIT(5) 357 #define MCHP_DMA_C_DIR_POS 8u 358 #define MCHP_DMA_C_DEV2MEM 0u 359 #define MCHP_DMA_C_MEM2DEV BIT(8) 360 #define MCHP_DMA_C_DEV_NUM_POS 9u 361 #define MCHP_DMA_C_DEV_NUM_MASK0 0x7fu 362 #define MCHP_DMA_C_DEV_NUM_MASK (0x7fu << 9) 363 #define MCHP_DMA_C_NO_INCR_MEM 0u 364 #define MCHP_DMA_C_INCR_MEM BIT(16) 365 #define MCHP_DMA_C_NO_INCR_DEV 0u 366 #define MCHP_DMA_C_INCR_DEV BIT(17) 367 #define MCHP_DMA_C_LOCK_CHAN BIT(18) 368 #define MCHP_DMA_C_DIS_HWFLC BIT(19) 369 #define MCHP_DMA_C_XFRU_POS 20u 370 #define MCHP_DMA_C_XFRU_MASK0 0x07u 371 #define MCHP_DMA_C_XFRU_MASK (0x07u << 20) 372 #define MCHP_DMA_C_XFRU_1B (1u << MCHP_DMA_C_XFRU_POS) 373 #define MCHP_DMA_C_XFRU_2B (2u << MCHP_DMA_C_XFRU_POS) 374 #define MCHP_DMA_C_XFRU_4B (4u << MCHP_DMA_C_XFRU_POS) 375 #define MCHP_DMA_C_XFER_GO BIT(24) 376 #define MCHP_DMA_C_XFER_ABORT BIT(25) 377 /* combine direction and device number fields */ 378 #define MCHP_DMA_C_DEVDIR_POS 8u 379 #define MCHP_DMA_C_DEVDIR_MASK0 0xffu 380 #define MCHP_DMA_C_DEVDIR_MASK (0xffu << 8) 381 382 /* 383 * Channel Interrupt Status, Offset 0x14 384 */ 385 #define MCHP_DMA_STS_REG_MASK 0x07u 386 #define MCHP_DMA_STS_BUS_ERR BIT(0) 387 #define MCHP_DMA_STS_FLOW_CTRL_ERR BIT(1) 388 #define MCHP_DMA_STS_DONE BIT(2) 389 #define MCHP_DMA_STS_ALL 0x07u 390 391 /* 392 * Channel Interrupt Enable, Offset 0x18 393 */ 394 #define MCHP_DMA_IEN_REG_MASK 0x07u 395 #define MCHP_DMA_IEN_BUS_ERR BIT(0) 396 #define MCHP_DMA_IEN_FLOW_CTRL_ERR BIT(1) 397 #define MCHP_DMA_IEN_DONE BIT(2) 398 #define MCHP_DMA_IEN_ALL 0x07u 399 400 /* 401 * Channel FSM (read-only), Offset 0x1C 402 */ 403 #define MCHP_DMA_FSM_REG_MASK 0x0ffffu 404 405 /* 406 * DMA Block with optional ALU includes four extra registers. 407 * Channel's total register allocation is 0x40 408 */ 409 410 /* 411 * ALU Control, Offset 0x20 412 */ 413 #define MCHP_DMA_ALU_CTRL_MASK 0x03u 414 #define MCHP_DMA_ALU_ENABLE_POS 0 415 #define MCHP_DMA_ALU_MASK BIT(MCHP_DMA_ALU_ENABLE_POS) 416 #define MCHP_DMA_ALU_DISABLE 0u 417 #define MCHP_DMA_ALU_ENABLE BIT(MCHP_DMA_ALU_ENABLE_POS) 418 #define MCHP_DMA_ALU_POST_XFER_EN_POS 1u 419 #define MCHP_DMA_ALU_POST_XFER_EN_MASK BIT(MCHP_DMA_ALU_POST_XFER_EN_POS) 420 #define MCHP_DMA_ALU_POST_XFER_DIS 0u 421 #define MCHP_DMA_ALU_POST_XFER_EN BIT(MCHP_DMA_ALU_POST_XFER_EN_POS) 422 423 /* 424 * ALU Data, Offset 0x24 425 */ 426 #define MCHP_DMA_ALU_DATA_MASK 0xffffffffu 427 428 /* 429 * ALU Status, Offset 0x28 Read-Only 430 */ 431 #define MCHP_DMA_ALU_STS_MASK 0x0fu 432 #define MCHP_DMA_ALU_STS_DONE_POS 0u 433 #define MCHP_DMA_ALU_STS_RUN_POS 1u 434 #define MCHP_DMA_ALU_STS_XFR_DONE_POS 2u 435 #define MCHP_DMA_ALU_STS_DATA_RDY_POS 3u 436 #define MCHP_DMA_ALU_STS_DONE BIT(MCHP_DMA_ALU_STS_DONE_POS) 437 #define MCHP_DMA_ALU_STS_RUN BIT(MCHP_DMA_ALU_STS_RUN_POS) 438 #define MCHP_DMA_ALU_STS_XFR_DONE BIT(MCHP_DMA_ALU_STS_XFR_DONE_POS) 439 #define MCHP_DMA_ALU_STS_DATA_RDY BIT(MCHP_DMA_ALU_STS_DATA_RDY_POS) 440 441 /* 442 * ALU Test, Offset 0x2C Reserved 443 */ 444 #define MCHP_DMA_ALU_TEST_MASK 0xffffffffu 445 446 /* 447 * Channel 0 has ALU for CRC32 448 * Channel 1 has ALU for memory fill 449 * Channels 2-11 do not implement an ALU 450 */ 451 #define MCHP_DMA_NUM_CHAN 12u 452 #define MCHP_DMA_CHAN_SPACING 0x40u 453 #define MCHP_DMA_CHAN_SPACING_POF2 6u 454 455 #define MCHP_DMA_WCRC_CHAN_ID 0u 456 #define MCHP_DMA_WMF_CHAN_ID 1u 457 #define MCHP_MAX_DMA_CHAN 12u 458 #define MCHP_NUM_DMA_CHAN_NO_ALU ((MCHP_MAX_DMA_CHAN) - 2) 459 460 /** 461 * @brief DMA Main (DMAM) 462 */ 463 typedef struct dma_main_regs 464 { /*!< (@ 0x40002400) DMA Structure */ 465 __IOM uint8_t ACTRST; /*!< (@ 0x00000000) DMA block activate/reset */ 466 uint8_t RSVDA[3]; 467 __IM uint32_t DATA_PKT; /*!< (@ 0x00000004) DMA data packet (RO) */ 468 __IM uint32_t ARB_FSM; /*!< (@ 0x00000008) DMA Arbiter FSM (RO) */ 469 } DMAM_Type; 470 471 /* 472 * NOTE: structure size is 0x40 (64) bytes as each channel 473 * is spaced every 0x40 bytes from DMA block base address. 474 * Channel 0 starts at offset 0x40 from DMA Main base address. 475 * Channels 0 and 1 include an ALU for special operations on data 476 * they transfer. 477 * Channel 0 ALU is specialized for CRC-32 calculations. 478 * Channel 1 ALU is specialized for memory fill. 479 */ 480 481 /** 482 * @brief DMA Channels 0 and 1 with ALU 483 */ 484 typedef struct dma_chan_alu_regs 485 { 486 __IOM uint8_t ACTV; /*!< (@ 0x00000000) DMA channel activate */ 487 uint8_t RSVD1[3]; 488 __IOM uint32_t MSTART; /*!< (@ 0x00000004) DMA channel memory start address */ 489 __IOM uint32_t MEND; /*!< (@ 0x00000008) DMA channel memory end address */ 490 __IOM uint32_t DSTART; /*!< (@ 0x0000000C) DMA channel device start address */ 491 __IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */ 492 __IOM uint8_t ISTS; /*!< (@ 0x00000014) DMA channel interrupt status */ 493 uint8_t RSVD2[3]; 494 __IOM uint8_t IEN; /*!< (@ 0x00000018) DMA channel interrupt enable */ 495 uint8_t RSVD3[3]; 496 __IM uint32_t FSM; /*!< (@ 0x0000001C) DMA channel FSM (RO) */ 497 __IOM uint8_t ALU_EN; /*!< (@ 0x00000020) DMA channels [0-1] ALU Enable */ 498 uint8_t RSVD4[3]; 499 __IOM uint32_t ALU_DATA; /*!< (@ 0x00000024) DMA channels [0-1] ALU Data */ 500 __IOM uint8_t ALU_STS; /*!< (@ 0x00000028) DMA channels [0-1] ALU post status (RO) */ 501 uint8_t RSVD5[3]; 502 __IM uint32_t ALU_FSM; /*!< (@ 0x0000002C) DMA channels [0-1] ALU FSM (RO) */ 503 uint8_t RSVD6[16]; /* pad to 0x40(64) byte size */ 504 } DMA_CHAN_ALU_Type; 505 506 /** 507 * @brief DMA Channels 2 through 11 no ALU 508 */ 509 typedef struct dma_chan_regs 510 { 511 __IOM uint8_t ACTV; /*!< (@ 0x00000000) DMA channel activate */ 512 uint8_t RSVD1[3]; 513 __IOM uint32_t MSTART; /*!< (@ 0x00000004) DMA channel memory start address */ 514 __IOM uint32_t MEND; /*!< (@ 0x00000008) DMA channel memory end address */ 515 __IOM uint32_t DSTART; /*!< (@ 0x0000000C) DMA channel device start address */ 516 __IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */ 517 __IOM uint8_t ISTS; /*!< (@ 0x00000014) DMA channel interrupt status */ 518 uint8_t RSVD2[3]; 519 __IOM uint8_t IEN; /*!< (@ 0x00000018) DMA channel interrupt enable */ 520 uint8_t RSVD3[3]; 521 __IM uint32_t FSM; /*!< (@ 0x0000001C) DMA channel FSM (RO) */ 522 uint8_t RSVD4[0x20]; /* pad to 0x40(64) byte size */ 523 } DMA_CHAN_Type; 524 525 #endif /* #ifndef _DMA_H */ 526 /* end dma.h */ 527 /** @} 528 */ 529
