1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file acpi_ec.h 28 *MEC1501 ACPI EC Registers 29 */ 30 /** @defgroup MEC1501 Peripherals ACPI_EC 31 */ 32 33 #ifndef _ACPI_EC_H 34 #define _ACPI_EC_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ ACPI_EC =================== */ 43 /* =========================================================================*/ 44 45 #define MCHP_ACPI_EC_BASE_ADDR 0x400f0800u 46 47 #define MCHP_ACPI_EC_NUM_INSTANCES 4u 48 #define MCHP_ACPI_EC_SPACING 0x0400u 49 #define MCHP_ACPI_EC_SPACING_PWROF2 10u 50 51 #define MCHP_ACPI_EC0_ADDR 0x400f0800u 52 #define MCHP_ACPI_EC1_ADDR 0x400f0C00u 53 #define MCHP_ACPI_EC2_ADDR 0x400f1000u 54 #define MCHP_ACPI_EC3_ADDR 0x400f1400u 55 56 /* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */ 57 #define MCHP_ACPI_EC_ADDR(n) (MCHP_ACPI_EC_BASE_ADDR +\ 58 ((uint32_t)(n) << MCHP_ACPI_EC_SPACING_PWROF2)) 59 60 /* 61 * ACPI_EC interrupts 62 */ 63 #define MCHP_ACPI_EC_GIRQ 15u 64 #define MCHP_ACPI_EC_GIRQ_NVIC 7u 65 66 #define MCHP_ACPI_EC_0_IBF_NVIC 45u 67 #define MCHP_ACPI_EC_0_OBE_NVIC 46u 68 #define MCHP_ACPI_EC_0_IBF_GIRQ_POS 5u 69 #define MCHP_ACPI_EC_0_OBE_GIRQ_POS 6u 70 #define MCHP_ACPI_EC_0_IBF_GIRQ BIT(5) 71 #define MCHP_ACPI_EC_0_OBE_GIRQ BIT(6) 72 73 #define MCHP_ACPI_EC_1_IBF_NVIC 47u 74 #define MCHP_ACPI_EC_1_OBE_NVIC 48u 75 #define MCHP_ACPI_EC_1_IBF_GIRQ_POS 7u 76 #define MCHP_ACPI_EC_1_OBE_GIRQ_POS 8u 77 #define MCHP_ACPI_EC_1_IBF_GIRQ BIT(7) 78 #define MCHP_ACPI_EC_1_OBE_GIRQ BIT(8) 79 80 #define MCHP_ACPI_EC_2_IBF_NVIC 49u 81 #define MCHP_ACPI_EC_2_OBE_NVIC 50u 82 #define MCHP_ACPI_EC_2_IBF_GIRQ_POS 9u 83 #define MCHP_ACPI_EC_2_OBE_GIRQ_POS 10u 84 #define MCHP_ACPI_EC_2_IBF_GIRQ BIT(9) 85 #define MCHP_ACPI_EC_2_OBE_GIRQ BIT(10) 86 87 #define MCHP_ACPI_EC_3_IBF_NVIC 51u 88 #define MCHP_ACPI_EC_3_OBE_NVIC 52u 89 #define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11u 90 #define MCHP_ACPI_EC_3_OBE_GIRQ_POS 12u 91 #define MCHP_ACPI_EC_3_IBF_GIRQ BIT(11) 92 #define MCHP_ACPI_EC_3_OBE_GIRQ BIT(12) 93 94 /* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */ 95 #define MCHP_ACPI_EC_IBF_NVIC(n) (45u + ((uint32_t)(n) << 1)) 96 #define MCHP_ACPI_EC_OBE_NVIC(n) (46u + ((uint32_t)(n) << 1)) 97 #define MCHP_ACPI_EC_IBF_GIRQ_POS(n) (5u + ((uint32_t)(n) << 1)) 98 #define MCHP_ACPI_EC_OBE_GIRQ_POS(n) (6u + ((uint32_t)(n) << 1)) 99 #define MCHP_ACPI_EC_IBF_GIRQ(n) (1u << MCHP_ACPI_EC_IBF_GIRQ_POS(n)) 100 #define MCHP_ACPI_EC_OBE_GIRQ(n) (1u << MCHP_ACPI_EC_OBE_GIRQ_POS(n)) 101 102 103 /* 104 * EC_STS and OS_CMD_STS(read) bit definitions 105 */ 106 #define MCHP_ACPI_EC_STS_OBF_POS 0u 107 #define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI_EC_STS_OBF_POS) 108 #define MCHP_ACPI_EC_STS_IBF_POS 1u 109 #define MCHP_ACPI_EC_STS_IBF BIT(MCHP_ACPI_EC_STS_IBF_POS) 110 #define MCHP_ACPI_EC_STS_UD1A_POS 2u 111 #define MCHP_ACPI_EC_STS_UD1A BIT(MCHP_ACPI_EC_STS_UD1A_POS) 112 #define MCHP_ACPI_EC_STS_CMD_POS 3u 113 #define MCHP_ACPI_EC_STS_CMD BIT(MCHP_ACPI_EC_STS_CMD_POS) 114 #define MCHP_ACPI_EC_STS_BURST_POS 4u 115 #define MCHP_ACPI_EC_STS_BURST BIT(MCHP_ACPI_EC_STS_BURST_POS) 116 #define MCHP_ACPI_EC_STS_SCI_POS 5u 117 #define MCHP_ACPI_EC_STS_SCI BIT(MCHP_ACPI_EC_STS_SCI_POS) 118 #define MCHP_ACPI_EC_STS_SMI_POS 6u 119 #define MCHP_ACPI_EC_STS_SMI BIT(MCHP_ACPI_EC_STS_SMI_POS) 120 #define MCHP_ACPI_EC_STS_UD0A_POS 7u 121 #define MCHP_ACPI_EC_STS_UD0A BIT(MCHP_ACPI_EC_STS_UD0A_POS) 122 123 /* 124 * EC_BYTE_CTRL and OS_BYTE_CTRL 125 */ 126 #define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0u 127 #define MCHP_ACPI_EC_BYTE_CTRL_4B_EN BIT(MCHP_ACPI_EC_BYTE_CTRL_4B_POS) 128 129 /** 130 * @brief ACPI EC Registers (ACPI_EC) 131 */ 132 typedef struct acpi_ec_regs { 133 __IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */ 134 __IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */ 135 __IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */ 136 uint8_t RSVD1[0x100 - 0x06]; 137 __IOM uint32_t EC2OS_DATA; /*!< (@ 0x0100) EC to OS Data */ 138 __IOM uint8_t EC_STS; /*!< (@ 0x0104) EC Status */ 139 __IOM uint8_t EC_BYTE_CTRL; /*!< (@ 0x0105) EC Byte Control */ 140 uint8_t RSVD2[2]; 141 __IOM uint32_t OS2EC_DATA; /*!< (@ 0x0108) OS to EC Data */ 142 } ACPI_EC_Type; 143 144 /* =========================================================================*/ 145 /* ================ ACPI_PM1 =================== */ 146 /* =========================================================================*/ 147 148 #define MCHP_ACPI_PM1_BASE_ADDR 0x400f1c00u 149 150 /* 151 * ACPI_PM1 interrupts 152 */ 153 #define MCHP_ACPI_PM1_CTL_GIRQ 15u 154 #define MCHP_ACPI_PM1_EN_GIRQ 15u 155 #define MCHP_ACPI_PM1_STS_GIRQ 15u 156 157 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 158 #define MCHP_ACPI_PM1_CTL_GIRQ_POS 15u 159 #define MCHP_ACPI_PM1_EN_GIRQ_POS 16u 160 #define MCHP_ACPI_PM1_STS_GIRQ_POS 17u 161 162 #define MCHP_ACPI_PM1_CTL_GIRQ_VAL BIT(MCHP_ACPI_PM1_CTL_GIRQ_POS) 163 #define MCHP_ACPI_PM1_EN_GIRQ_VAL BIT(MCHP_ACPI_PM1_EN_GIRQ_POS) 164 #define MCHP_ACPI_PM1_STS_GIRQ_VAL BIT(MCHP_ACPI_PM1_STS_GIRQ_POS) 165 166 /* VCI GIRQ aggregated NVIC input */ 167 #define MCHP_ACPI_PM1_CTL_NVIC_AGGR 7u 168 #define MCHP_ACPI_PM1_EN_NVIC_AGGR 7u 169 #define MCHP_ACPI_PM1_STS_NVIC_AGGR 7u 170 171 /* VCI direct NVIC inputs */ 172 #define MCHP_ACPI_PM1_CTL_NVIC_DIRECT 55u 173 #define MCHP_ACPI_PM1_EN_NVIC_DIRECT 56u 174 #define MCHP_ACPI_PM1_STS_NVIC_DIRECT 57u 175 176 /* ACPI_PM1 RT/EC Status 1 */ 177 #define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0u 178 #define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100u 179 #define MCHP_ACPI_PM1_STS1_REG_MASK 0u 180 181 /* ACPI_PM1 RT/EC Status 2 */ 182 #define MCHP_ACPI_PM1_RT_STS2_REG_OFS 0x0001u 183 #define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101u 184 #define MCHP_ACPI_PM1_STS2_REG_MASK 0x008fu 185 #define MCHP_ACPI_PM1_STS2_PWRBTN BIT(0) 186 #define MCHP_ACPI_PM1_STS2_SLPBTN BIT(1) 187 #define MCHP_ACPI_PM1_STS2_RTC BIT(2) 188 #define MCHP_ACPI_PM1_STS2_PWRBTNOR BIT(3) 189 #define MCHP_ACPI_PM1_STS2_WAK BIT(7) 190 191 /* ACPI_PM1 RT/EC Enable 1 */ 192 #define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002u 193 #define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102u 194 #define MCHP_ACPI_PM1_EN1_REG_MASK 0u 195 196 /* ACPI_PM1 RT/EC Enable 2 */ 197 #define MCHP_ACPI_PM1_RT_EN2_REG_OFS 0x0003u 198 #define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103u 199 #define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007u 200 #define MCHP_ACPI_PM1_EN2_PWRBTN BIT(0) 201 #define MCHP_ACPI_PM1_EN2_SLPBTN BIT(1) 202 #define MCHP_ACPI_PM1_EN2_RTC BIT(2) 203 204 /* ACPI_PM1 RT/EC Control 1 */ 205 #define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 0x0004u 206 #define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104u 207 #define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u 208 209 /* ACPI_PM1 RT/EC Control 2 */ 210 #define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 0x0005u 211 #define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105u 212 #define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003eu 213 #define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN BIT(1) 214 #define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2 215 #define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK (0x03u << 2) 216 #define MCHP_ACPI_PM1_CTRL2_SLP_EN BIT(5) 217 218 /* ACPI_PM1 RT/EC Control 21 */ 219 #define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006u 220 #define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106u 221 #define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u 222 223 /* ACPI_PM1 RT/EC Control 22 */ 224 #define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 0x0007u 225 #define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107u 226 #define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u 227 228 /* ACPI_PM1 EC PM Status register */ 229 #define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110u 230 #define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x0001u 231 #define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x0001u 232 233 /** @brief ACPI PM1 Registers (ACPI_PM1) */ 234 typedef struct acpi_pm1_regs { 235 __IOM uint8_t RT_STS1; /*!< (@ 0x0000) */ 236 __IOM uint8_t RT_STS2; /*!< (@ 0x0001) */ 237 __IOM uint8_t RT_EN1; /*!< (@ 0x0002) */ 238 __IOM uint8_t RT_EN2; /*!< (@ 0x0003) */ 239 __IOM uint8_t RT_CTRL1; /*!< (@ 0x0004) */ 240 __IOM uint8_t RT_CTRL2; /*!< (@ 0x0005) */ 241 __IOM uint8_t RT_CTRL21; /*!< (@ 0x0006) */ 242 __IOM uint8_t RT_CTRL22; /*!< (@ 0x0007) */ 243 uint8_t RSVD1[(0x100 - 0x008)]; 244 __IOM uint8_t EC_STS1; /*!< (@ 0x0100) */ 245 __IOM uint8_t EC_STS2; /*!< (@ 0x0101) */ 246 __IOM uint8_t EC_EN1; /*!< (@ 0x0102) */ 247 __IOM uint8_t EC_EN2; /*!< (@ 0x0103) */ 248 __IOM uint8_t EC_CTRL1; /*!< (@ 0x0104) */ 249 __IOM uint8_t EC_CTRL2; /*!< (@ 0x0105) */ 250 __IOM uint8_t EC_CTRL21; /*!< (@ 0x0106) */ 251 __IOM uint8_t EC_CTRL22; /*!< (@ 0x0107) */ 252 uint8_t RSVD2[(0x0110 - 0x0108)]; 253 __IOM uint8_t EC_PM_STS; /*!< (@ 0x0110) */ 254 uint8_t RSVD3[3]; 255 } ACPI_PM1_Type; 256 257 #endif /* #ifndef _ACPI_EC_H */ 258 /* end acpi_ec.h */ 259 /** @} 260 */ 261
