1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * This file has been automatically generated 9 * Tool Version: 1.0.0 10 * Generation Date: 2023-08-01 11 */ 12 13 #ifndef _SEDI_HPET_REGS_H_ 14 #define _SEDI_HPET_REGS_H_ 15 16 #include <sedi_reg_defs.h> 17 18 19 /* ********* HPET GCID_LOW *********** 20 * 21 * Register of SEDI HPET 22 * GCID_LOW: General Capabilities And ID 23 * AddressOffset : 0x0 24 * AccessType : RO 25 * WritableBitMask: 0x0 26 * ResetValue : (uint32_t)0x8086a201 27 */ 28 SEDI_REG_DEFINE(HPET, GCID_LOW, 0x0, RO, (uint32_t)0x0, (uint32_t)0x8086a201); 29 30 /* 31 * Bit Field of Register GCID_LOW 32 * RID: Revision ID 33 * BitOffset : 0 34 * BitWidth : 8 35 * AccessType: RO 36 * ResetValue: (uint32_t)0x1 37 */ 38 SEDI_RBF_DEFINE(HPET, GCID_LOW, RID, 0, 8, RO, (uint32_t)0x1); 39 40 /* 41 * Bit Field of Register GCID_LOW 42 * NT: Number Of Timers 43 * BitOffset : 8 44 * BitWidth : 5 45 * AccessType: RO 46 * ResetValue: (uint32_t)0x2 47 */ 48 SEDI_RBF_DEFINE(HPET, GCID_LOW, NT, 8, 5, RO, (uint32_t)0x2); 49 50 /* 51 * Bit Field of Register GCID_LOW 52 * CS: Counter Size 53 * BitOffset : 13 54 * BitWidth : 1 55 * AccessType: RO 56 * ResetValue: (uint32_t)0x1 57 */ 58 SEDI_RBF_DEFINE(HPET, GCID_LOW, CS, 13, 1, RO, (uint32_t)0x1); 59 SEDI_RBFV_DEFINE(HPET, GCID_LOW, CS, 0, 0); 60 SEDI_RBFV_DEFINE(HPET, GCID_LOW, CS, 1, 1); 61 62 /* 63 * Bit Field of Register GCID_LOW 64 * RESERVED0: 65 * BitOffset : 14 66 * BitWidth : 1 67 * AccessType: RO 68 * ResetValue: (uint32_t)0x0 69 */ 70 SEDI_RBF_DEFINE(HPET, GCID_LOW, RESERVED0, 14, 1, RO, (uint32_t)0x0); 71 SEDI_RBFV_DEFINE(HPET, GCID_LOW, RESERVED0, 0, 0); 72 SEDI_RBFV_DEFINE(HPET, GCID_LOW, RESERVED0, 1, 1); 73 74 /* 75 * Bit Field of Register GCID_LOW 76 * LRC: Legacy Rout Capable 77 * BitOffset : 15 78 * BitWidth : 1 79 * AccessType: RO 80 * ResetValue: (uint32_t)0x1 81 */ 82 SEDI_RBF_DEFINE(HPET, GCID_LOW, LRC, 15, 1, RO, (uint32_t)0x1); 83 SEDI_RBFV_DEFINE(HPET, GCID_LOW, LRC, 0, 0); 84 SEDI_RBFV_DEFINE(HPET, GCID_LOW, LRC, 1, 1); 85 86 /* 87 * Bit Field of Register GCID_LOW 88 * VID: Vendor ID 89 * BitOffset : 16 90 * BitWidth : 16 91 * AccessType: RO 92 * ResetValue: (uint32_t)0x8086 93 */ 94 SEDI_RBF_DEFINE(HPET, GCID_LOW, VID, 16, 16, RO, (uint32_t)0x8086); 95 96 /* ********* HPET GCID_HIGH *********** 97 * 98 * Register of SEDI HPET 99 * GCID_HIGH: General Capabilities And ID 100 * AddressOffset : 0x4 101 * AccessType : RO 102 * WritableBitMask: 0x0 103 * ResetValue : (uint32_t)0x1d1a94a 104 */ 105 SEDI_REG_DEFINE(HPET, GCID_HIGH, 0x4, RO, (uint32_t)0x0, (uint32_t)0x1d1a94a); 106 107 /* 108 * Bit Field of Register GCID_HIGH 109 * CTP: Counter Tick Period 110 * BitOffset : 0 111 * BitWidth : 32 112 * AccessType: RO 113 * ResetValue: (uint32_t)0x1d1a94a 114 */ 115 SEDI_RBF_DEFINE(HPET, GCID_HIGH, CTP, 0, 32, RO, (uint32_t)0x1d1a94a); 116 117 /* ********* HPET GCFG_LOW *********** 118 * 119 * Register of SEDI HPET 120 * GCFG_LOW: General Configuration 121 * AddressOffset : 0x10 122 * AccessType : RW 123 * WritableBitMask: 0x3 124 * ResetValue : (uint32_t)0x0 125 */ 126 SEDI_REG_DEFINE(HPET, GCFG_LOW, 0x10, RW, (uint32_t)0x3, (uint32_t)0x0); 127 128 /* 129 * Bit Field of Register GCFG_LOW 130 * EN: Overall Enable 131 * BitOffset : 0 132 * BitWidth : 1 133 * AccessType: RW_V 134 * ResetValue: (uint32_t)0x0 135 */ 136 SEDI_RBF_DEFINE(HPET, GCFG_LOW, EN, 0, 1, RW_V, (uint32_t)0x0); 137 SEDI_RBFV_DEFINE(HPET, GCFG_LOW, EN, 0, 0); 138 SEDI_RBFV_DEFINE(HPET, GCFG_LOW, EN, 1, 1); 139 140 /* 141 * Bit Field of Register GCFG_LOW 142 * LRE: Overall Enable 143 * BitOffset : 1 144 * BitWidth : 1 145 * AccessType: RW_V 146 * ResetValue: (uint32_t)0x0 147 */ 148 SEDI_RBF_DEFINE(HPET, GCFG_LOW, LRE, 1, 1, RW_V, (uint32_t)0x0); 149 SEDI_RBFV_DEFINE(HPET, GCFG_LOW, LRE, 0, 0); 150 SEDI_RBFV_DEFINE(HPET, GCFG_LOW, LRE, 1, 1); 151 152 /* 153 * Bit Field of Register GCFG_LOW 154 * RESERVED0: 155 * BitOffset : 2 156 * BitWidth : 30 157 * AccessType: RO 158 * ResetValue: (uint32_t)0x0 159 */ 160 SEDI_RBF_DEFINE(HPET, GCFG_LOW, RESERVED0, 2, 30, RO, (uint32_t)0x0); 161 162 /* ********* HPET GCFG_HIGH *********** 163 * 164 * Register of SEDI HPET 165 * GCFG_HIGH: General Configuration 166 * AddressOffset : 0x14 167 * AccessType : RO 168 * WritableBitMask: 0x0 169 * ResetValue : (uint32_t)0x0 170 */ 171 SEDI_REG_DEFINE(HPET, GCFG_HIGH, 0x14, RO, (uint32_t)0x0, (uint32_t)0x0); 172 173 /* 174 * Bit Field of Register GCFG_HIGH 175 * RESERVED0: 176 * BitOffset : 0 177 * BitWidth : 32 178 * AccessType: RO 179 * ResetValue: (uint32_t)0x0 180 */ 181 SEDI_RBF_DEFINE(HPET, GCFG_HIGH, RESERVED0, 0, 32, RO, (uint32_t)0x0); 182 183 /* ********* HPET GIS_LOW *********** 184 * 185 * Register of SEDI HPET 186 * GIS_LOW: General Interrupt Status 187 * AddressOffset : 0x20 188 * AccessType : RW 189 * WritableBitMask: 0x7 190 * ResetValue : (uint32_t)0x0 191 */ 192 SEDI_REG_DEFINE(HPET, GIS_LOW, 0x20, RW, (uint32_t)0x7, (uint32_t)0x0); 193 194 /* 195 * Bit Field of Register GIS_LOW 196 * T0: Timer 0 Status 197 * BitOffset : 0 198 * BitWidth : 1 199 * AccessType: RW_V 200 * ResetValue: (uint32_t)0x0 201 */ 202 SEDI_RBF_DEFINE(HPET, GIS_LOW, T0, 0, 1, RW_V, (uint32_t)0x0); 203 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T0, 0, 0); 204 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T0, 1, 1); 205 206 /* 207 * Bit Field of Register GIS_LOW 208 * T1: Timer 1 Status 209 * BitOffset : 1 210 * BitWidth : 1 211 * AccessType: RW_V 212 * ResetValue: (uint32_t)0x0 213 */ 214 SEDI_RBF_DEFINE(HPET, GIS_LOW, T1, 1, 1, RW_V, (uint32_t)0x0); 215 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T1, 0, 0); 216 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T1, 1, 1); 217 218 /* 219 * Bit Field of Register GIS_LOW 220 * T2: Timer 2 Status 221 * BitOffset : 2 222 * BitWidth : 1 223 * AccessType: RW_V 224 * ResetValue: (uint32_t)0x0 225 */ 226 SEDI_RBF_DEFINE(HPET, GIS_LOW, T2, 2, 1, RW_V, (uint32_t)0x0); 227 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T2, 0, 0); 228 SEDI_RBFV_DEFINE(HPET, GIS_LOW, T2, 1, 1); 229 230 /* 231 * Bit Field of Register GIS_LOW 232 * RESERVED0: 233 * BitOffset : 3 234 * BitWidth : 29 235 * AccessType: RO 236 * ResetValue: (uint32_t)0x0 237 */ 238 SEDI_RBF_DEFINE(HPET, GIS_LOW, RESERVED0, 3, 29, RO, (uint32_t)0x0); 239 240 /* ********* HPET GIS_HIGH *********** 241 * 242 * Register of SEDI HPET 243 * GIS_HIGH: General Interrupt Status 244 * AddressOffset : 0x24 245 * AccessType : RO 246 * WritableBitMask: 0x0 247 * ResetValue : (uint32_t)0x0 248 */ 249 SEDI_REG_DEFINE(HPET, GIS_HIGH, 0x24, RO, (uint32_t)0x0, (uint32_t)0x0); 250 251 /* 252 * Bit Field of Register GIS_HIGH 253 * RESERVED0: 254 * BitOffset : 0 255 * BitWidth : 32 256 * AccessType: RO 257 * ResetValue: (uint32_t)0x0 258 */ 259 SEDI_RBF_DEFINE(HPET, GIS_HIGH, RESERVED0, 0, 32, RO, (uint32_t)0x0); 260 261 /* ********* HPET MCV_LOW *********** 262 * 263 * Register of SEDI HPET 264 * MCV_LOW: Main Counter Value 265 * AddressOffset : 0x0f0 266 * AccessType : RW 267 * WritableBitMask: 0xffffffff 268 * ResetValue : (uint32_t)0x0 269 */ 270 SEDI_REG_DEFINE(HPET, MCV_LOW, 0x0f0, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 271 272 /* 273 * Bit Field of Register MCV_LOW 274 * MCV_LOW: Counter Value 275 * BitOffset : 0 276 * BitWidth : 32 277 * AccessType: RW_V 278 * ResetValue: (uint32_t)0x0 279 */ 280 SEDI_RBF_DEFINE(HPET, MCV_LOW, MCV_LOW, 0, 32, RW_V, (uint32_t)0x0); 281 282 /* ********* HPET MCV_HIGH *********** 283 * 284 * Register of SEDI HPET 285 * MCV_HIGH: Main Counter Value 286 * AddressOffset : 0x0f4 287 * AccessType : RW 288 * WritableBitMask: 0xffffffff 289 * ResetValue : (uint32_t)0x0 290 */ 291 SEDI_REG_DEFINE(HPET, MCV_HIGH, 0x0f4, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 292 293 /* 294 * Bit Field of Register MCV_HIGH 295 * MCV_HIGH: Counter Value 296 * BitOffset : 0 297 * BitWidth : 32 298 * AccessType: RW_V 299 * ResetValue: (uint32_t)0x0 300 */ 301 SEDI_RBF_DEFINE(HPET, MCV_HIGH, MCV_HIGH, 0, 32, RW_V, (uint32_t)0x0); 302 303 /* ********* HPET T0C_LOW *********** 304 * 305 * Register of SEDI HPET 306 * T0C_LOW: Timer N Config And Capabilities 307 * AddressOffset : 0x100 308 * AccessType : RW 309 * WritableBitMask: 0x3f4e 310 * ResetValue : (uint32_t)0x30 311 */ 312 SEDI_REG_DEFINE(HPET, T0C_LOW, 0x100, RW, (uint32_t)0x3f4e, (uint32_t)0x30); 313 314 /* 315 * Bit Field of Register T0C_LOW 316 * RESERVED2: 317 * BitOffset : 0 318 * BitWidth : 1 319 * AccessType: RO 320 * ResetValue: (uint32_t)0x0 321 */ 322 SEDI_RBF_DEFINE(HPET, T0C_LOW, RESERVED2, 0, 1, RO, (uint32_t)0x0); 323 SEDI_RBFV_DEFINE(HPET, T0C_LOW, RESERVED2, 0, 0); 324 SEDI_RBFV_DEFINE(HPET, T0C_LOW, RESERVED2, 1, 1); 325 326 /* 327 * Bit Field of Register T0C_LOW 328 * IT: Timer Interrupt Type 329 * BitOffset : 1 330 * BitWidth : 1 331 * AccessType: RW_V 332 * ResetValue: (uint32_t)0x0 333 */ 334 SEDI_RBF_DEFINE(HPET, T0C_LOW, IT, 1, 1, RW_V, (uint32_t)0x0); 335 SEDI_RBFV_DEFINE(HPET, T0C_LOW, IT, 0, 0); 336 SEDI_RBFV_DEFINE(HPET, T0C_LOW, IT, 1, 1); 337 338 /* 339 * Bit Field of Register T0C_LOW 340 * IE: Interrupt Enable 341 * BitOffset : 2 342 * BitWidth : 1 343 * AccessType: RW_V 344 * ResetValue: (uint32_t)0x0 345 */ 346 SEDI_RBF_DEFINE(HPET, T0C_LOW, IE, 2, 1, RW_V, (uint32_t)0x0); 347 SEDI_RBFV_DEFINE(HPET, T0C_LOW, IE, 0, 0); 348 SEDI_RBFV_DEFINE(HPET, T0C_LOW, IE, 1, 1); 349 350 /* 351 * Bit Field of Register T0C_LOW 352 * TYP: Timer Type 353 * BitOffset : 3 354 * BitWidth : 1 355 * AccessType: RW_V 356 * ResetValue: (uint32_t)0x0 357 */ 358 SEDI_RBF_DEFINE(HPET, T0C_LOW, TYP, 3, 1, RW_V, (uint32_t)0x0); 359 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TYP, 0, 0); 360 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TYP, 1, 1); 361 362 /* 363 * Bit Field of Register T0C_LOW 364 * PIC: Periodic Interrupt Capable 365 * BitOffset : 4 366 * BitWidth : 1 367 * AccessType: RO 368 * ResetValue: (uint32_t)0x1 369 */ 370 SEDI_RBF_DEFINE(HPET, T0C_LOW, PIC, 4, 1, RO, (uint32_t)0x1); 371 SEDI_RBFV_DEFINE(HPET, T0C_LOW, PIC, 0, 0); 372 SEDI_RBFV_DEFINE(HPET, T0C_LOW, PIC, 1, 1); 373 374 /* 375 * Bit Field of Register T0C_LOW 376 * TS: Timer Size 377 * BitOffset : 5 378 * BitWidth : 1 379 * AccessType: RO 380 * ResetValue: (uint32_t)0x1 381 */ 382 SEDI_RBF_DEFINE(HPET, T0C_LOW, TS, 5, 1, RO, (uint32_t)0x1); 383 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TS, 0, 0); 384 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TS, 1, 1); 385 386 /* 387 * Bit Field of Register T0C_LOW 388 * TVS: Timer Value Set 389 * BitOffset : 6 390 * BitWidth : 1 391 * AccessType: RW_V 392 * ResetValue: (uint32_t)0x0 393 */ 394 SEDI_RBF_DEFINE(HPET, T0C_LOW, TVS, 6, 1, RW_V, (uint32_t)0x0); 395 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TVS, 0, 0); 396 SEDI_RBFV_DEFINE(HPET, T0C_LOW, TVS, 1, 1); 397 398 /* 399 * Bit Field of Register T0C_LOW 400 * RESERVED1: 401 * BitOffset : 7 402 * BitWidth : 1 403 * AccessType: RO 404 * ResetValue: (uint32_t)0x0 405 */ 406 SEDI_RBF_DEFINE(HPET, T0C_LOW, RESERVED1, 7, 1, RO, (uint32_t)0x0); 407 SEDI_RBFV_DEFINE(HPET, T0C_LOW, RESERVED1, 0, 0); 408 SEDI_RBFV_DEFINE(HPET, T0C_LOW, RESERVED1, 1, 1); 409 410 /* 411 * Bit Field of Register T0C_LOW 412 * T32M: Timer 32-Bit Mode 413 * BitOffset : 8 414 * BitWidth : 1 415 * AccessType: RW_V 416 * ResetValue: (uint32_t)0x0 417 */ 418 SEDI_RBF_DEFINE(HPET, T0C_LOW, T32M, 8, 1, RW_V, (uint32_t)0x0); 419 SEDI_RBFV_DEFINE(HPET, T0C_LOW, T32M, 0, 0); 420 SEDI_RBFV_DEFINE(HPET, T0C_LOW, T32M, 1, 1); 421 422 /* 423 * Bit Field of Register T0C_LOW 424 * IR: Interrupt Rout 425 * BitOffset : 9 426 * BitWidth : 5 427 * AccessType: RW_V 428 * ResetValue: (uint32_t)0x0 429 */ 430 SEDI_RBF_DEFINE(HPET, T0C_LOW, IR, 9, 5, RW_V, (uint32_t)0x0); 431 432 /* 433 * Bit Field of Register T0C_LOW 434 * FE: FSB Enable 435 * BitOffset : 14 436 * BitWidth : 1 437 * AccessType: RO 438 * ResetValue: (uint32_t)0x0 439 */ 440 SEDI_RBF_DEFINE(HPET, T0C_LOW, FE, 14, 1, RO, (uint32_t)0x0); 441 SEDI_RBFV_DEFINE(HPET, T0C_LOW, FE, 0, 0); 442 SEDI_RBFV_DEFINE(HPET, T0C_LOW, FE, 1, 1); 443 444 /* 445 * Bit Field of Register T0C_LOW 446 * FID: FSB Interrupt Delivery 447 * BitOffset : 15 448 * BitWidth : 1 449 * AccessType: RO 450 * ResetValue: (uint32_t)0x0 451 */ 452 SEDI_RBF_DEFINE(HPET, T0C_LOW, FID, 15, 1, RO, (uint32_t)0x0); 453 SEDI_RBFV_DEFINE(HPET, T0C_LOW, FID, 0, 0); 454 SEDI_RBFV_DEFINE(HPET, T0C_LOW, FID, 1, 1); 455 456 /* 457 * Bit Field of Register T0C_LOW 458 * RESERVED0: 459 * BitOffset : 16 460 * BitWidth : 16 461 * AccessType: RO 462 * ResetValue: (uint32_t)0x0 463 */ 464 SEDI_RBF_DEFINE(HPET, T0C_LOW, RESERVED0, 16, 16, RO, (uint32_t)0x0); 465 466 /* ********* HPET T0C_HIGH *********** 467 * 468 * Register of SEDI HPET 469 * T0C_HIGH: Timer N Config And Capabilities 470 * AddressOffset : 0x104 471 * AccessType : RO 472 * WritableBitMask: 0x0 473 * ResetValue : (uint32_t)0xf00000 474 */ 475 SEDI_REG_DEFINE(HPET, T0C_HIGH, 0x104, RO, (uint32_t)0x0, (uint32_t)0xf00000); 476 477 /* 478 * Bit Field of Register T0C_HIGH 479 * IRC: Interrupt Rout Capability 480 * BitOffset : 0 481 * BitWidth : 32 482 * AccessType: RO 483 * ResetValue: (uint32_t)0x0f00000 484 */ 485 SEDI_RBF_DEFINE(HPET, T0C_HIGH, IRC, 0, 32, RO, (uint32_t)0x0f00000); 486 487 /* ********* HPET T0CV_LOW *********** 488 * 489 * Register of SEDI HPET 490 * T0CV_LOW: Timer N Comparator Value 491 * AddressOffset : 0x108 492 * AccessType : RW 493 * WritableBitMask: 0xffffffff 494 * ResetValue : (uint32_t)-1 495 */ 496 SEDI_REG_DEFINE(HPET, T0CV_LOW, 0x108, RW, (uint32_t)0xffffffff, (uint32_t)-1); 497 498 /* 499 * Bit Field of Register T0CV_LOW 500 * T0CV_LOW: 501 * BitOffset : 0 502 * BitWidth : 32 503 * AccessType: RW_V 504 * ResetValue: (uint32_t)0x0ffffffff 505 */ 506 SEDI_RBF_DEFINE(HPET, T0CV_LOW, T0CV_LOW, 0, 32, RW_V, (uint32_t)0x0ffffffff); 507 508 /* ********* HPET T0CV_HIGH *********** 509 * 510 * Register of SEDI HPET 511 * T0CV_HIGH: Timer N Comparator Value 512 * AddressOffset : 0x10c 513 * AccessType : RW 514 * WritableBitMask: 0xffffffff 515 * ResetValue : (uint32_t)-1 516 */ 517 SEDI_REG_DEFINE(HPET, T0CV_HIGH, 0x10c, RW, (uint32_t)0xffffffff, (uint32_t)-1); 518 519 /* 520 * Bit Field of Register T0CV_HIGH 521 * T0CV_HIGH: 522 * BitOffset : 0 523 * BitWidth : 32 524 * AccessType: RW_V 525 * ResetValue: (uint32_t)0x0ffffffff 526 */ 527 SEDI_RBF_DEFINE(HPET, T0CV_HIGH, T0CV_HIGH, 0, 32, RW_V, (uint32_t)0x0ffffffff); 528 529 /* ********* HPET T1C_LOW *********** 530 * 531 * Register of SEDI HPET 532 * T1C_LOW: Timer N Config And Capabilities 533 * AddressOffset : 0x120 534 * AccessType : RW 535 * WritableBitMask: 0x3e06 536 * ResetValue : (uint32_t)0x0 537 */ 538 SEDI_REG_DEFINE(HPET, T1C_LOW, 0x120, RW, (uint32_t)0x3e06, (uint32_t)0x0); 539 540 /* 541 * Bit Field of Register T1C_LOW 542 * RESERVED2: 543 * BitOffset : 0 544 * BitWidth : 1 545 * AccessType: RO 546 * ResetValue: (uint32_t)0x0 547 */ 548 SEDI_RBF_DEFINE(HPET, T1C_LOW, RESERVED2, 0, 1, RO, (uint32_t)0x0); 549 SEDI_RBFV_DEFINE(HPET, T1C_LOW, RESERVED2, 0, 0); 550 SEDI_RBFV_DEFINE(HPET, T1C_LOW, RESERVED2, 1, 1); 551 552 /* 553 * Bit Field of Register T1C_LOW 554 * IT: Timer Interrupt Type 555 * BitOffset : 1 556 * BitWidth : 1 557 * AccessType: RW_V 558 * ResetValue: (uint32_t)0x0 559 */ 560 SEDI_RBF_DEFINE(HPET, T1C_LOW, IT, 1, 1, RW_V, (uint32_t)0x0); 561 SEDI_RBFV_DEFINE(HPET, T1C_LOW, IT, 0, 0); 562 SEDI_RBFV_DEFINE(HPET, T1C_LOW, IT, 1, 1); 563 564 /* 565 * Bit Field of Register T1C_LOW 566 * IE: Interrupt Enable 567 * BitOffset : 2 568 * BitWidth : 1 569 * AccessType: RW_V 570 * ResetValue: (uint32_t)0x0 571 */ 572 SEDI_RBF_DEFINE(HPET, T1C_LOW, IE, 2, 1, RW_V, (uint32_t)0x0); 573 SEDI_RBFV_DEFINE(HPET, T1C_LOW, IE, 0, 0); 574 SEDI_RBFV_DEFINE(HPET, T1C_LOW, IE, 1, 1); 575 576 /* 577 * Bit Field of Register T1C_LOW 578 * TYP: Timer Type 579 * BitOffset : 3 580 * BitWidth : 1 581 * AccessType: RO 582 * ResetValue: (uint32_t)0x0 583 */ 584 SEDI_RBF_DEFINE(HPET, T1C_LOW, TYP, 3, 1, RO, (uint32_t)0x0); 585 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TYP, 0, 0); 586 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TYP, 1, 1); 587 588 /* 589 * Bit Field of Register T1C_LOW 590 * PIC: Periodic Interrupt Capable 591 * BitOffset : 4 592 * BitWidth : 1 593 * AccessType: RO 594 * ResetValue: (uint32_t)0x0 595 */ 596 SEDI_RBF_DEFINE(HPET, T1C_LOW, PIC, 4, 1, RO, (uint32_t)0x0); 597 SEDI_RBFV_DEFINE(HPET, T1C_LOW, PIC, 0, 0); 598 SEDI_RBFV_DEFINE(HPET, T1C_LOW, PIC, 1, 1); 599 600 /* 601 * Bit Field of Register T1C_LOW 602 * TS: Timer Size 603 * BitOffset : 5 604 * BitWidth : 1 605 * AccessType: RO 606 * ResetValue: (uint32_t)0x0 607 */ 608 SEDI_RBF_DEFINE(HPET, T1C_LOW, TS, 5, 1, RO, (uint32_t)0x0); 609 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TS, 0, 0); 610 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TS, 1, 1); 611 612 /* 613 * Bit Field of Register T1C_LOW 614 * TVS: Timer Value Set 615 * BitOffset : 6 616 * BitWidth : 1 617 * AccessType: RO 618 * ResetValue: (uint32_t)0x0 619 */ 620 SEDI_RBF_DEFINE(HPET, T1C_LOW, TVS, 6, 1, RO, (uint32_t)0x0); 621 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TVS, 0, 0); 622 SEDI_RBFV_DEFINE(HPET, T1C_LOW, TVS, 1, 1); 623 624 /* 625 * Bit Field of Register T1C_LOW 626 * RESERVED1: 627 * BitOffset : 7 628 * BitWidth : 1 629 * AccessType: RO 630 * ResetValue: (uint32_t)0x0 631 */ 632 SEDI_RBF_DEFINE(HPET, T1C_LOW, RESERVED1, 7, 1, RO, (uint32_t)0x0); 633 SEDI_RBFV_DEFINE(HPET, T1C_LOW, RESERVED1, 0, 0); 634 SEDI_RBFV_DEFINE(HPET, T1C_LOW, RESERVED1, 1, 1); 635 636 /* 637 * Bit Field of Register T1C_LOW 638 * T32M: Timer 32-Bit Mode 639 * BitOffset : 8 640 * BitWidth : 1 641 * AccessType: RO 642 * ResetValue: (uint32_t)0x0 643 */ 644 SEDI_RBF_DEFINE(HPET, T1C_LOW, T32M, 8, 1, RO, (uint32_t)0x0); 645 SEDI_RBFV_DEFINE(HPET, T1C_LOW, T32M, 0, 0); 646 SEDI_RBFV_DEFINE(HPET, T1C_LOW, T32M, 1, 1); 647 648 /* 649 * Bit Field of Register T1C_LOW 650 * IR: Interrupt Route 651 * BitOffset : 9 652 * BitWidth : 5 653 * AccessType: RW_V 654 * ResetValue: (uint32_t)0x0 655 */ 656 SEDI_RBF_DEFINE(HPET, T1C_LOW, IR, 9, 5, RW_V, (uint32_t)0x0); 657 658 /* 659 * Bit Field of Register T1C_LOW 660 * FE: FSB Enable 661 * BitOffset : 14 662 * BitWidth : 1 663 * AccessType: RO 664 * ResetValue: (uint32_t)0x0 665 */ 666 SEDI_RBF_DEFINE(HPET, T1C_LOW, FE, 14, 1, RO, (uint32_t)0x0); 667 SEDI_RBFV_DEFINE(HPET, T1C_LOW, FE, 0, 0); 668 SEDI_RBFV_DEFINE(HPET, T1C_LOW, FE, 1, 1); 669 670 /* 671 * Bit Field of Register T1C_LOW 672 * FID: FSB Interrupt Delivery 673 * BitOffset : 15 674 * BitWidth : 1 675 * AccessType: RO 676 * ResetValue: (uint32_t)0x0 677 */ 678 SEDI_RBF_DEFINE(HPET, T1C_LOW, FID, 15, 1, RO, (uint32_t)0x0); 679 SEDI_RBFV_DEFINE(HPET, T1C_LOW, FID, 0, 0); 680 SEDI_RBFV_DEFINE(HPET, T1C_LOW, FID, 1, 1); 681 682 /* 683 * Bit Field of Register T1C_LOW 684 * RESERVED0: 685 * BitOffset : 16 686 * BitWidth : 16 687 * AccessType: RO 688 * ResetValue: (uint32_t)0x0 689 */ 690 SEDI_RBF_DEFINE(HPET, T1C_LOW, RESERVED0, 16, 16, RO, (uint32_t)0x0); 691 692 /* ********* HPET T1C_HIGH *********** 693 * 694 * Register of SEDI HPET 695 * T1C_HIGH: Timer N Config And Capabilities 696 * AddressOffset : 0x124 697 * AccessType : RO 698 * WritableBitMask: 0x0 699 * ResetValue : (uint32_t)0xf00000 700 */ 701 SEDI_REG_DEFINE(HPET, T1C_HIGH, 0x124, RO, (uint32_t)0x0, (uint32_t)0xf00000); 702 703 /* 704 * Bit Field of Register T1C_HIGH 705 * IRC: Interrupt Rout Capability 706 * BitOffset : 0 707 * BitWidth : 32 708 * AccessType: RO 709 * ResetValue: (uint32_t)0x0f00000 710 */ 711 SEDI_RBF_DEFINE(HPET, T1C_HIGH, IRC, 0, 32, RO, (uint32_t)0x0f00000); 712 713 /* ********* HPET T1CV_LOW *********** 714 * 715 * Register of SEDI HPET 716 * T1CV_LOW: Timer N Comparator Value 717 * AddressOffset : 0x128 718 * AccessType : RW 719 * WritableBitMask: 0xffffffff 720 * ResetValue : (uint32_t)-1 721 */ 722 SEDI_REG_DEFINE(HPET, T1CV_LOW, 0x128, RW, (uint32_t)0xffffffff, (uint32_t)-1); 723 724 /* 725 * Bit Field of Register T1CV_LOW 726 * T1CV: 727 * BitOffset : 0 728 * BitWidth : 32 729 * AccessType: RW_V 730 * ResetValue: (uint32_t)0x0ffffffff 731 */ 732 SEDI_RBF_DEFINE(HPET, T1CV_LOW, T1CV, 0, 32, RW_V, (uint32_t)0x0ffffffff); 733 734 /* ********* HPET T2C_LOW *********** 735 * 736 * Register of SEDI HPET 737 * T2C_LOW: Timer N Config And Capabilities 738 * AddressOffset : 0x140 739 * AccessType : RW 740 * WritableBitMask: 0x3e06 741 * ResetValue : (uint32_t)0x0 742 */ 743 SEDI_REG_DEFINE(HPET, T2C_LOW, 0x140, RW, (uint32_t)0x3e06, (uint32_t)0x0); 744 745 /* 746 * Bit Field of Register T2C_LOW 747 * RESERVED2: 748 * BitOffset : 0 749 * BitWidth : 1 750 * AccessType: RO 751 * ResetValue: (uint32_t)0x0 752 */ 753 SEDI_RBF_DEFINE(HPET, T2C_LOW, RESERVED2, 0, 1, RO, (uint32_t)0x0); 754 SEDI_RBFV_DEFINE(HPET, T2C_LOW, RESERVED2, 0, 0); 755 SEDI_RBFV_DEFINE(HPET, T2C_LOW, RESERVED2, 1, 1); 756 757 /* 758 * Bit Field of Register T2C_LOW 759 * IT: Timer Interrupt Type 760 * BitOffset : 1 761 * BitWidth : 1 762 * AccessType: RW_V 763 * ResetValue: (uint32_t)0x0 764 */ 765 SEDI_RBF_DEFINE(HPET, T2C_LOW, IT, 1, 1, RW_V, (uint32_t)0x0); 766 SEDI_RBFV_DEFINE(HPET, T2C_LOW, IT, 0, 0); 767 SEDI_RBFV_DEFINE(HPET, T2C_LOW, IT, 1, 1); 768 769 /* 770 * Bit Field of Register T2C_LOW 771 * IE: Interrupt Enable 772 * BitOffset : 2 773 * BitWidth : 1 774 * AccessType: RW_V 775 * ResetValue: (uint32_t)0x0 776 */ 777 SEDI_RBF_DEFINE(HPET, T2C_LOW, IE, 2, 1, RW_V, (uint32_t)0x0); 778 SEDI_RBFV_DEFINE(HPET, T2C_LOW, IE, 0, 0); 779 SEDI_RBFV_DEFINE(HPET, T2C_LOW, IE, 1, 1); 780 781 /* 782 * Bit Field of Register T2C_LOW 783 * TYP: Timer Type 784 * BitOffset : 3 785 * BitWidth : 1 786 * AccessType: RO 787 * ResetValue: (uint32_t)0x0 788 */ 789 SEDI_RBF_DEFINE(HPET, T2C_LOW, TYP, 3, 1, RO, (uint32_t)0x0); 790 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TYP, 0, 0); 791 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TYP, 1, 1); 792 793 /* 794 * Bit Field of Register T2C_LOW 795 * PIC: Periodic Interrupt Capable 796 * BitOffset : 4 797 * BitWidth : 1 798 * AccessType: RO 799 * ResetValue: (uint32_t)0x0 800 */ 801 SEDI_RBF_DEFINE(HPET, T2C_LOW, PIC, 4, 1, RO, (uint32_t)0x0); 802 SEDI_RBFV_DEFINE(HPET, T2C_LOW, PIC, 0, 0); 803 SEDI_RBFV_DEFINE(HPET, T2C_LOW, PIC, 1, 1); 804 805 /* 806 * Bit Field of Register T2C_LOW 807 * TS: Timer Size 808 * BitOffset : 5 809 * BitWidth : 1 810 * AccessType: RO 811 * ResetValue: (uint32_t)0x0 812 */ 813 SEDI_RBF_DEFINE(HPET, T2C_LOW, TS, 5, 1, RO, (uint32_t)0x0); 814 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TS, 0, 0); 815 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TS, 1, 1); 816 817 /* 818 * Bit Field of Register T2C_LOW 819 * TVS: Timer Value Set 820 * BitOffset : 6 821 * BitWidth : 1 822 * AccessType: RO 823 * ResetValue: (uint32_t)0x0 824 */ 825 SEDI_RBF_DEFINE(HPET, T2C_LOW, TVS, 6, 1, RO, (uint32_t)0x0); 826 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TVS, 0, 0); 827 SEDI_RBFV_DEFINE(HPET, T2C_LOW, TVS, 1, 1); 828 829 /* 830 * Bit Field of Register T2C_LOW 831 * RESERVED1: 832 * BitOffset : 7 833 * BitWidth : 1 834 * AccessType: RO 835 * ResetValue: (uint32_t)0x0 836 */ 837 SEDI_RBF_DEFINE(HPET, T2C_LOW, RESERVED1, 7, 1, RO, (uint32_t)0x0); 838 SEDI_RBFV_DEFINE(HPET, T2C_LOW, RESERVED1, 0, 0); 839 SEDI_RBFV_DEFINE(HPET, T2C_LOW, RESERVED1, 1, 1); 840 841 /* 842 * Bit Field of Register T2C_LOW 843 * T32M: Timer 32-Bit Mode 844 * BitOffset : 8 845 * BitWidth : 1 846 * AccessType: RO 847 * ResetValue: (uint32_t)0x0 848 */ 849 SEDI_RBF_DEFINE(HPET, T2C_LOW, T32M, 8, 1, RO, (uint32_t)0x0); 850 SEDI_RBFV_DEFINE(HPET, T2C_LOW, T32M, 0, 0); 851 SEDI_RBFV_DEFINE(HPET, T2C_LOW, T32M, 1, 1); 852 853 /* 854 * Bit Field of Register T2C_LOW 855 * IR: Interrupt Route 856 * BitOffset : 9 857 * BitWidth : 5 858 * AccessType: RW_V 859 * ResetValue: (uint32_t)0x0 860 */ 861 SEDI_RBF_DEFINE(HPET, T2C_LOW, IR, 9, 5, RW_V, (uint32_t)0x0); 862 863 /* 864 * Bit Field of Register T2C_LOW 865 * FE: FSB Enable 866 * BitOffset : 14 867 * BitWidth : 1 868 * AccessType: RO 869 * ResetValue: (uint32_t)0x0 870 */ 871 SEDI_RBF_DEFINE(HPET, T2C_LOW, FE, 14, 1, RO, (uint32_t)0x0); 872 SEDI_RBFV_DEFINE(HPET, T2C_LOW, FE, 0, 0); 873 SEDI_RBFV_DEFINE(HPET, T2C_LOW, FE, 1, 1); 874 875 /* 876 * Bit Field of Register T2C_LOW 877 * FID: FSB Interrupt Delivery 878 * BitOffset : 15 879 * BitWidth : 1 880 * AccessType: RO 881 * ResetValue: (uint32_t)0x0 882 */ 883 SEDI_RBF_DEFINE(HPET, T2C_LOW, FID, 15, 1, RO, (uint32_t)0x0); 884 SEDI_RBFV_DEFINE(HPET, T2C_LOW, FID, 0, 0); 885 SEDI_RBFV_DEFINE(HPET, T2C_LOW, FID, 1, 1); 886 887 /* 888 * Bit Field of Register T2C_LOW 889 * RESERVED0: 890 * BitOffset : 16 891 * BitWidth : 16 892 * AccessType: RO 893 * ResetValue: (uint32_t)0x0 894 */ 895 SEDI_RBF_DEFINE(HPET, T2C_LOW, RESERVED0, 16, 16, RO, (uint32_t)0x0); 896 897 /* ********* HPET T2C_HIGH *********** 898 * 899 * Register of SEDI HPET 900 * T2C_HIGH: Timer N Config And Capabilities 901 * AddressOffset : 0x144 902 * AccessType : RO 903 * WritableBitMask: 0x0 904 * ResetValue : (uint32_t)0xf00800 905 */ 906 SEDI_REG_DEFINE(HPET, T2C_HIGH, 0x144, RO, (uint32_t)0x0, (uint32_t)0xf00800); 907 908 /* 909 * Bit Field of Register T2C_HIGH 910 * IRC: Interrupt Rout Capability 911 * BitOffset : 0 912 * BitWidth : 32 913 * AccessType: RO 914 * ResetValue: (uint32_t)0x0f00800 915 */ 916 SEDI_RBF_DEFINE(HPET, T2C_HIGH, IRC, 0, 32, RO, (uint32_t)0x0f00800); 917 918 /* ********* HPET T2CV_LOW *********** 919 * 920 * Register of SEDI HPET 921 * T2CV_LOW: Timer N Comparator Value 922 * AddressOffset : 0x148 923 * AccessType : RW 924 * WritableBitMask: 0xffffffff 925 * ResetValue : (uint32_t)-1 926 */ 927 SEDI_REG_DEFINE(HPET, T2CV_LOW, 0x148, RW, (uint32_t)0xffffffff, (uint32_t)-1); 928 929 /* 930 * Bit Field of Register T2CV_LOW 931 * T2CV: 932 * BitOffset : 0 933 * BitWidth : 32 934 * AccessType: RW_V 935 * ResetValue: (uint32_t)0x0ffffffff 936 */ 937 SEDI_RBF_DEFINE(HPET, T2CV_LOW, T2CV, 0, 32, RW_V, (uint32_t)0x0ffffffff); 938 939 /* ********* HPET HPET_CTRL_STS *********** 940 * 941 * Register of SEDI HPET 942 * HPET_CTRL_STS: HPET Control And Status 943 * AddressOffset : 0x160 944 * AccessType : RW 945 * WritableBitMask: 0xc0000000 946 * ResetValue : (uint32_t)0x80000000 947 */ 948 SEDI_REG_DEFINE(HPET, HPET_CTRL_STS, 0x160, RW, (uint32_t)0xc0000000, (uint32_t)0x80000000); 949 950 /* 951 * Bit Field of Register HPET_CTRL_STS 952 * HPET_CTRL_STS0: 953 * BitOffset : 0 954 * BitWidth : 1 955 * AccessType: RO 956 * ResetValue: (uint32_t)0x0 957 */ 958 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS0, 0, 1, RO, (uint32_t)0x0); 959 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS0, 0, 0); 960 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS0, 1, 1); 961 962 /* 963 * Bit Field of Register HPET_CTRL_STS 964 * HPET_CTRL_STS1: 965 * BitOffset : 1 966 * BitWidth : 1 967 * AccessType: RO 968 * ResetValue: (uint32_t)0x0 969 */ 970 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS1, 1, 1, RO, (uint32_t)0x0); 971 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS1, 0, 0); 972 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS1, 1, 1); 973 974 /* 975 * Bit Field of Register HPET_CTRL_STS 976 * HPET_CTRL_STS2: 977 * BitOffset : 2 978 * BitWidth : 1 979 * AccessType: RO 980 * ResetValue: (uint32_t)0x0 981 */ 982 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS2, 2, 1, RO, (uint32_t)0x0); 983 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS2, 0, 0); 984 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS2, 1, 1); 985 986 /* 987 * Bit Field of Register HPET_CTRL_STS 988 * HPET_CTRL_STS3: 989 * BitOffset : 3 990 * BitWidth : 1 991 * AccessType: RO 992 * ResetValue: (uint32_t)0x0 993 */ 994 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS3, 3, 1, RO, (uint32_t)0x0); 995 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS3, 0, 0); 996 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS3, 1, 1); 997 998 /* 999 * Bit Field of Register HPET_CTRL_STS 1000 * HPET_CTRL_STS4: 1001 * BitOffset : 4 1002 * BitWidth : 1 1003 * AccessType: RO 1004 * ResetValue: (uint32_t)0x0 1005 */ 1006 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS4, 4, 1, RO, (uint32_t)0x0); 1007 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS4, 0, 0); 1008 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS4, 1, 1); 1009 1010 /* 1011 * Bit Field of Register HPET_CTRL_STS 1012 * HPET_CTRL_STS5: 1013 * BitOffset : 5 1014 * BitWidth : 1 1015 * AccessType: RO 1016 * ResetValue: (uint32_t)0x0 1017 */ 1018 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS5, 5, 1, RO, (uint32_t)0x0); 1019 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS5, 0, 0); 1020 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS5, 1, 1); 1021 1022 /* 1023 * Bit Field of Register HPET_CTRL_STS 1024 * HPET_CTRL_STS6: 1025 * BitOffset : 6 1026 * BitWidth : 1 1027 * AccessType: RO 1028 * ResetValue: (uint32_t)0x0 1029 */ 1030 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS6, 6, 1, RO, (uint32_t)0x0); 1031 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS6, 0, 0); 1032 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS6, 1, 1); 1033 1034 /* 1035 * Bit Field of Register HPET_CTRL_STS 1036 * HPET_CTRL_STS7: 1037 * BitOffset : 7 1038 * BitWidth : 1 1039 * AccessType: RO 1040 * ResetValue: (uint32_t)0x0 1041 */ 1042 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS7, 7, 1, RO, (uint32_t)0x0); 1043 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS7, 0, 0); 1044 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS7, 1, 1); 1045 1046 /* 1047 * Bit Field of Register HPET_CTRL_STS 1048 * HPET_CTRL_STS8: 1049 * BitOffset : 8 1050 * BitWidth : 1 1051 * AccessType: RO 1052 * ResetValue: (uint32_t)0x0 1053 */ 1054 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS8, 8, 1, RO, (uint32_t)0x0); 1055 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS8, 0, 0); 1056 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS8, 1, 1); 1057 1058 /* 1059 * Bit Field of Register HPET_CTRL_STS 1060 * HPET_CTRL_STS9: 1061 * BitOffset : 9 1062 * BitWidth : 1 1063 * AccessType: RO 1064 * ResetValue: (uint32_t)0x0 1065 */ 1066 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS9, 9, 1, RO, (uint32_t)0x0); 1067 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS9, 0, 0); 1068 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS9, 1, 1); 1069 1070 /* 1071 * Bit Field of Register HPET_CTRL_STS 1072 * HPET_CTRL_STS10: 1073 * BitOffset : 10 1074 * BitWidth : 1 1075 * AccessType: RO 1076 * ResetValue: (uint32_t)0x0 1077 */ 1078 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS10, 10, 1, RO, (uint32_t)0x0); 1079 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS10, 0, 0); 1080 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS10, 1, 1); 1081 1082 /* 1083 * Bit Field of Register HPET_CTRL_STS 1084 * HPET_CTRL_STS11: 1085 * BitOffset : 11 1086 * BitWidth : 1 1087 * AccessType: RO 1088 * ResetValue: (uint32_t)0x0 1089 */ 1090 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS11, 11, 1, RO, (uint32_t)0x0); 1091 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS11, 0, 0); 1092 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS11, 1, 1); 1093 1094 /* 1095 * Bit Field of Register HPET_CTRL_STS 1096 * HPET_CTRL_STS12: 1097 * BitOffset : 12 1098 * BitWidth : 1 1099 * AccessType: RO 1100 * ResetValue: (uint32_t)0x0 1101 */ 1102 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS12, 12, 1, RO, (uint32_t)0x0); 1103 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS12, 0, 0); 1104 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS12, 1, 1); 1105 1106 /* 1107 * Bit Field of Register HPET_CTRL_STS 1108 * HPET_CTRL_STS13: 1109 * BitOffset : 13 1110 * BitWidth : 1 1111 * AccessType: RO 1112 * ResetValue: (uint32_t)0x0 1113 */ 1114 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS13, 13, 1, RO, (uint32_t)0x0); 1115 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS13, 0, 0); 1116 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS13, 1, 1); 1117 1118 /* 1119 * Bit Field of Register HPET_CTRL_STS 1120 * HPET_CTRL_STS16_29: 1121 * BitOffset : 14 1122 * BitWidth : 16 1123 * AccessType: RO 1124 * ResetValue: (uint32_t)0x0 1125 */ 1126 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS16_29, 14, 16, RO, (uint32_t)0x0); 1127 1128 /* 1129 * Bit Field of Register HPET_CTRL_STS 1130 * HPET_CTRL_STS30: Write In Progress Status Bit Disable 1131 * BitOffset : 30 1132 * BitWidth : 1 1133 * AccessType: RW 1134 * ResetValue: (uint32_t)0x0 1135 */ 1136 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS30, 30, 1, RW, (uint32_t)0x0); 1137 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS30, 0, 0); 1138 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS30, 1, 1); 1139 1140 /* 1141 * Bit Field of Register HPET_CTRL_STS 1142 * HPET_CTRL_STS31: Enbale HPET Latency Fix 1143 * BitOffset : 31 1144 * BitWidth : 1 1145 * AccessType: RW_V 1146 * ResetValue: (uint32_t)0x1 1147 */ 1148 SEDI_RBF_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS31, 31, 1, RW_V, (uint32_t)0x1); 1149 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS31, 0, 0); 1150 SEDI_RBFV_DEFINE(HPET, HPET_CTRL_STS, HPET_CTRL_STS31, 1, 1); 1151 1152 /* 1153 * Registers' Address Map Structure 1154 */ 1155 1156 typedef struct { 1157 /* General Capabilities And ID */ 1158 __IO_R uint32_t gcid_low; 1159 1160 /* General Capabilities And ID */ 1161 __IO_R uint32_t gcid_high; 1162 1163 /* Reserved */ 1164 __IO_RW uint32_t reserved0[2]; 1165 1166 /* General Configuration */ 1167 __IO_RW uint32_t gcfg_low; 1168 1169 /* General Configuration */ 1170 __IO_R uint32_t gcfg_high; 1171 1172 /* Reserved */ 1173 __IO_RW uint32_t reserved1[2]; 1174 1175 /* General Interrupt Status */ 1176 __IO_RW uint32_t gis_low; 1177 1178 /* General Interrupt Status */ 1179 __IO_R uint32_t gis_high; 1180 1181 /* Reserved */ 1182 __IO_RW uint32_t reserved2[50]; 1183 1184 /* Main Counter Value */ 1185 __IO_RW uint32_t mcv_low; 1186 1187 /* Main Counter Value */ 1188 __IO_RW uint32_t mcv_high; 1189 1190 /* Reserved */ 1191 __IO_RW uint32_t reserved3[2]; 1192 1193 /* Timer N Config And Capabilities */ 1194 __IO_RW uint32_t t0c_low; 1195 1196 /* Timer N Config And Capabilities */ 1197 __IO_R uint32_t t0c_high; 1198 1199 /* Timer N Comparator Value */ 1200 __IO_RW uint32_t t0cv_low; 1201 1202 /* Timer N Comparator Value */ 1203 __IO_RW uint32_t t0cv_high; 1204 1205 /* Reserved */ 1206 __IO_RW uint32_t reserved4[4]; 1207 1208 /* Timer N Config And Capabilities */ 1209 __IO_RW uint32_t t1c_low; 1210 1211 /* Timer N Config And Capabilities */ 1212 __IO_R uint32_t t1c_high; 1213 1214 /* Timer N Comparator Value */ 1215 __IO_RW uint32_t t1cv_low; 1216 1217 /* Reserved */ 1218 __IO_RW uint32_t reserved5[5]; 1219 1220 /* Timer N Config And Capabilities */ 1221 __IO_RW uint32_t t2c_low; 1222 1223 /* Timer N Config And Capabilities */ 1224 __IO_R uint32_t t2c_high; 1225 1226 /* Timer N Comparator Value */ 1227 __IO_RW uint32_t t2cv_low; 1228 1229 /* Reserved */ 1230 __IO_RW uint32_t reserved6[5]; 1231 1232 /* HPET Control And Status */ 1233 __IO_RW uint32_t hpet_ctrl_sts; 1234 1235 } sedi_hpet_regs_t; 1236 1237 1238 #endif /* _SEDI_HPET_REGS_H_ */ 1239
