1 /***************************************************************************//** 2 * \file system_cat1c.h 3 * \version 1.0 4 * 5 * \brief Device system header file. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2021 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 26 #ifndef _SYSTEM_FACELIFT_H_ 27 #define _SYSTEM_FACELIFT_H_ 28 29 /** 30 * \addtogroup group_system_config_cm7 31 * \{ 32 * Provides device startup, system configuration, and linker script files. 33 * The system startup provides the followings features: 34 * - \ref group_system_config_device_memory_definition_cm7 35 * - \ref group_system_config_device_initialization_cm7 36 * - \ref group_system_config_heap_stack_config_cm7 37 * - \ref group_system_config_default_handlers_cm7 38 * - \ref group_system_config_device_vector_table_cm7 39 * - \ref group_system_config_cm7_functions 40 * 41 * \section group_system_config_configuration_cm7 Configuration Considerations 42 * 43 * \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition 44 * Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts. 45 * 46 * \note - The linker files provided with the PDL are generic and handle all common 47 * use cases. Your project may not use every section defined in the linker files. 48 * In that case you may see warnings during the build process. To eliminate build 49 * warnings in your project, you can simply comment out or remove the relevant 50 * code in the linker file. 51 * 52 * \note - There is a common linker script for both CM7_0 and CM7_1 core. 53 * By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system. 54 * For example, below piece of code is implemented in the build system. 55 * \code 56 * ifeq ($(TOOLCHAIN),IAR) 57 * LDFLAGS += --config_def _CORE_cm7_1_=1 58 * else ifeq ($(TOOLCHAIN),GCC_ARM) 59 * LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1' 60 * endif 61 * \endcode 62 * 63 * <b>ARM GCC</b>\n 64 * The flash and RAM sections for the CPU are defined in the linker files: 65 * 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; 66 * for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. 67 * \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value 68 * of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The 69 * \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the 70 * Cy_SysEnableCM7() function call. 71 * By default, 72 * - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). 73 * - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). 74 * 75 * Change the flash and RAM sizes by editing the macro values in the 76 * linker files for both CPUs: 77 * - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group: 78 * \code 79 * cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P 80 * cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P 81 * \endcode 82 * - 'xx_yy_cm7.ld', where 'xx_yy' is the device group: 83 * \code 84 * ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM 85 * flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P 86 * flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH 87 * \endcode 88 * 89 * Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR 90 * macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE 91 * value (0x80000, the size of a flash image of the Cortex-M0+ application should be the 92 * same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file, 93 * where 'xx_yy' is the device group. 94 * 95 * - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value 96 * in the 'system_xx.h', where 'xx' is the device family:\n 97 * \code 98 * #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 99 * #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 100 * \endcode 101 * 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h 102 * 103 * <b>ARM Compiler</b>\n 104 * The flash and RAM sections for the CPU are defined in the linker files: 105 * 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; 106 * for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. 107 * 108 * \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value 109 * of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The 110 * \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the 111 * Cy_SysEnableCM7() function call. 112 * By default, 113 * - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). 114 * - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). 115 * 116 * \note The linker files provided with the PDL are generic and handle all common 117 * use cases. Your project may not use every section defined in the linker files. 118 * In that case you may see the warnings during the build process: 119 * L6314W (no section matches pattern) and/or L6329W 120 * (pattern only matches removed unused sections). In your project, you can 121 * suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to 122 * the linker. You can also comment out or remove the relevant code in the linker 123 * file. 124 * 125 * Change the flash and RAM sizes by editing the macros value in the 126 * linker files for both CPUs: 127 * - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group: 128 * \code 129 * #define SRAM_BASE_ADDRESS 0x28000000 130 * #define CM0PLUS_SRAM_RESERVE 0x00020000 131 * #define CODE_FLASH_BASE_ADDRESS 0x10000000 132 * #define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 133 * \endcode 134 * - 'xx_yy_cm7.sct', where 'xx_yy' is the device group: 135 * \code 136 * #define SRAM_BASE_ADDRESS 0x28000000 //SRAM START 137 * #define CM7_0_SRAM_RESERVE 0x00060000 //cm7_0 sram size 138 * #define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE 139 * #define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE 140 * //In case of dual CM7-core MCU device device 141 * #define SIZE_SRAM_CM7_1 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE 142 * #define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE 143 * 144 * #define CODE_FLASH_BASE_ADDRESS 0x10000000 //FLASH START 145 * #define CM7_0_CODE_FLASH_RESERVE 0x00200000 //cm7_0 flash size 146 * #define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE 147 * #define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE 148 * //In case of dual CM7-core MCU device device 149 * #define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE 150 * #define SIZE_CODE_FLASH_CM7_1 CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE 151 * \endcode 152 * 153 * Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR 154 * macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE 155 * value (0x80000, the size of a flash image of the Cortex-M0+ application should be the 156 * same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file, 157 * where 'xx_yy' is the device group. 158 * 159 * - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value 160 * in the 'system_xx.h', where 'xx' is the device family:\n 161 * \code 162 * #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 163 * #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 164 * \endcode 165 * 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h 166 167 * <b>IAR</b>\n 168 * The flash and RAM sections for the CPU are defined in the linker files: 169 * 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 170 * 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. 171 * \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value 172 * of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The 173 * \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the 174 * Cy_SysEnableCM7() function call. 175 * By default, 176 * - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). 177 * - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). 178 * 179 * Change the flash and RAM sizes by editing the macros value in the 180 * linker files for both CPUs: 181 * - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group: 182 * \code 183 * define symbol sram_base_address = 0x28000000; 184 * define symbol cm0plus_sram_reserve = 0x00020000; //cm0 sram size 185 * define symbol code_flash_base_address = 0x10000000; 186 * define symbol cm0plus_code_flash_reserve = 0x00080000; //cm0 flash size 187 * \endcode 188 * - 'xx_yy_cm7.icf', where 'xx_yy' is the device group: 189 * \code 190 * define symbol sram_base_address = 0x28000000; 191 * define symbol cm7_0_sram_reserve = 0x00060000; 192 * define symbol _base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve; 193 * define symbol _size_SRAM_CM7_0 = cm7_0_sram_reserve; 194 * //In case of dual CM7-core MCU device device 195 * define symbol _base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve; 196 * define symbol _size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve; 197 * 198 * define symbol code_flash_base_address = 0x10000000; 199 * define symbol cm7_0_code_flash_reserve = 0x00200000; 200 * define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve; 201 * define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve; 202 * //In case of dual CM7-core MCU device device 203 * define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve; 204 * define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve; 205 * \endcode 206 * 207 * Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR 208 * macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE 209 * value (0x80000, the size of a flash image of the Cortex-M0+ application should be the 210 * same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file, 211 * where 'xx_yy' is the device group. 212 * 213 * - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value 214 * in the 'system_xx.h', where 'xx' is the device family:\n 215 * \code 216 * #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 217 * #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 218 * \endcode 219 * 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h 220 * 221 * \subsection group_system_config_device_initialization_cm7 Device Initialization 222 * After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup. 223 * The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup. 224 * The startup code is the piece of code which is executed after every system reset. 225 * It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function. 226 * The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core. 227 * 228 * The CM0+ startup code implements the following functions to run the CM0+ application: 229 * 230 * 1. In the Reset Handler, it disables global interrupts 231 * 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core, 232 * sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet. 233 * 4. Calls SystemInit() function 234 * - Initializes and enables the SRAM memory for ECC 235 * - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register) 236 * - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority, 237 * then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1. 238 * So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1 239 * - Unlocks and disable WDT (Watchdog timer) 240 * - Calls the SystemCoreClockUpdate() 241 * 5. Executes main() application 242 * 243 * The CM7 startup code implement the following functions to run the CM7 user application: 244 * 245 * 1. In the Reset handler, it disables global interrupts 246 * 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register 247 * 3. Enables CM7 core ITCM and DTCM 248 * 4. Enables the FPU if it is used 249 * 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register) 250 * 6. Enables the CM7 core instruction and data cache 251 * 7. Calls SystemInit() function 252 * - Unlocks and disable WDT (Watchdog timer) 253 * - Calls the SystemCoreClockUpdate() 254 * 6. Executes CM7 main() application 255 * 256 * \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration 257 * By default, the stack size is set to 0x00001000 and the Heap size is allocated 258 * dynamically to the whole available free memory up to stack memory. 259 * The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address. 260 * The Heap grows opposite of Stack. It grows from lower to higher address. 261 * The Heap top starts from end of used data section till Stack end. 262 * 263 * \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC 264 * <b>Editing source code files</b>\n 265 * The stack size is defined in the linker script files: 'xx_yy_zz.ld', 266 * 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 267 * 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. 268 * Change the stack size by modifying the following line:\n 269 * \code STACK_SIZE = 0x1000; \endcode 270 * 271 * \note Correct operation of malloc and related functions depends on the working 272 * implementation of the 'sbrk' function. Newlib-nano (default C runtime library 273 * used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that 274 * doesn't check for heap and stack collisions during excessive memory allocations. 275 * To ensure the heap always remains within the range defined by __HeapBase and 276 * __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: 277 * \snippet startup/snippet/main.c snippet_sbrk 278 * For FreeRTOS-enabled multi-threaded applications, it is sufficient to include 279 * clib-support library that provides newlib-compatible implementations of 280 * 'sbrk', '__malloc_lock' and '__malloc_unlock': 281 * <br> 282 * https://github.com/Infineon/clib-support. 283 * 284 * \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler 285 * <b>Editing source code files</b>\n 286 * The stack size is defined in the linker script files: 'xx_yy_zz.sct', 287 * 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 288 * 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. 289 * Change the stack size by modifying the following line:\n 290 * \code #define STACK_SIZE 0x1000 \endcode 291 * 292 * \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR 293 * <b>Editing source code files</b>\n 294 * The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf', 295 * where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 296 * 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. 297 * Change the heap and stack sizes by modifying the following lines:\n 298 * \code define symbol cm7_stack_reserve = 0x00001000; \endcode 299 * 300 * \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition 301 * The default interrupt handler functions are defined as weak functions to a dummy 302 * handler in the startup file. The naming convention for the interrupt handler names 303 * is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in 304 * user code by defining the handler function using the same name. For example: 305 * \code 306 * void scb_0_interrupt_IRQHandler(void) 307 *{ 308 * ... 309 *} 310 * \endcode 311 * 312 * \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM 313 * This process uses memory sections defined in the linker script. The startup 314 * code actually defines the contents of the vector table and performs the copy. 315 * 316 * \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC 317 * The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; 318 * for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. 319 * It defines sections and locations in memory.\n 320 * Copy interrupt vectors from flash to RAM: \n 321 * From: \code LONG (__Vectors) \endcode 322 * To: \code LONG (__ram_vectors_start__) \endcode 323 * Size: \code LONG (__Vectors_End - __Vectors) \endcode 324 * The vector table address (and the vector table itself) are defined in the 325 * startup files (e.g. startup_cm0plus.S and startup_cm7.c). 326 * The code in these files copies the vector table from Flash to RAM. 327 * 328 * \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler 329 * The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; 330 * for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 331 * 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table 332 * (RESET_RAM) shall be first in the RAM section.\n 333 * RESET_RAM represents the vector table. It is defined in the startup 334 * files (e.g. startup_cm0plus.S and startup_cm7.c). 335 * The code in these files copies the vector table from Flash to RAM. 336 * 337 * \subsubsection group_system_config_device_vector_table_iar_cm7 IAR 338 * The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; 339 * for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and ' 340 * 'xmc7100d_x4160_cm0plus.icf'.\n 341 * The vector table address (and the vector table itself) are defined in the 342 * startup files (e.g. startup_cm0plus.S and startup_cm7.c). 343 * The code in these files copies the vector table from Flash to RAM. 344 * 345 * \section group_system_config_changelog_cm7 Changelog 346 * <table class="doxtable"> 347 * <tr> 348 * <th>Version</th> 349 * <th>Changes</th> 350 * <th>Reason for Change</th> 351 * </tr> 352 * <tr> 353 * <td>1.0</td> 354 * <td>Initial version</td> 355 * <td></td> 356 * </tr> 357 * </table> 358 * 359 * \defgroup group_system_config_macro_cm7 Macros 360 * \{ 361 * \defgroup group_system_config_system_macro_cm7 System Macros 362 * \} 363 * \defgroup group_system_config_functions_cm7 Functions 364 * \{ 365 * \defgroup group_system_config_cm7_functions Cortex-M7 Control 366 * \} 367 * \} 368 */ 369 #ifdef __cplusplus 370 extern "C" { 371 #endif 372 373 374 /******************************************************************************* 375 * Include files 376 *******************************************************************************/ 377 #include <stdint.h> 378 #include "xmc7xxx_partition.h" 379 380 /******************************************************************************* 381 * Global preprocessor symbols/macros ('define') 382 *******************************************************************************/ 383 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 384 (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 385 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) 386 #define CY_SYSTEM_CPU_CM0P 1UL 387 #else 388 #define CY_SYSTEM_CPU_CM0P 0UL 389 #endif 390 391 392 /******************************************************************************* 393 * 394 * START OF USER SETTINGS HERE 395 * =========================== 396 * 397 * All lines with '<<<' can be set by user. 398 * 399 *******************************************************************************/ 400 401 /** 402 * \addtogroup group_system_config_system_macro_cm7 403 * \{ 404 */ 405 406 /******************************************************************************* 407 * 408 * END OF USER SETTINGS HERE 409 * ========================= 410 * 411 *******************************************************************************/ 412 413 /** Start address of the Cortex-M7_0 application */ 414 #ifndef CY_CORTEX_M7_0_APPL_ADDR 415 #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 416 #endif 417 418 /** Start address of the Cortex-M7_1 application */ 419 #ifndef CY_CORTEX_M7_1_APPL_ADDR 420 #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 421 #endif 422 423 /** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */ 424 #define CY_SYS_CM7_STATUS_ENABLED (3U) 425 /** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */ 426 #define CY_SYS_CM7_STATUS_DISABLED (0U) 427 /** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */ 428 #define CY_SYS_CM7_STATUS_RETAINED (2U) 429 /** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */ 430 #define CY_SYS_CM7_STATUS_RESET (1U) 431 /** \} group_system_config_system_macro_cm7 */ 432 433 /** \cond */ 434 /** Cortex-M7 core 0 */ 435 #define CORE_CM7_0 (0U) 436 /** Cortex-M7 core 1 */ 437 #define CORE_CM7_1 (1U) 438 /** Error Selection */ 439 #define CORE_MAX (2U) 440 441 /** Define start of the function placed to the ITCM area by the linker */ 442 #ifndef CY_SECTION_ITCM_BEGIN 443 #define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm") 444 #endif 445 446 /** Define end of the function placed to the ITCM area by the linker */ 447 #ifndef CY_SECTION_ITCM_END 448 #define CY_SECTION_ITCM_END 449 #endif 450 451 extern uint32_t cy_delayFreqHz; 452 extern uint32_t cy_delayFreqKhz; 453 extern uint32_t cy_delayFreqMhz; 454 455 extern uint32_t SystemCoreClock; 456 extern uint32_t cy_Hfclk0FreqHz; 457 extern uint32_t cy_PeriClkFreqHz; 458 extern uint32_t cy_AhbFreqHz; 459 460 extern void SystemInit(void); 461 extern void SystemIrqInit(void); 462 extern void SystemCoreClockUpdate(void); 463 464 /** \endcond */ 465 466 /** 467 * \addtogroup group_system_config_cm7_functions 468 * \{ 469 */ 470 /******************************************************************************* 471 * Function Name: Cy_SysGetCM7Status 472 ****************************************************************************//** 473 * 474 * Gets the Cortex-M7 core power mode. 475 * 476 * \param core Core type (CM7_0 or CM7_1). 477 * 478 * \return \ref group_system_config_system_macro_cm7 \n 479 * If 0: CY_SYS_CM7_STATUS_DISABLED \n 480 * 1: CY_SYS_CM7_STATUS_RESET \n 481 * 2: CY_SYS_CM7_STATUS_RETAINED \n 482 * 3: CY_SYS_CM7_STATUS_ENABLED \n 483 * 484 ******************************************************************************/ 485 extern uint32_t Cy_SysGetCM7Status(uint8_t core); 486 /******************************************************************************* 487 * Function Name: Cy_SysEnableCM7 488 ****************************************************************************//** 489 * 490 * Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled 491 * or retained mode. 492 * 493 * \param core Core type (CM7_0 or CM7_1). 494 * 495 * \param vectorTableOffset The offset of the vector table base address from 496 * memory address 0x00000000. The offset should be multiple to 1024 bytes. 497 * 498 *******************************************************************************/ 499 extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset); 500 /******************************************************************************* 501 * Function Name: Cy_SysDisableCM7 502 ****************************************************************************//** 503 * 504 * Disables the Cortex-M7 core. 505 * 506 * \param core Core type (CM7_0 or CM7_1). 507 * 508 * \warning Do not call the function while the Cortex-M7 is executing because 509 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause 510 * unexpected behavior in the system including a deadlock. Call the function 511 * while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use 512 * the \ref group_syspm Power Management (syspm) API to put the CPU into the 513 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. 514 * 515 *******************************************************************************/ 516 extern void Cy_SysDisableCM7(uint8_t core); 517 /******************************************************************************* 518 * Function Name: Cy_SysRetainCM7 519 ****************************************************************************//** 520 * 521 * Retains the Cortex-M7 core. 522 * 523 * \param core Core type (CM7_0 or CM7_1). 524 * 525 * \warning Do not call the function while the Cortex-M7 is executing because 526 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause 527 * unexpected behavior in the system including a deadlock. Call the function 528 * while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use 529 * the \ref group_syspm Power Management (syspm) API to put the CPU into the 530 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. 531 * 532 *******************************************************************************/ 533 extern void Cy_SysRetainCM7(uint8_t core); 534 /******************************************************************************* 535 * Function Name: Cy_SysResetCM7 536 ****************************************************************************//** 537 * 538 * Resets the Cortex-M7 core. 539 * 540 * \param core Core type (CM7_0 or CM7_1). 541 * 542 * \warning Do not call the function while the Cortex-M7 is executing because 543 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause 544 * unexpected behavior in the system including a deadlock. Call the function 545 * while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use 546 * the \ref group_syspm Power Management (syspm) API to put the CPU into the 547 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. 548 * 549 *******************************************************************************/ 550 extern void Cy_SysResetCM7(uint8_t core); 551 /** \} group_system_config_cm7_functions */ 552 553 554 /** \cond */ 555 556 extern void Default_Handler (void); 557 558 extern void Cy_SystemInit(void); 559 extern void Cy_SystemInitFpuEnable(void); 560 extern void CyMain(void); 561 562 #define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection 563 #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection 564 /** \endcond */ 565 566 567 568 569 570 571 #ifdef __cplusplus 572 } 573 #endif 574 575 #endif /* _SYSTEM_FACELIFT_H_ */ 576 577 578 /* [] END OF FILE */ 579
