1 /***************************************************************************//** 2 * \file system_cat1b.h 3 * \version 1.2 4 * 5 * \brief CAT1B Device system header file. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2016-2021 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 26 #ifndef _SYSTEM_CAT1B_H_ 27 #define _SYSTEM_CAT1B_H_ 28 29 /** 30 * \addtogroup group_system_config_cm33 31 * \{ 32 * Provides device startup, system configuration, and linker script files. 33 * The system startup provides the followings features: 34 * - \ref group_system_config_device_memory_definition_cm33 35 * - \ref group_system_config_device_initialization_cm33 36 * - \ref group_system_config_heap_stack_config_cm33 37 * - \ref group_system_config_default_handlers_cm33 38 * - \ref group_system_config_device_vector_table_cm33 39 * 40 * \section group_system_config_configuration_cm33 Configuration Considerations 41 * 42 * \subsection group_system_config_device_memory_definition_cm33 Device Memory Definition 43 * Allocation of different types of memory such as the ROM, flash and RAM etc. for the CPU is defined by the linker scripts. 44 * 45 * \note The linker files provided with the PDL are generic and handle all common 46 * use cases. Your project may not use every section defined in the linker files. 47 * In that case you may see warnings during the build process. To eliminate build 48 * warnings in your project, you can simply comment out or remove the relevant 49 * code in the linker file. 50 * 51 * <b>For CYW20829</b> 52 * 53 * <b>ARM GCC</b>\n 54 * The ROM, flash and RAM sections for the CPU are defined in the linker file: 55 * 'cyw20829_ns_flash_cbus.ld', where 'ns' indicates that the 56 * linker script file is for non-secure image. 57 * For devices without security extension, there will be only one linker file and it 58 * is always non-secure. 59 * 60 * Memory sections are for the GNU GCC ARM tool set is defined in the linker file 61 * cyw20829_ns_flash_cbus.ld. Following are the important memory sections for the User/Application image. 62 * 63 * Memory sections are for the GNU GCC ARM tool set is defined in the linker file 64 * \<device\>_ns.sct. Following are the important memory sections for the User/Application image. 65 * \code 66 * code (rx) : ORIGIN = CODE_VMA, LENGTH = CODE_BS_SIZE Starting address and the size of Non-secure bootstrap code 67 * bsData (rwx) : ORIGIN = DATA_BS_VMA, LENGTH = DATA_BS_SIZE Starting address and the size of Non-secure bootstrap data 68 * appCodeRam (rx) : ORIGIN = DATA_CBUS_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application ram functions 69 * data (rwx) : ORIGIN = DATA_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application data 70 * xip (rx) : ORIGIN = XIP_VMA, LENGTH = XIP_SIZE Starting address and the size of Non-secure application code 71 * \endcode 72 * 73 * \note In CYW20829, the Bootstrap memory is used to place the startup code along with SMIF driver in the ram area. The size requirement for Bootstrap may vary 74 * depending on the number of functions that are linked from SMIF driver. When more functions are linked, you may see linker error. 75 * In order to fix this you need to increase Bootstarp memory size in the ram by modifying the value of BOOTSTRAP_OFFSET_RAM.\n 76 * E.g. if linker error suggests to increase by 8192 bytes, then you need to move the starting address of the bootstrap memory up by 8192 bytes as shown below \n 77 * BOOTSTRAP_OFFSET_RAM = 0x0001E000; Old value\n 78 * BOOTSTRAP_OFFSET_RAM = 0x0001C000; New value\n 79 * Because of the change in the bootstrap size, you may also need to move the application start address in the flash. If you see a linker error after above change, 80 * then you need to modify the application code offset APPCODE_OFFSET_FLASH in the flash.\n 81 * E.g. if linker error suggests 256 bytes overlap of .appText LMA with .bootstrapText LMA, you need to move the application start offset in the flash 82 * down by 256 bytes as shown below\n 83 * APPCODE_OFFSET_FLASH = 0x00002200; Old value\n 84 * APPCODE_OFFSET_FLASH = 0x00002300; New value 85 * 86 * <b>ARM Compiler</b>\n 87 * The ROM, flash and RAM sections for the CPU are defined in the linker file: 88 * 'cyw20829_ns_flash_cbus.sct', where 'ns' indicates that the 89 * linker script file is for non-secure image. 90 * For devices without security extension, there will be only one linker file and it 91 * is always non-secure. 92 * 93 * Memory sections are for the GNU GCC ARM tool set is defined in the linker file 94 * cyw20829_ns_flash_cbus.sct. Following are the important memory sections for the User/Application image. 95 * \code 96 * bootstrapText_vma Starting address of bootstrap code 97 * bootstrapText_size Size of memory reserved for Bootstrap code 98 * bootstrapData_vma Starting address of Bootstrap data 99 * appText_vma Stating address of application code 100 * appData_vma Stating address of application data 101 * \endcode 102 * 103 * <b>IAR</b>\n 104 * The ROM, flash and RAM sections for the CPU are defined in the linker file: 105 * 'cyw20829_ns_flash_cbus.icf', where 'ns' indicates that the 106 * linker script file is for non-secure image. 107 * For devices without security extension, there will be only one linker file and it 108 * is always non-secure. 109 * 110 * Memory sections are for the GNU GCC ARM tool set is defined in the linker file 111 * cyw20829_ns_flash_cbus.icf. Following are the important memory sections for the User/Application image. 112 * \code 113 * define region CODE_region = mem:[from CODE_VMA size CODE_BS_SIZE]; Bootstrap code region and size 114 * define region DATA_BS_region = mem:[from DATA_BS_VMA size DATA_BS_SIZE]; Bootstrap data region and size 115 * define region DATA_region = mem:[from DATA_VMA size DATA_SIZE]; Application data region and size 116 * define region XIP_region = mem:[from XIP_VMA size XIP_SIZE]; Application code (xip) region and size 117 * \endcode 118 * 119 * \subsection group_system_config_device_initialization_cm33 Device Initialization 120 * <b>CM33 Without ARM TrustZone Support:</b><br/> 121 * Below MSC describes the simplified startup sequence starting from reset release of the core. As soon as the reset 122 * is released, the execution starts form the ROM interrupt vector table reset vector. The ROM code initializes the basic 123 * clock needed to access and configure MMIO registers and then sets up debug port so that the debugger can be attached. 124 * After it finishes all the necessary initialization, it reads the bootstrap (part of non secure application image) 125 * location, size from TOC2 header and loads the bootstrap code into SRAM. 126 * 127 * Before switching execution to the non-secure application code, the ROM code needs to initialize the stack pointer 128 * MSP_NS for the non-secure code. This value is picked form the first entry in the non-secure bootstrap's vector 129 * table __ns_vector_table. Once the non-secure stack is initialized, the ROM code will call the non-secure code entry 130 * point which is nothing but the Reset_Handler. Address of this function is picked form the second entry in the non-secure 131 * vector table __ns_vector_table and type casting it to function pointer. 132 * 133 * In the non-secure Reset_Handler, the vector table is copied to RAM area and then the address of the vector table is set 134 * to VTOR register. This calls SystemInit function which internally calls Cy_PDL_Init, Cy_SystemInit and SystemCoreClockUpdate 135 * functions. Then it calls C runtime initialization function which calls main function of the application code. 136 * 137 * Below sequence diagram captures the initialization process in the startup code. 138 *  139 * 140 * \subsection group_system_config_heap_stack_config_cm33 Heap and Stack Configuration 141 * By default, the stack size is set to 0x00001000 and the entire remaining ram is used for the heap 142 * 143 * \subsubsection group_system_config_heap_stack_config_gcc_cm33 ARM GCC 144 * - <b>Editing source code files for non-secure image</b>\n 145 * The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.ld'. 146 * Change the stack size by modifying the following line:\n 147 * \code STACK_SIZE = 0x00001000; \endcode 148 * Remaining free RAM is used as heap. 149 * 150 * \note Correct operation of malloc and related functions depends on the working 151 * implementation of the 'sbrk' function. Newlib-nano (default C runtime library 152 * used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that 153 * doesn't check for heap and stack collisions during excessive memory allocations. 154 * To ensure the heap always remains within the range defined by __HeapBase and 155 * __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: 156 * \snippet startup/snippet/main.c snippet_sbrk_cm33 157 * For FreeRTOS-enabled multi-threaded applications, it is sufficient to include 158 * clib-support library that provides newlib-compatible implementations of 159 * 'sbrk', '__malloc_lock' and '__malloc_unlock': 160 * <br> 161 * https://github.com/Infineon/clib-support. 162 * 163 * \subsubsection group_system_config_heap_stack_config_arm_cm33 ARM Compiler 164 * - <b>Editing source code files for non-secure image</b>\n 165 * The stack sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.sct'. 166 * Change the stack by modifying the following lines:\n 167 * \code #define STACK_SIZE 0x00001000 \endcode 168 * Remaining free RAM is used as heap. 169 * 170 * \subsubsection group_system_config_heap_stack_config_iar_cm33 IAR 171 * - <b>Editing source code files for non-secure image</b>\n 172 * The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.icf'. 173 * Change the stack size by modifying the following line:\n 174 * \code define symbol STACK_SIZE = 0x00001000; \endcode 175 * Remaining free RAM is used as heap. 176 * 177 * \subsection group_system_config_default_handlers_cm33 Default Interrupt Handlers Definition 178 * The default interrupt handler functions are dummy handler in the startup file.\n 179 * Below is the default handler for the non-secure interrupts:\n 180 * \code interrupt_type void InterruptHandler(void) { 181 * while(1); 182 * } \endcode 183 * 184 * \subsection group_system_config_device_vector_table_cm33 Vectors Table Copy from ROM/Flash to RAM 185 * This process uses memory sections defined in the linker script. The startup code copies the 186 * default vector table contents to the non-secure SRAM region specified by the linker script. 187 * APIs are provided in the sysint driver to hook user implemented handler replacing the default 188 * handler for the corresponding interrupt. 189 * 190 * Following tables provide the address of the default and non-secure SRAM interrupt vector 191 * table for different supported compilers. 192 * \subsubsection group_system_config_device_vector_table_gcc_cm33 ARM GCC 193 * The linker script file is 'cyw20829_ns_flash_cbus.ld'. 194 * For non-secure world, it uses the following variable.\n 195 * Copy interrupt vectors from ROM/flash to RAM: \n 196 * From: \code __ns_vector_table \endcode 197 * To: \code __ns_vector_table_rw \endcode 198 * The vector table address (and the vector table itself) are defined in the 199 * ns_start_<device>.c startup file corresponding to non-secure world. 200 * The code in these files copies the vector table from ROM/Flash to RAM. 201 * 202 * \subsubsection group_system_config_device_vector_table_mdk_cm33 ARM Compiler 203 * The linker script file is 'cyw20829_ns_flash_cbus.sct'. 204 * For non-secure world, it uses the following variable.\n 205 * Copy interrupt vectors from ROM/flash to RAM: \n 206 * From: \code __ns_vector_table \endcode 207 * To: \code __ns_vector_table_rw \endcode 208 * The vector table address (and the vector table itself) are defined in the 209 * ns_start_<device>.c startup file corresponding to non-secure world. 210 * The code in these files copies the vector table from ROM/Flash to RAM. 211 * 212 * \subsubsection group_system_config_device_vector_table_iar_cm33 IAR 213 * The linker script file is 'cyw20829_ns_flash_cbus.icf'. 214 * For non-secure world, it uses the following variable.\n 215 * Copy interrupt vectors from ROM/flash to RAM: \n 216 * From: \code __ns_vector_table \endcode 217 * To: \code __ns_vector_table_rw \endcode 218 * The vector table address (and the vector table itself) are defined in the 219 * ns_start_<device>.c startup file corresponding to non-secure worlds. 220 * The code in these files copies the vector table from ROM/Flash to RAM. 221 * 222 * \section group_system_config_changelog_cm33 Changelog 223 * <table class="doxtable"> 224 * <tr> 225 * <th>Version</th> 226 * <th>Changes</th> 227 * <th>Reason for Change</th> 228 * </tr> 229 * <tr> 230 * <td>1.2</td> 231 * <td>Added new internal functions.</td> 232 * <td>Added support for DSRAM Setup for CAT1B devices.</td> 233 * </tr> 234 * <tr> 235 * <td>1.1</td> 236 * <td>Restructured documentation and internal function behaviour.</td> 237 * <td>User experience enhancement.</td> 238 * </tr> 239 * <tr> 240 * <td>1.0</td> 241 * <td>Initial version</td> 242 * <td></td> 243 * </tr> 244 * </table> 245 * 246 * 247 * \defgroup group_system_config_macro_cm33 Macros 248 * \{ 249 * \defgroup group_system_config_system_macro_cm33 System Macros 250 * \} 251 * 252 * \} 253 */ 254 255 256 #ifdef __cplusplus 257 extern "C" { 258 #endif 259 260 /******************************************************************************* 261 * Include files 262 *******************************************************************************/ 263 #include <stdint.h> 264 #include <stdbool.h> 265 266 #define CY_SYSTEM_CPU_CM33 1UL 267 268 /******************************************************************************* 269 * Global preprocessor symbols/macros ('define') 270 *******************************************************************************/ 271 272 /** 273 * \addtogroup group_system_config_system_macro_cm33 274 * \{ 275 */ 276 #if (CY_SYSTEM_CPU_CM33 == 1UL) || defined(CY_DOXYGEN) 277 /** The Cortex-M33 startup driver identifier */ 278 #define CY_STARTUP_M33_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) 279 #endif /* (CY_SYSTEM_CPU_CM33 == 1UL) */ 280 /** \} group_system_config_system_macro_cm33 */ 281 282 /** \cond */ 283 void SystemInit(void); 284 void SystemInit_Warmboot_CAT1B_CM33(void); 285 void System_Store_NVIC_Reg(void); 286 void System_Restore_NVIC_Reg(void); 287 extern void SystemCoreClockUpdate(void); 288 289 extern void Cy_SystemInit(void); 290 extern void bootstrapInit(void); 291 292 extern uint32_t cy_delayFreqHz; 293 extern uint32_t cy_delayFreqKhz; 294 extern uint8_t cy_delayFreqMhz; 295 296 extern uint32_t SystemCoreClock; 297 extern uint32_t cy_Hfclk0FreqHz; 298 extern uint32_t cy_PeriClkFreqHz; 299 extern uint32_t cy_AhbFreqHz; 300 extern bool cy_WakeupFromWarmBootStatus; 301 302 /** \endcond */ 303 304 305 #ifdef __cplusplus 306 } 307 #endif 308 309 #endif /* _SYSTEM_CAT1B_H_ */ 310 311 312 /* [] END OF FILE */ 313 314 315 316
