Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/bsp/platforms/PSVP-CYW20829\cycfg_clocks.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned short PCLK_CPUSS_CLOCK_TRACE_IN_POS_EN PCLK_SCB0_CLOCK_SCB_EN PCLK_SCB1_CLOCK_SCB_EN PCLK_SCB2_CLOCK_SCB_EN PCLK_TCPWM0_CLOCK_COUNTER_EN0 PCLK_TCPWM0_CLOCK_COUNTER_EN1 PCLK_TCPWM0_CLOCK_COUNTER_EN256 PCLK_TCPWM0_CLOCK_COUNTER_EN257 PCLK_TCPWM0_CLOCK_COUNTER_EN258 PCLK_TCPWM0_CLOCK_COUNTER_EN259 PCLK_TCPWM0_CLOCK_COUNTER_EN260 PCLK_TCPWM0_CLOCK_COUNTER_EN261 PCLK_TCPWM0_CLOCK_COUNTER_EN262 PCLK_LIN0_CLOCK_CH_EN0 PCLK_LIN0_CLOCK_CH_EN1 PCLK_CANFD0_CLOCK_CAN_EN0 PCLK_IOSS_CLOCK_SMARTIO_PCLK_POS_EN3 PCLK_SMIF_CLK_MEM PCLK_SMIF_CLK_FAST PCLK_SMIF_CLK_SLOW PCLK_BTSS_CLK_CPUSS_EXP PCLK_BTSS_CLK_PERI PCLK_CRYPTO_CLK_HF PCLK_PDM0_CLK_IF_SRSS PCLK_TDM0_CLK_IF_SRSS0 PCLK_ADCMIC_CLK_HF PCLK_SMIF_CLK_IF PCLK_IOSS_CLK_HF unsigned char CY_SYSCLK_DIV_8_BIT CY_SYSCLK_DIV_16_BIT CY_SYSCLK_DIV_16_5_BIT CY_SYSCLK_DIV_24_5_BIT unsigned int CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE en_clk_dst_t Cy_SysClk_PeriPclkEnableDivider cy_en_sysclk_status_t cy_en_divider_types_t uint32_t init_cycfg_clocks reserve_cycfg_clocks OUTLINED_FUNCTION_0 Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/bsp/platforms/PSVP-CYW20829\cycfg_system.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv srss_0_clock_0_fll_0_fllConfig fllMult unsigned int uint32_t refDiv unsigned short uint16_t ccoRange unsigned char CY_SYSCLK_FLL_CCO_RANGE0 CY_SYSCLK_FLL_CCO_RANGE1 CY_SYSCLK_FLL_CCO_RANGE2 CY_SYSCLK_FLL_CCO_RANGE3 CY_SYSCLK_FLL_CCO_RANGE4 cy_en_fll_cco_ranges_t enableOutputDiv _Bool lockTolerance igain uint8_t pgain settlingCount outputMode CY_SYSCLK_FLLPLL_OUTPUT_AUTO CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 CY_SYSCLK_FLLPLL_OUTPUT_INPUT CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT cy_en_fll_pll_output_mode_t cco_Freq cy_stc_fll_manual_config_t CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE CY_SYSCLK_CLKPATH_IN_IMO CY_SYSCLK_CLKPATH_IN_EXT CY_SYSCLK_CLKPATH_IN_ECO CY_SYSCLK_CLKPATH_IN_ALTHF CY_SYSCLK_CLKPATH_IN_DSIMUX CY_SYSCLK_CLKPATH_IN_LPECO CY_SYSCLK_CLKPATH_IN_IHO CY_SYSCLK_CLKPATH_IN_DSI CY_SYSCLK_CLKPATH_IN_ILO CY_SYSCLK_CLKPATH_IN_WCO CY_SYSCLK_CLKPATH_IN_ALTLF CY_SYSCLK_CLKPATH_IN_PILO CY_SYSCLK_CLKPATH_IN_ILO1 CY_SYSCLK_CLKHF_IN_CLKPATH0 CY_SYSCLK_CLKHF_IN_CLKPATH1 CY_SYSCLK_CLKHF_IN_CLKPATH2 CY_SYSCLK_CLKHF_IN_CLKPATH3 CY_SYSCLK_CLKHF_IN_CLKPATH4 CY_SYSCLK_CLKHF_IN_CLKPATH5 CY_SYSCLK_CLKHF_IN_CLKPATH6 CY_SYSCLK_CLKHF_IN_CLKPATH7 CY_SYSCLK_CLKHF_IN_CLKPATH8 CY_SYSCLK_CLKHF_IN_CLKPATH9 CY_SYSCLK_CLKHF_IN_CLKPATH10 CY_SYSCLK_CLKHF_IN_CLKPATH11 CY_SYSCLK_CLKHF_IN_CLKPATH12 CY_SYSCLK_CLKHF_IN_CLKPATH13 CY_SYSCLK_CLKHF_IN_CLKPATH14 CY_SYSCLK_CLKHF_IN_CLKPATH15 CY_SYSCLK_CLKHF_NO_DIVIDE CY_SYSCLK_CLKHF_DIVIDE_BY_2 CY_SYSCLK_CLKHF_DIVIDE_BY_4 CY_SYSCLK_CLKHF_DIVIDE_BY_8 Cy_SysClk_FllDeInit Cy_SysClk_IhoInit Cy_SysClk_ClkPath1Init Cy_SysClk_ClkPath2Init Cy_SysClk_ClkPath3Init Cy_SysClk_ClkHf1Init Cy_SysClk_ClkPath0Init Cy_SysClk_FllInit Cy_SysClk_ClkHf0Init SystemCoreClockUpdate cycfg_ClockStartupError init_cycfg_system reserve_cycfg_system error Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/bsp/platforms/PSVP-CYW20829\cycfg_pins.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv ioss_0_port_2_pin_0_config outVal unsigned int uint32_t driveMode hsiom unsigned char HSIOM_SEL_GPIO HSIOM_SEL_GPIO_DSI HSIOM_SEL_DSI_DSI HSIOM_SEL_DSI_GPIO HSIOM_SEL_AMUXA HSIOM_SEL_AMUXB HSIOM_SEL_AMUXA_DSI HSIOM_SEL_AMUXB_DSI HSIOM_SEL_ACT_0 HSIOM_SEL_ACT_1 HSIOM_SEL_ACT_2 HSIOM_SEL_ACT_3 HSIOM_SEL_DS_0 HSIOM_SEL_DS_1 HSIOM_SEL_DS_2 HSIOM_SEL_DS_3 HSIOM_SEL_ACT_4 HSIOM_SEL_ACT_5 HSIOM_SEL_ACT_6 HSIOM_SEL_ACT_7 HSIOM_SEL_ACT_8 HSIOM_SEL_ACT_9 HSIOM_SEL_ACT_10 HSIOM_SEL_ACT_11 HSIOM_SEL_ACT_12 HSIOM_SEL_ACT_13 HSIOM_SEL_ACT_14 HSIOM_SEL_ACT_15 HSIOM_SEL_DS_4 HSIOM_SEL_DS_5 HSIOM_SEL_DS_6 HSIOM_SEL_DS_7 P0_0_GPIO P0_0_TCPWM0_LINE_COMPL0 P0_0_TCPWM0_LINE_COMPL262 P0_0_KEYSCAN_KS_COL3 P0_0_PDM_PDM_CLK1 P0_0_TDM_TDM_RX_MCK0 P0_0_BTSS_DEBUG12 P0_0_SCB0_SPI_SELECT1 P0_1_GPIO P0_1_TCPWM0_LINE1 P0_1_TCPWM0_LINE256 P0_1_KEYSCAN_KS_COL4 P0_1_PDM_PDM_DATA1 P0_1_TDM_TDM_RX_SCK0 P0_1_BTSS_DEBUG13 P0_1_SCB0_SPI_SELECT2 P0_2_GPIO P0_2_TCPWM0_LINE_COMPL1 P0_2_TCPWM0_LINE_COMPL256 P0_2_KEYSCAN_KS_COL11 P0_2_SCB0_I2C_SCL P0_2_PERI_TR_IO_INPUT4 P0_2_TDM_TDM_RX_FSYNC0 P0_2_BTSS_DEBUG14 P0_2_SCB0_SPI_MOSI P0_3_GPIO P0_3_TCPWM0_LINE0 P0_3_TCPWM0_LINE257 P0_3_KEYSCAN_KS_COL12 P0_3_SCB0_I2C_SDA P0_3_SCB1_SPI_SELECT3 P0_3_PERI_TR_IO_INPUT5 P0_3_TDM_TDM_RX_SD0 P0_3_BTSS_DEBUG15 P0_3_SCB0_SPI_MISO P0_4_GPIO P0_4_TCPWM0_LINE_COMPL0 P0_4_TCPWM0_LINE_COMPL257 P0_4_BTSS_GPIO5 P0_4_BTSS_TXD_PYLD_MOD_TEST1 P0_4_KEYSCAN_KS_ROW0 P0_4_SRSS_EXT_CLK P0_4_CPUSS_TRACE_DATA3 P0_4_SCB1_SPI_SELECT2 P0_4_PERI_TR_IO_INPUT0 P0_4_TDM_TDM_TX_MCK0 P0_4_BTSS_DEBUG3 P0_4_BTSS_SPI_CLK P0_4_SCB0_SPI_CLK P0_4_IOSS_DDFT_PIN1 P0_5_GPIO P0_5_TCPWM0_LINE1 P0_5_TCPWM0_LINE258 P0_5_BTSS_ANTENNA_SWITCH_CTRL0 P0_5_BTSS_TX_ST_TEST P0_5_KEYSCAN_KS_ROW1 P0_5_CPUSS_TRACE_DATA2 P0_5_SCB1_SPI_SELECT1 P0_5_PERI_TR_IO_INPUT1 P0_5_TDM_TDM_TX_SCK0 P0_5_BTSS_GCI_GPIO0 P0_5_BTSS_DEBUG4 P0_5_SMIF_SPIHB_SELECT1 P1_0_GPIO P1_0_TCPWM0_LINE_COMPL1 P1_0_TCPWM0_LINE_COMPL258 P1_0_BTSS_ANTENNA_SWITCH_CTRL1 P1_0_BTSS_RPU_TDO P1_0_KEYSCAN_KS_ROW5 P1_0_CPUSS_TRACE_DATA1 P1_0_SCB1_UART_CTS P1_0_SCB1_SPI_SELECT0 P1_0_PERI_TR_IO_OUTPUT0 P1_0_TDM_TDM_TX_FSYNC0 P1_0_BTSS_GCI_GPIO1 P1_0_BTSS_DEBUG5 P1_0_CPUSS_SWJ_SWO_TDO P1_1_GPIO P1_1_TCPWM0_LINE0 P1_1_TCPWM0_LINE259 P1_1_BTSS_ANTENNA_SWITCH_CTRL2 P1_1_BTSS_RPU_TDI P1_1_KEYSCAN_KS_ROW6 P1_1_CPUSS_TRACE_DATA0 P1_1_SCB1_UART_RTS P1_1_SCB1_SPI_CLK P1_1_PERI_TR_IO_OUTPUT1 P1_1_TDM_TDM_TX_SD0 P1_1_BTSS_GCI_GPIO2 P1_1_BTSS_DEBUG6 P1_1_BTSS_UART_TXD P1_1_CPUSS_SWJ_SWDOE_TDI P1_1_IOSS_DDFT_PIN0 P1_2_GPIO P1_2_TCPWM0_LINE_COMPL0 P1_2_TCPWM0_LINE_COMPL259 P1_2_BTSS_GPIO0 P1_2_BTSS_RPU_SWD P1_2_KEYSCAN_KS_COL17 P1_2_CPUSS_TRACE_CLOCK P1_2_SCB1_UART_RX P1_2_SCB2_I2C_SCL P1_2_SCB1_SPI_MOSI P1_2_PERI_TR_IO_INPUT2 P1_2_BTSS_GCI_GPIO3 P1_2_BTSS_DEBUG7 P1_2_BTSS_SPI_MOSI P1_2_CPUSS_SWJ_SWDIO_TMS P1_3_GPIO P1_3_TCPWM0_LINE1 P1_3_TCPWM0_LINE260 P1_3_BTSS_GPIO1 P1_3_BTSS_RPU_TCK P1_3_KEYSCAN_KS_COL16 P1_3_SRSS_EXT_CLK P1_3_SCB1_UART_TX P1_3_SCB2_I2C_SDA P1_3_SCB1_SPI_MISO P1_3_PERI_TR_IO_INPUT3 P1_3_BTSS_GCI_GPIO4 P1_3_BTSS_DEBUG8 P1_3_BTSS_SPI_CLK P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK P1_4_GPIO P1_4_TCPWM0_LINE_COMPL1 P1_4_TCPWM0_LINE_COMPL260 P1_4_BTSS_GPIO5 P1_4_KEYSCAN_KS_COL15 P1_4_KEYSCAN_KS_COL16 P1_4_LIN0_LIN_EN1 P1_4_BTSS_GCI_GPIO2 P1_4_BTSS_DEBUG9 P1_5_GPIO P1_5_TCPWM0_LINE0 P1_5_TCPWM0_LINE261 P1_5_BTSS_GPIO6 P1_5_KEYSCAN_KS_COL5 P1_5_LIN0_LIN_RX1 P1_5_BTSS_DEBUG10 P1_6_GPIO P1_6_TCPWM0_LINE_COMPL0 P1_6_TCPWM0_LINE_COMPL261 P1_6_BTSS_GPIO7 P1_6_KEYSCAN_KS_COL6 P1_6_SRSS_CAL_WAVE P1_6_LIN0_LIN_TX1 P1_6_BTSS_DEBUG11 P2_0_GPIO P2_0_SMIF_SPIHB_SELECT0 P2_1_GPIO P2_1_SMIF_SPIHB_DATA3 P2_2_GPIO P2_2_SMIF_SPIHB_DATA2 P2_3_GPIO P2_3_SMIF_SPIHB_DATA1 P2_4_GPIO P2_4_SMIF_SPIHB_DATA0 P2_5_GPIO P2_5_SMIF_SPIHB_CLK P3_0_GPIO P3_0_TCPWM0_LINE0 P3_0_TCPWM0_LINE256 P3_0_KEYSCAN_KS_ROW7 P3_0_CPUSS_TRACE_DATA3 P3_0_SCB2_UART_CTS P3_0_SCB1_SPI_SELECT0 P3_0_BTSS_UART_CTS P3_1_GPIO P3_1_TCPWM0_LINE_COMPL0 P3_1_TCPWM0_LINE_COMPL256 P3_1_BTSS_RPU_NTRST P3_1_KEYSCAN_KS_ROW4 P3_1_CPUSS_TRACE_DATA2 P3_1_SCB2_UART_RTS P3_1_SCB1_SPI_CLK P3_1_LIN0_LIN_EN0 P3_1_BTSS_UART_RTS P3_1_BTSS_SYSCLK_RF P3_1_CPUSS_RST_SWJ_TRSTN P3_2_GPIO P3_2_TCPWM0_LINE1 P3_2_TCPWM0_LINE257 P3_2_BTSS_TXD_SYMB_DATA_TEST0 P3_2_KEYSCAN_KS_COL13 P3_2_CPUSS_TRACE_DATA1 P3_2_SCB2_UART_RX P3_2_SCB2_I2C_SCL P3_2_SCB1_SPI_MOSI P3_2_PDM_PDM_CLK0 P3_2_PERI_TR_IO_INPUT6 P3_2_LIN0_LIN_RX0 P3_2_CANFD0_TTCAN_RX0 P3_2_ADCMIC_CLK_PDM P3_2_BTSS_UART_RXD P3_2_IOSS_DDFT_PIN1 P3_3_GPIO P3_3_TCPWM0_LINE_COMPL1 P3_3_TCPWM0_LINE_COMPL257 P3_3_BTSS_TXD_SYMB_DATA_TEST1 P3_3_KEYSCAN_KS_COL14 P3_3_KEYSCAN_KS_COL17 P3_3_CPUSS_TRACE_DATA0 P3_3_SCB2_UART_TX P3_3_SCB2_I2C_SDA P3_3_SCB1_SPI_MISO P3_3_PDM_PDM_DATA0 P3_3_PERI_TR_IO_INPUT7 P3_3_LIN0_LIN_TX0 P3_3_CANFD0_TTCAN_TX0 P3_3_ADCMIC_PDM_DATA P3_3_BTSS_UART_TXD P3_3_IOSS_DDFT_PIN0 P3_4_GPIO P3_4_TCPWM0_LINE0 P3_4_TCPWM0_LINE258 P3_4_BTSS_GPIO0 P3_4_KEYSCAN_KS_COL7 P3_4_CPUSS_TRACE_CLOCK P3_4_SCB1_SPI_SELECT3 P3_4_BTSS_DEBUG3 P3_5_GPIO P3_5_TCPWM0_LINE_COMPL0 P3_5_TCPWM0_LINE_COMPL258 P3_5_BTSS_GPIO1 P3_5_KEYSCAN_KS_COL8 P3_5_SCB1_SPI_SELECT2 P3_5_BTSS_DEBUG1 P3_6_GPIO P3_6_TCPWM0_LINE1 P3_6_TCPWM0_LINE259 P3_6_KEYSCAN_KS_COL9 P3_6_SCB1_SPI_SELECT1 P3_6_BTSS_DEBUG2 P3_7_GPIO P3_7_TCPWM0_LINE_COMPL1 P3_7_TCPWM0_LINE_COMPL259 P3_7_BTSS_ANTENNA_SWITCH_CTRL3 P3_7_KEYSCAN_KS_COL10 P3_7_BTSS_DEBUG7 P4_0_GPIO P4_0_TCPWM0_LINE_COMPL1 P4_0_TCPWM0_LINE_COMPL261 P4_0_BTSS_GPIO2 P4_0_BTSS_TXD_SYMB_STRB_TEST P4_0_KEYSCAN_KS_ROW2 P4_0_SCB0_I2C_SCL P4_0_SCB2_UART_CTS P4_0_BTSS_DEBUG1 P4_0_BTSS_UART_TXD P4_0_SCB0_SPI_MOSI P4_1_GPIO P4_1_TCPWM0_LINE0 P4_1_TCPWM0_LINE262 P4_1_BTSS_GPIO4 P4_1_BTSS_TXD_PYLD_MOD_TEST0 P4_1_KEYSCAN_KS_ROW3 P4_1_SCB0_I2C_SDA P4_1_BTSS_DEBUG2 P4_1_BTSS_SPI_MOSI P4_1_SCB0_SPI_MISO P5_0_GPIO P5_0_TCPWM0_LINE0 P5_0_TCPWM0_LINE260 P5_0_BTSS_TXD_SYMB_DATA_TEST2 P5_0_KEYSCAN_KS_COL0 P5_0_SCB2_UART_CTS P5_0_SCB1_SPI_SELECT0 P5_0_PDM_PDM_CLK0 P5_0_ADCMIC_CLK_PDM P5_0_BTSS_UART_CTS P5_1_GPIO P5_1_TCPWM0_LINE_COMPL0 P5_1_TCPWM0_LINE_COMPL260 P5_1_BTSS_GPIO3 P5_1_BTSS_TXD_SYMB_DATA_TEST3 P5_1_KEYSCAN_KS_COL1 P5_1_PDM_PDM_DATA0 P5_1_ADCMIC_PDM_DATA P5_1_BTSS_DEBUG0 P5_1_BTSS_UART_RXD P5_1_SCB0_SPI_SELECT0 P5_2_GPIO P5_2_TCPWM0_LINE1 P5_2_TCPWM0_LINE261 P5_2_BTSS_GPIO4 P5_2_KEYSCAN_KS_COL2 P5_2_BTSS_DEBUG8 en_hsiom_sel_t intEdge intMask vtrip slewRate driveSel vregEn ibufMode vtripSel vrefSel vohSel nonSec cy_stc_gpio_pin_config_t ioss_0_port_2_pin_1_config ioss_0_port_2_pin_2_config ioss_0_port_2_pin_3_config ioss_0_port_2_pin_4_config ioss_0_port_2_pin_5_config CY_GPIO_SUCCESS CY_GPIO_BAD_PARAM OUT OUT_CLR OUT_SET OUT_INV IN INTR INTR_MASK INTR_MASKED INTR_SET RESERVED __ARRAY_SIZE_TYPE__ INTR_CFG CFG CFG_IN CFG_OUT CFG_SIO RESERVED1 CFG_IN_AUTOLVL RESERVED2 CFG_OUT2 CFG_SLEW_EXT CFG_DRIVE_EXT0 CFG_DRIVE_EXT1 RESERVED3 GPIO_PRT_Type PRT SEC_INTR_CAUSE0 SEC_INTR_CAUSE1 SEC_INTR_CAUSE2 SEC_INTR_CAUSE3 INTR_CAUSE0 INTR_CAUSE1 INTR_CAUSE2 INTR_CAUSE3 VDD_ACTIVE VDD_INTR VDD_INTR_MASK VDD_INTR_MASKED VDD_INTR_SET VDD_PWRSW_STATUS VDD_PWRSW_CTL GPIO_Type init_cycfg_pins reserve_cycfg_pins Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/bsp/platforms/PSVP-CYW20829\cycfg_peripherals.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv SMIF_config mode unsigned int uint32_t deselectDelay rxClockSel blockEvent cy_stc_smif_config_t reserve_cycfg_peripherals Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/bsp/platforms/PSVP-CYW20829\cycfg.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv init_cycfg_pins reserve_cycfg_pins init_cycfg_all cycfg_config_init cycfg_config_reservations Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_syspm_btss.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv cy_btss_lock_count unsigned int uint32_t cy_cpuss_lock_count CY_BTSS_SUCCESS CY_BTSS_BAD_PARAM CY_BTSS_TIMEOUT CY_BTSS_INVALID_STATE unsigned char CY_PD_PDCM_MAIN CY_PD_PDCM_CPUSS CY_PD_PDCM_SRAM CY_PD_PDCM_BTSS CY_SYSPM_SUCCESS CY_SYSPM_BAD_PARAM CY_SYSPM_TIMEOUT CY_SYSPM_INVALID_STATE CY_SYSPM_CANCELED CY_SYSPM_SYSCALL_PENDING CY_SYSPM_FAIL CY_SYSCLK_PERI_GROUP_SL_CTL CY_SYSCLK_PERI_GROUP_SL_CTL2 CY_SYSCLK_PERI_GROUP_SL_CTL3 Cy_BTSS_GetXtalOscFreq Cy_BTSS_PowerDep cy_en_btss_status_t Cy_BTSS_CPUSSPowerDep enable _Bool timeoutus retVal interruptState Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_efuse_v3.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned int CY_EFUSE_SUCCESS CY_EFUSE_INVALID_PROTECTION CY_EFUSE_INVALID_FUSE_ADDR CY_EFUSE_BAD_PARAM CY_EFUSE_IPC_BUSY CY_EFUSE_WRITE_BUSY CY_EFUSE_WRITE_ERROR CY_EFUSE_WRITE_TIMEOUT_ERROR CY_EFUSE_ERR_UNC CTL uint32_t RESERVED __ARRAY_SIZE_TYPE__ TEST RESERVED1 CMD CONFIG RESERVED2 SEQ_DEFAULT RESERVED3 SEQ_READ_CTL_0 SEQ_READ_CTL_1 SEQ_READ_CTL_2 SEQ_READ_CTL_3 SEQ_READ_CTL_4 SEQ_READ_CTL_5 SEQ_READ_CTL_6 SEQ_READ_CTL_7 SEQ_PROGRAM_CTL_0 SEQ_PROGRAM_CTL_1 SEQ_PROGRAM_CTL_2 SEQ_PROGRAM_CTL_3 SEQ_PROGRAM_CTL_4 SEQ_PROGRAM_CTL_5 SEQ_PROGRAM_CTL_6 SEQ_PROGRAM_CTL_7 BOOTROW EFUSE_Type unsigned char uint8_t Cy_EFUSE_Disable base Cy_EFUSE_Enable Cy_EFUSE_ReadByte cy_en_efuse_status_t dst offset ret byteNum word Cy_EFUSE_ReadWord Cy_EFUSE_IsEnabled _Bool Cy_EFUSE_Init Cy_EFUSE_DeInit Cy_EFUSE_WriteBit Cy_EFUSE_WriteByte Cy_EFUSE_WriteWord Cy_EFUSE_WriteWordArray Cy_EFUSE_ReadBit Cy_EFUSE_ReadWordArray Cy_EFUSE_WriteBootRow Cy_EFUSE_ReadBootRow bitPos timeout byteAddr macroAddr readByte src readWord val num byte bootrow Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_pd_pdcm.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned char CY_PD_PDCM_DEP_NONE CY_PD_PDCM_DEP_DIRECT CY_PD_PDCM_DEP_CONFIG CY_PD_PDCM_MAIN CY_PD_PDCM_CPUSS CY_PD_PDCM_SRAM CY_PD_PDCM_BTSS CY_PD_PDCM_SUCCESS CY_PD_PDCM_BAD_PARAM CY_PD_PDCM_TIMEOUT CY_PD_PDCM_INVALID_STATE CY_PD_PDCM_ERROR unsigned int uint32_t PD_SENSE PD_SPT RESERVED __ARRAY_SIZE_TYPE__ PWRMODE_PD_Type PD PPU_MAIN PWPR PMER PWSR DISR MISR STSR UNLK PWCR PTCR RESERVED1 IMR AIMR ISR AISR IESR OPSR RESERVED2 FUNRR FULRR MEMRR RESERVED3 EDTR0 EDTR1 RESERVED4 DCDR0 DCDR1 RESERVED5 IDR0 IDR1 RESERVED6 IIDR AIDR RESERVED7 PWRMODE_PPU_MAIN_PPU_MAIN_Type PWRMODE_PPU_MAIN_Type CLK_SELECT PWRMODE_Type cy_pd_pdcm_dep_t cy_pd_pdcm_get_dependency cy_pd_pdcm_set_dependency cy_pd_pdcm_status_t cy_pd_pdcm_clear_dependency host_pd cy_pd_pdcm_id_t dest_pd dep ret Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/non-secure\ns_system_cyw20829.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv SystemCoreClock unsigned int uint32_t cy_Hfclk0FreqHz cy_PeriClkFreqHz cy_delayFreqHz cy_delayFreqKhz cy_delayFreqMhz unsigned char uint8_t cy_delay32kMs CY_SYSCLK_PERI_GROUP_SL_CTL CY_SYSCLK_PERI_GROUP_SL_CTL2 CY_SYSCLK_PERI_GROUP_SL_CTL3 CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE SystemInit Cy_SystemInit SystemCoreClockUpdate OUTLINED_FUNCTION_0 clkHfPath pathFreqHz Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_sysclk_v2.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv clk1Count1 unsigned int uint32_t cySysClkExtFreq clkCounting _Bool preventCounting CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE unsigned short PCLK_CPUSS_CLOCK_TRACE_IN_POS_EN PCLK_SCB0_CLOCK_SCB_EN PCLK_SCB1_CLOCK_SCB_EN PCLK_SCB2_CLOCK_SCB_EN PCLK_TCPWM0_CLOCK_COUNTER_EN0 PCLK_TCPWM0_CLOCK_COUNTER_EN1 PCLK_TCPWM0_CLOCK_COUNTER_EN256 PCLK_TCPWM0_CLOCK_COUNTER_EN257 PCLK_TCPWM0_CLOCK_COUNTER_EN258 PCLK_TCPWM0_CLOCK_COUNTER_EN259 PCLK_TCPWM0_CLOCK_COUNTER_EN260 PCLK_TCPWM0_CLOCK_COUNTER_EN261 PCLK_TCPWM0_CLOCK_COUNTER_EN262 PCLK_LIN0_CLOCK_CH_EN0 PCLK_LIN0_CLOCK_CH_EN1 PCLK_CANFD0_CLOCK_CAN_EN0 PCLK_IOSS_CLOCK_SMARTIO_PCLK_POS_EN3 PCLK_SMIF_CLK_MEM PCLK_SMIF_CLK_FAST PCLK_SMIF_CLK_SLOW PCLK_BTSS_CLK_CPUSS_EXP PCLK_BTSS_CLK_PERI PCLK_CRYPTO_CLK_HF PCLK_PDM0_CLK_IF_SRSS PCLK_TDM0_CLK_IF_SRSS0 PCLK_ADCMIC_CLK_HF PCLK_SMIF_CLK_IF PCLK_IOSS_CLK_HF unsigned char CY_SYSCLK_DIV_8_BIT CY_SYSCLK_DIV_16_BIT CY_SYSCLK_DIV_16_5_BIT CY_SYSCLK_DIV_24_5_BIT CY_SYSCLK_PUMP_IN_CLKPATH0 CY_SYSCLK_PUMP_IN_CLKPATH1 CY_SYSCLK_PUMP_IN_CLKPATH2 CY_SYSCLK_PUMP_IN_CLKPATH3 CY_SYSCLK_PUMP_IN_CLKPATH4 CY_SYSCLK_PUMP_IN_CLKPATH5 CY_SYSCLK_PUMP_IN_CLKPATH6 CY_SYSCLK_PUMP_IN_CLKPATH7 CY_SYSCLK_PUMP_IN_CLKPATH8 CY_SYSCLK_PUMP_IN_CLKPATH9 CY_SYSCLK_PUMP_IN_CLKPATH10 CY_SYSCLK_PUMP_IN_CLKPATH11 CY_SYSCLK_PUMP_IN_CLKPATH12 CY_SYSCLK_PUMP_IN_CLKPATH13 CY_SYSCLK_PUMP_IN_CLKPATH14 CY_SYSCLK_PUMP_IN_CLKPATH15 CY_SYSCLK_PUMP_NO_DIV CY_SYSCLK_PUMP_DIV_2 CY_SYSCLK_PUMP_DIV_4 CY_SYSCLK_PUMP_DIV_8 CY_SYSCLK_PUMP_DIV_16 CY_SYSCLK_BAK_IN_WCO CY_SYSCLK_BAK_IN_CLKLF CY_SYSCLK_BAK_IN_ILO CY_SYSCLK_BAK_IN_LPECO_PRESCALER CY_SYSCLK_BAK_IN_PILO CY_SYSCLK_CLKLF_IN_ILO CY_SYSCLK_CLKLF_IN_WCO CY_SYSCLK_CLKLF_IN_ALTLF CY_SYSCLK_CLKLF_IN_PILO CY_SYSCLK_CLKLF_IN_ILO1 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER CY_SYSCLK_CLKLF_IN_MAX CY_SYSCLK_PERI_GROUP_SL_CTL CY_SYSCLK_PERI_GROUP_SL_CTL2 CY_SYSCLK_PERI_GROUP_SL_CTL3 CY_SYSCLK_CLKHF_IN_CLKPATH0 CY_SYSCLK_CLKHF_IN_CLKPATH1 CY_SYSCLK_CLKHF_IN_CLKPATH2 CY_SYSCLK_CLKHF_IN_CLKPATH3 CY_SYSCLK_CLKHF_IN_CLKPATH4 CY_SYSCLK_CLKHF_IN_CLKPATH5 CY_SYSCLK_CLKHF_IN_CLKPATH6 CY_SYSCLK_CLKHF_IN_CLKPATH7 CY_SYSCLK_CLKHF_IN_CLKPATH8 CY_SYSCLK_CLKHF_IN_CLKPATH9 CY_SYSCLK_CLKHF_IN_CLKPATH10 CY_SYSCLK_CLKHF_IN_CLKPATH11 CY_SYSCLK_CLKHF_IN_CLKPATH12 CY_SYSCLK_CLKHF_IN_CLKPATH13 CY_SYSCLK_CLKHF_IN_CLKPATH14 CY_SYSCLK_CLKHF_IN_CLKPATH15 CY_SYSCLK_CLKHF_NO_DIVIDE CY_SYSCLK_CLKHF_DIVIDE_BY_2 CY_SYSCLK_CLKHF_DIVIDE_BY_4 CY_SYSCLK_CLKHF_DIVIDE_BY_8 CY_SYSCLK_CLKMF_IN_MFO CY_SYSCLK_CLKMF_IN_ILO CY_SYSCLK_CLKMF_IN_WCO CY_SYSCLK_CLKMF_IN_ALTLF CY_SYSCLK_CLKMF_IN_PILO CY_SYSCLK_CLKMF_IN_ILO1 CY_SYSCLK_CLKMF_IN_ECO_PRESCALER CY_SYSCLK_CLKMF_IN_LPECO CY_SYSCLK_WCO_NOT_BYPASSED CY_SYSCLK_WCO_BYPASSED CY_SYSCLK_CLKPATH_IN_IMO CY_SYSCLK_CLKPATH_IN_EXT CY_SYSCLK_CLKPATH_IN_ECO CY_SYSCLK_CLKPATH_IN_ALTHF CY_SYSCLK_CLKPATH_IN_DSIMUX CY_SYSCLK_CLKPATH_IN_LPECO CY_SYSCLK_CLKPATH_IN_IHO CY_SYSCLK_CLKPATH_IN_DSI CY_SYSCLK_CLKPATH_IN_ILO CY_SYSCLK_CLKPATH_IN_WCO CY_SYSCLK_CLKPATH_IN_ALTLF CY_SYSCLK_CLKPATH_IN_PILO CY_SYSCLK_CLKPATH_IN_ILO1 CY_SYSCLK_FLL_CCO_RANGE0 CY_SYSCLK_FLL_CCO_RANGE1 CY_SYSCLK_FLL_CCO_RANGE2 CY_SYSCLK_FLL_CCO_RANGE3 CY_SYSCLK_FLL_CCO_RANGE4 CY_SYSCLK_FLLPLL_OUTPUT_AUTO CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 CY_SYSCLK_FLLPLL_OUTPUT_INPUT CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT CY_SYSCLK_MEAS_CLK_NC CY_SYSCLK_MEAS_CLK_ILO CY_SYSCLK_MEAS_CLK_WCO CY_SYSCLK_MEAS_CLK_BAK CY_SYSCLK_MEAS_CLK_ALTLF CY_SYSCLK_MEAS_CLK_LFCLK CY_SYSCLK_MEAS_CLK_IMO CY_SYSCLK_MEAS_CLK_SLPCTRL CY_SYSCLK_MEAS_CLK_PILO CY_SYSCLK_MEAS_CLK_ILO1 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER CY_SYSCLK_MEAS_CLK_LPECO CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER CY_SYSCLK_MEAS_CLK_MFO CY_SYSCLK_MEAS_CLK_FAST_CLKS CY_SYSCLK_MEAS_CLK_ECO CY_SYSCLK_MEAS_CLK_EXT CY_SYSCLK_MEAS_CLK_ALTHF CY_SYSCLK_MEAS_CLK_TIMERCLK CY_SYSCLK_MEAS_CLK_IHO CY_SYSCLK_MEAS_CLK_PWR CY_SYSCLK_MEAS_CLK_PATH_CLKS CY_SYSCLK_MEAS_CLK_PATH0 CY_SYSCLK_MEAS_CLK_PATH1 CY_SYSCLK_MEAS_CLK_PATH2 CY_SYSCLK_MEAS_CLK_PATH3 CY_SYSCLK_MEAS_CLK_PATH4 CY_SYSCLK_MEAS_CLK_PATH5 CY_SYSCLK_MEAS_CLK_PATH6 CY_SYSCLK_MEAS_CLK_PATH7 CY_SYSCLK_MEAS_CLK_PATH8 CY_SYSCLK_MEAS_CLK_PATH9 CY_SYSCLK_MEAS_CLK_PATH10 CY_SYSCLK_MEAS_CLK_PATH11 CY_SYSCLK_MEAS_CLK_PATH12 CY_SYSCLK_MEAS_CLK_PATH13 CY_SYSCLK_MEAS_CLK_PATH14 CY_SYSCLK_MEAS_CLK_PATH15 CY_SYSCLK_MEAS_CLK_CLKHFS CY_SYSCLK_MEAS_CLK_CLKHF0 CY_SYSCLK_MEAS_CLK_CLKHF1 CY_SYSCLK_MEAS_CLK_CLKHF2 CY_SYSCLK_MEAS_CLK_CLKHF3 CY_SYSCLK_MEAS_CLK_CLKHF4 CY_SYSCLK_MEAS_CLK_CLKHF5 CY_SYSCLK_MEAS_CLK_CLKHF6 CY_SYSCLK_MEAS_CLK_CLKHF7 CY_SYSCLK_MEAS_CLK_CLKHF8 CY_SYSCLK_MEAS_CLK_CLKHF9 CY_SYSCLK_MEAS_CLK_CLKHF10 CY_SYSCLK_MEAS_CLK_CLKHF11 CY_SYSCLK_MEAS_CLK_CLKHF12 CY_SYSCLK_MEAS_CLK_CLKHF13 CY_SYSCLK_MEAS_CLK_CLKHF14 CY_SYSCLK_MEAS_CLK_CLKHF15 CY_SYSCLK_MEAS_CLK_LAST_CLK CY_SYSPM_SUCCESS CY_SYSPM_BAD_PARAM CY_SYSPM_TIMEOUT CY_SYSPM_INVALID_STATE CY_SYSPM_CANCELED CY_SYSPM_SYSCALL_PENDING CY_SYSPM_FAIL CY_SYSPM_CHECK_READY CY_SYSPM_CHECK_FAIL CY_SYSPM_BEFORE_TRANSITION CY_SYSPM_AFTER_TRANSITION CY_SYSPM_AFTER_DS_WFI_TRANSITION uint8_t DIV_CMD RESERVED __ARRAY_SIZE_TYPE__ CLOCK_CTL DIV_8_CTL DIV_16_CTL DIV_16_5_CTL DIV_24_5_CTL RESERVED1 PERI_PCLK_GR_Type GR PERI_PCLK_Type en_clk_dst_t PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 RESERVED2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED RESERVED3 SRSS_AINTR SRSS_AINTR_SET SRSS_AINTR_MASK SRSS_AINTR_MASKED RESERVED4 TST_DEBUG_CTL TST_DEBUG_STATUS RESERVED5 RES_SOFT_CTL RESERVED6 PWR_HIB_DATA RESERVED7 PWR_HIB_WAKE_CTL PWR_HIB_WAKE_CTL2 RESERVED8 PWR_HIB_WAKE_CAUSE RESERVED9 PWR_CTL PWR_CTL2 PWR_HIBERNATE RESERVED10 PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 RESERVED11 PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 RESERVED12 PWR_PMIC_CTL4 RESERVED13 CLK_PATH_SELECT CLK_ROOT_SELECT CLK_DIRECT_SELECT RESERVED14 CSV_HF CSV REF_CTL REF_LIMIT MON_CTL CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT RESERVED15 CLK_ILO0_CONFIG CLK_ILO1_CONFIG RESERVED16 CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG RESERVED17 CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 CLK_ILO_CONFIG CLK_TRIM_ILO_CTL CLK_TRIM_ILO0_CTL CLK_MF_SELECT CLK_MFO_CONFIG RESERVED18 CLK_IHO_CONFIG CLK_ALTHF_CTL RESERVED19 CLK_PLL_CONFIG RESERVED20 CLK_PLL_STATUS RESERVED21 CSV_REF_SEL RESERVED22 CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RESERVED23 RES_CAUSE RES_CAUSE2 RES_CAUSE_EXTEND RESERVED24 RES_PXRES_CTL RESERVED25 CLK_PLL400M CONFIG CONFIG2 CONFIG3 STATUS CLK_PLL400M_Type RESERVED26 PWR_CBUCK_CTL PWR_CBUCK_CTL2 PWR_CBUCK_CTL3 PWR_CBUCK_STATUS PWR_SDR0_CTL PWR_SDR1_CTL RESERVED27 PWR_HVLDO0_CTL RESERVED28 TST_XRES_SECURE RESERVED29 PWR_TRIM_CBUCK_CTL RESERVED30 CLK_TRIM_ECO_CTL RESERVED31 CLK_TRIM_ILO1_CTL RESERVED32 WDT_CTL WDT_CNT WDT_MATCH WDT_MATCH2 RESERVED33 MCWDT_STRUCT MCWDT_CNTLOW MCWDT_CNTHIGH MCWDT_MATCH MCWDT_CONFIG MCWDT_CTL MCWDT_INTR MCWDT_INTR_SET MCWDT_INTR_MASK MCWDT_INTR_MASKED MCWDT_LOCK MCWDT_LOWER_LIMIT MCWDT_STRUCT_Type SRSS_Type cy_en_clkpump_in_sources_t cy_en_clkpump_divide_t CTL RTC_RW CAL_CTL RTC_TIME RTC_DATE ALM1_TIME ALM1_DATE ALM2_TIME ALM2_DATE INTR INTR_SET INTR_MASK INTR_MASKED PMIC_CTL RESET LPECO_CTL LPECO_PRESCALE LPECO_STATUS WCO_STATUS CSV_BAK BACKUP_CSV_BAK_CSV_Type BACKUP_CSV_BAK_Type BREG_SET0 BREG_SET1 BREG_SET2 BREG_SET3 BACKUP_Type cy_en_clkbak_in_sources_t cy_en_clklf_in_sources_t SL_CTL SL_CTL2 SL_CTL3 PERI_GR_Type TIMEOUT_CTL AHB_ERROR_STATUS1 AHB_ERROR_STATUS2 AHB_ERROR_STATUS3 INTR_AHB_ERROR INTR_AHB_ERROR_SET INTR_AHB_ERROR_MASK INTR_AHB_ERROR_MASKED TR_CMD INFRA_CLK_FORCE TR_GR TR_CTL PERI_TR_GR_Type TR_1TO1_GR PERI_TR_1TO1_GR_Type PERI_Type cy_en_clkhf_in_sources_t cy_en_clkhf_dividers_t cy_en_clkmf_in_sources_t cy_en_clkpath_in_sources_t unsigned long long uint64_t uint16_t cy_en_fll_pll_output_mode_t cy_en_fll_cco_ranges_t int int32_t Cy_SysClk_PeriPclkGetDivider ipBlock dividerType cy_en_divider_types_t dividerNum instNum grpNum retVal Cy_SysClk_PeriPclkGetAssignedDivider periNum Cy_SysClk_ClkPumpIsEnabled Cy_SysClk_ClkPumpGetSource Cy_SysClk_ClkPumpGetDivider Cy_SysClk_FllIsEnabled Cy_SysClk_ClkHfGetDivider clkHf Cy_SysClk_ClkHfGetSource Cy_SysClk_IsClkHfDirectSelEnabled Cy_SysClk_ClkMfIsEnabled Cy_SysClk_MfoIsEnabled Cy_SysClk_ClkMfGetDivider Cy_SysClk_WcoOkay Cy_BTSS_GetXtalOscFreq Cy_SysClk_IsAltHfEnabled Cy_SysClk_ClkPathGetSource clkPath Cy_SysClk_ExtClkGetFrequency Cy_SysClk_AltHfGetFrequency Cy_SysClk_IhoIsEnabled Cy_SysClk_IloGetTrim Cy_SysClk_IloSetTrim trimVal Cy_SysClk_PeriPclkSetDivider cy_en_sysclk_status_t Cy_SysClk_PeriPclkSetFracDivider Cy_SysClk_PeriPclkGetFracDivider Cy_SysClk_PeriPclkAssignDivider Cy_SysClk_PeriPclkEnableDivider Cy_SysClk_PeriPclkDisableDivider Cy_SysClk_PeriPclkEnablePhaseAlignDivider Cy_SysClk_PeriphDisableDivider Cy_SysClk_PeriPclkGetDividerEnabled Cy_SysClk_PeriphSetDivider Cy_SysClk_PeriphGetDivider Cy_SysClk_PeriphSetFracDivider Cy_SysClk_PeriphGetFracDivider Cy_SysClk_PeriphAssignDivider Cy_SysClk_PeriphGetAssignedDivider Cy_SysClk_PeriphEnableDivider Cy_SysClk_PeriphEnablePhaseAlignDivider Cy_SysClk_PeriphGetDividerEnabled Cy_SysClk_ClkPumpSetSource Cy_SysClk_ClkPumpSetDivider Cy_SysClk_ClkPumpEnable Cy_SysClk_ClkPumpDisable Cy_SysClk_ClkPumpGetFrequency Cy_SysClk_ClkPathGetFrequency Cy_SysClk_ClkBakSetSource Cy_SysClk_ClkBakGetSource Cy_SysClk_ClkLfSetSource Cy_SysClk_ClkLfGetSource Cy_SysClk_PeriGroupSetDivider Cy_SysClk_PeriGroupGetDivider Cy_SysClk_PeriGroupSetSlaveCtl Cy_SysClk_PeriGroupGetSlaveCtl Cy_SysClk_IsPeriGroupSlaveCtlSet Cy_SysClk_ClkHfEnable Cy_SysClk_ClkHfGetFrequency Cy_SysClk_ClkHfIsEnabled Cy_SysClk_ClkHfDisable Cy_SysClk_ClkHfSetSource Cy_SysClk_ClkHfSetDivider Cy_SysClk_ClkHfDirectSel Cy_SysClk_MfoEnable Cy_SysClk_MfoDisable Cy_SysClk_ClkMfEnable Cy_SysClk_ClkMfDisable Cy_SysClk_ClkMfSetDivider Cy_SysClk_ClkMfGetFrequency Cy_SysClk_ClkMfSetSource Cy_SysClk_ClkMfGetSource Cy_SysClk_WcoEnable Cy_SysClk_WcoDisable Cy_SysClk_WcoBypass Cy_SysClk_PiloEnable Cy_SysClk_PiloBackupEnable Cy_SysClk_PiloBackupDisable Cy_SysClk_PiloTcscEnable Cy_SysClk_PiloTcscDisable Cy_SysClk_PiloIsEnabled Cy_SysClk_PiloDisable Cy_SysClk_AltHfEnable Cy_SysClk_AltLfGetFrequency Cy_SysClk_AltLfIsEnabled Cy_SysClk_IloEnable Cy_SysClk_IloDisable Cy_SysClk_IloIsEnabled Cy_SysClk_IloHibernateOn Cy_SysClk_ExtClkSetFrequency Cy_SysClk_IhoDisable Cy_SysClk_IhoEnable Cy_SysClk_ClkPathSetSource Cy_SysClk_ClkPathMuxGetFrequency Cy_SysClk_FllGetConfiguration Cy_SysClk_FllLocked Cy_SysClk_FllDisable Cy_SysClk_FllOutputDividerEnable Cy_SysClk_FllConfigure Cy_SysClk_FllManualConfigure Cy_SysClk_FllEnable Cy_SysClk_FllGetFrequency Cy_SysClk_ClkMeasurementCountersDone Cy_SysClk_StartClkMeasurementCounters Cy_SysClk_ClkMeasurementCountersGetFreq Cy_SysClk_PiloTrim Cy_SysClk_PiloInitialTrim Cy_SysClk_PiloUpdateTrimStep Cy_SysClk_PiloSetTrim Cy_SysClk_PiloGetTrim Cy_SysClk_IloTrim Cy_SysClk_DeepSleepCallback cy_en_syspm_status_t Cy_SysClk_PeriphGetFrequency Cy_SysClk_PeriPclkGetFrequency Cy_Sysclk_PeriPclkGetClkHfNum OUTLINED_FUNCTION_0 OUTLINED_FUNCTION_1 OUTLINED_FUNCTION_2 OUTLINED_FUNCTION_3 OUTLINED_FUNCTION_4 OUTLINED_FUNCTION_5 OUTLINED_FUNCTION_6 OUTLINED_FUNCTION_7 dividerValue dividerIntValue dividerFracValue dividerTypePA dividerNumPA source divider fllCfg fllMult refDiv ccoRange enableOutputDiv lockTolerance igain pgain settlingCount outputMode cco_Freq cy_stc_fll_manual_config_t enabled oDiv rDiv fDiv freq groupNum slaveCtl cy_en_peri_grp_sl_ctl_num_t value slaveMsk hfFreq pDiv path enable deepSleepEnable locDiv locFreq timeoutus bypass cy_en_wco_bypass_modes_t on config tempReg inputFreq outputFreq ccoFreq kcco ki_p locpgain locigain cmp res mlt fref divval altval wcoSource trimSteps margin zeroTimeout clock1 cy_en_meas_clks_t count1 clock2 clkOutputFastMask clkOutputSlowMask clkOutputFastVal clkOutputSlowVal measuredClock refClkFreq isMeasurementValid piloFreq iloFreq sign diff trim changeInTrim callbackParams base context cy_stc_syspm_callback_params_t mode cy_en_syspm_callback_mode_t integer hfNum locFrac peri0GrpToHfArray peri1GrpToHfArray Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_gpio.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned int CY_GPIO_SUCCESS CY_GPIO_BAD_PARAM unsigned char HSIOM_SEL_GPIO HSIOM_SEL_GPIO_DSI HSIOM_SEL_DSI_DSI HSIOM_SEL_DSI_GPIO HSIOM_SEL_AMUXA HSIOM_SEL_AMUXB HSIOM_SEL_AMUXA_DSI HSIOM_SEL_AMUXB_DSI HSIOM_SEL_ACT_0 HSIOM_SEL_ACT_1 HSIOM_SEL_ACT_2 HSIOM_SEL_ACT_3 HSIOM_SEL_DS_0 HSIOM_SEL_DS_1 HSIOM_SEL_DS_2 HSIOM_SEL_DS_3 HSIOM_SEL_ACT_4 HSIOM_SEL_ACT_5 HSIOM_SEL_ACT_6 HSIOM_SEL_ACT_7 HSIOM_SEL_ACT_8 HSIOM_SEL_ACT_9 HSIOM_SEL_ACT_10 HSIOM_SEL_ACT_11 HSIOM_SEL_ACT_12 HSIOM_SEL_ACT_13 HSIOM_SEL_ACT_14 HSIOM_SEL_ACT_15 HSIOM_SEL_DS_4 HSIOM_SEL_DS_5 HSIOM_SEL_DS_6 HSIOM_SEL_DS_7 P0_0_GPIO P0_0_TCPWM0_LINE_COMPL0 P0_0_TCPWM0_LINE_COMPL262 P0_0_KEYSCAN_KS_COL3 P0_0_PDM_PDM_CLK1 P0_0_TDM_TDM_RX_MCK0 P0_0_BTSS_DEBUG12 P0_0_SCB0_SPI_SELECT1 P0_1_GPIO P0_1_TCPWM0_LINE1 P0_1_TCPWM0_LINE256 P0_1_KEYSCAN_KS_COL4 P0_1_PDM_PDM_DATA1 P0_1_TDM_TDM_RX_SCK0 P0_1_BTSS_DEBUG13 P0_1_SCB0_SPI_SELECT2 P0_2_GPIO P0_2_TCPWM0_LINE_COMPL1 P0_2_TCPWM0_LINE_COMPL256 P0_2_KEYSCAN_KS_COL11 P0_2_SCB0_I2C_SCL P0_2_PERI_TR_IO_INPUT4 P0_2_TDM_TDM_RX_FSYNC0 P0_2_BTSS_DEBUG14 P0_2_SCB0_SPI_MOSI P0_3_GPIO P0_3_TCPWM0_LINE0 P0_3_TCPWM0_LINE257 P0_3_KEYSCAN_KS_COL12 P0_3_SCB0_I2C_SDA P0_3_SCB1_SPI_SELECT3 P0_3_PERI_TR_IO_INPUT5 P0_3_TDM_TDM_RX_SD0 P0_3_BTSS_DEBUG15 P0_3_SCB0_SPI_MISO P0_4_GPIO P0_4_TCPWM0_LINE_COMPL0 P0_4_TCPWM0_LINE_COMPL257 P0_4_BTSS_GPIO5 P0_4_BTSS_TXD_PYLD_MOD_TEST1 P0_4_KEYSCAN_KS_ROW0 P0_4_SRSS_EXT_CLK P0_4_CPUSS_TRACE_DATA3 P0_4_SCB1_SPI_SELECT2 P0_4_PERI_TR_IO_INPUT0 P0_4_TDM_TDM_TX_MCK0 P0_4_BTSS_DEBUG3 P0_4_BTSS_SPI_CLK P0_4_SCB0_SPI_CLK P0_4_IOSS_DDFT_PIN1 P0_5_GPIO P0_5_TCPWM0_LINE1 P0_5_TCPWM0_LINE258 P0_5_BTSS_ANTENNA_SWITCH_CTRL0 P0_5_BTSS_TX_ST_TEST P0_5_KEYSCAN_KS_ROW1 P0_5_CPUSS_TRACE_DATA2 P0_5_SCB1_SPI_SELECT1 P0_5_PERI_TR_IO_INPUT1 P0_5_TDM_TDM_TX_SCK0 P0_5_BTSS_GCI_GPIO0 P0_5_BTSS_DEBUG4 P0_5_SMIF_SPIHB_SELECT1 P1_0_GPIO P1_0_TCPWM0_LINE_COMPL1 P1_0_TCPWM0_LINE_COMPL258 P1_0_BTSS_ANTENNA_SWITCH_CTRL1 P1_0_BTSS_RPU_TDO P1_0_KEYSCAN_KS_ROW5 P1_0_CPUSS_TRACE_DATA1 P1_0_SCB1_UART_CTS P1_0_SCB1_SPI_SELECT0 P1_0_PERI_TR_IO_OUTPUT0 P1_0_TDM_TDM_TX_FSYNC0 P1_0_BTSS_GCI_GPIO1 P1_0_BTSS_DEBUG5 P1_0_CPUSS_SWJ_SWO_TDO P1_1_GPIO P1_1_TCPWM0_LINE0 P1_1_TCPWM0_LINE259 P1_1_BTSS_ANTENNA_SWITCH_CTRL2 P1_1_BTSS_RPU_TDI P1_1_KEYSCAN_KS_ROW6 P1_1_CPUSS_TRACE_DATA0 P1_1_SCB1_UART_RTS P1_1_SCB1_SPI_CLK P1_1_PERI_TR_IO_OUTPUT1 P1_1_TDM_TDM_TX_SD0 P1_1_BTSS_GCI_GPIO2 P1_1_BTSS_DEBUG6 P1_1_BTSS_UART_TXD P1_1_CPUSS_SWJ_SWDOE_TDI P1_1_IOSS_DDFT_PIN0 P1_2_GPIO P1_2_TCPWM0_LINE_COMPL0 P1_2_TCPWM0_LINE_COMPL259 P1_2_BTSS_GPIO0 P1_2_BTSS_RPU_SWD P1_2_KEYSCAN_KS_COL17 P1_2_CPUSS_TRACE_CLOCK P1_2_SCB1_UART_RX P1_2_SCB2_I2C_SCL P1_2_SCB1_SPI_MOSI P1_2_PERI_TR_IO_INPUT2 P1_2_BTSS_GCI_GPIO3 P1_2_BTSS_DEBUG7 P1_2_BTSS_SPI_MOSI P1_2_CPUSS_SWJ_SWDIO_TMS P1_3_GPIO P1_3_TCPWM0_LINE1 P1_3_TCPWM0_LINE260 P1_3_BTSS_GPIO1 P1_3_BTSS_RPU_TCK P1_3_KEYSCAN_KS_COL16 P1_3_SRSS_EXT_CLK P1_3_SCB1_UART_TX P1_3_SCB2_I2C_SDA P1_3_SCB1_SPI_MISO P1_3_PERI_TR_IO_INPUT3 P1_3_BTSS_GCI_GPIO4 P1_3_BTSS_DEBUG8 P1_3_BTSS_SPI_CLK P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK P1_4_GPIO P1_4_TCPWM0_LINE_COMPL1 P1_4_TCPWM0_LINE_COMPL260 P1_4_BTSS_GPIO5 P1_4_KEYSCAN_KS_COL15 P1_4_KEYSCAN_KS_COL16 P1_4_LIN0_LIN_EN1 P1_4_BTSS_GCI_GPIO2 P1_4_BTSS_DEBUG9 P1_5_GPIO P1_5_TCPWM0_LINE0 P1_5_TCPWM0_LINE261 P1_5_BTSS_GPIO6 P1_5_KEYSCAN_KS_COL5 P1_5_LIN0_LIN_RX1 P1_5_BTSS_DEBUG10 P1_6_GPIO P1_6_TCPWM0_LINE_COMPL0 P1_6_TCPWM0_LINE_COMPL261 P1_6_BTSS_GPIO7 P1_6_KEYSCAN_KS_COL6 P1_6_SRSS_CAL_WAVE P1_6_LIN0_LIN_TX1 P1_6_BTSS_DEBUG11 P2_0_GPIO P2_0_SMIF_SPIHB_SELECT0 P2_1_GPIO P2_1_SMIF_SPIHB_DATA3 P2_2_GPIO P2_2_SMIF_SPIHB_DATA2 P2_3_GPIO P2_3_SMIF_SPIHB_DATA1 P2_4_GPIO P2_4_SMIF_SPIHB_DATA0 P2_5_GPIO P2_5_SMIF_SPIHB_CLK P3_0_GPIO P3_0_TCPWM0_LINE0 P3_0_TCPWM0_LINE256 P3_0_KEYSCAN_KS_ROW7 P3_0_CPUSS_TRACE_DATA3 P3_0_SCB2_UART_CTS P3_0_SCB1_SPI_SELECT0 P3_0_BTSS_UART_CTS P3_1_GPIO P3_1_TCPWM0_LINE_COMPL0 P3_1_TCPWM0_LINE_COMPL256 P3_1_BTSS_RPU_NTRST P3_1_KEYSCAN_KS_ROW4 P3_1_CPUSS_TRACE_DATA2 P3_1_SCB2_UART_RTS P3_1_SCB1_SPI_CLK P3_1_LIN0_LIN_EN0 P3_1_BTSS_UART_RTS P3_1_BTSS_SYSCLK_RF P3_1_CPUSS_RST_SWJ_TRSTN P3_2_GPIO P3_2_TCPWM0_LINE1 P3_2_TCPWM0_LINE257 P3_2_BTSS_TXD_SYMB_DATA_TEST0 P3_2_KEYSCAN_KS_COL13 P3_2_CPUSS_TRACE_DATA1 P3_2_SCB2_UART_RX P3_2_SCB2_I2C_SCL P3_2_SCB1_SPI_MOSI P3_2_PDM_PDM_CLK0 P3_2_PERI_TR_IO_INPUT6 P3_2_LIN0_LIN_RX0 P3_2_CANFD0_TTCAN_RX0 P3_2_ADCMIC_CLK_PDM P3_2_BTSS_UART_RXD P3_2_IOSS_DDFT_PIN1 P3_3_GPIO P3_3_TCPWM0_LINE_COMPL1 P3_3_TCPWM0_LINE_COMPL257 P3_3_BTSS_TXD_SYMB_DATA_TEST1 P3_3_KEYSCAN_KS_COL14 P3_3_KEYSCAN_KS_COL17 P3_3_CPUSS_TRACE_DATA0 P3_3_SCB2_UART_TX P3_3_SCB2_I2C_SDA P3_3_SCB1_SPI_MISO P3_3_PDM_PDM_DATA0 P3_3_PERI_TR_IO_INPUT7 P3_3_LIN0_LIN_TX0 P3_3_CANFD0_TTCAN_TX0 P3_3_ADCMIC_PDM_DATA P3_3_BTSS_UART_TXD P3_3_IOSS_DDFT_PIN0 P3_4_GPIO P3_4_TCPWM0_LINE0 P3_4_TCPWM0_LINE258 P3_4_BTSS_GPIO0 P3_4_KEYSCAN_KS_COL7 P3_4_CPUSS_TRACE_CLOCK P3_4_SCB1_SPI_SELECT3 P3_4_BTSS_DEBUG3 P3_5_GPIO P3_5_TCPWM0_LINE_COMPL0 P3_5_TCPWM0_LINE_COMPL258 P3_5_BTSS_GPIO1 P3_5_KEYSCAN_KS_COL8 P3_5_SCB1_SPI_SELECT2 P3_5_BTSS_DEBUG1 P3_6_GPIO P3_6_TCPWM0_LINE1 P3_6_TCPWM0_LINE259 P3_6_KEYSCAN_KS_COL9 P3_6_SCB1_SPI_SELECT1 P3_6_BTSS_DEBUG2 P3_7_GPIO P3_7_TCPWM0_LINE_COMPL1 P3_7_TCPWM0_LINE_COMPL259 P3_7_BTSS_ANTENNA_SWITCH_CTRL3 P3_7_KEYSCAN_KS_COL10 P3_7_BTSS_DEBUG7 P4_0_GPIO P4_0_TCPWM0_LINE_COMPL1 P4_0_TCPWM0_LINE_COMPL261 P4_0_BTSS_GPIO2 P4_0_BTSS_TXD_SYMB_STRB_TEST P4_0_KEYSCAN_KS_ROW2 P4_0_SCB0_I2C_SCL P4_0_SCB2_UART_CTS P4_0_BTSS_DEBUG1 P4_0_BTSS_UART_TXD P4_0_SCB0_SPI_MOSI P4_1_GPIO P4_1_TCPWM0_LINE0 P4_1_TCPWM0_LINE262 P4_1_BTSS_GPIO4 P4_1_BTSS_TXD_PYLD_MOD_TEST0 P4_1_KEYSCAN_KS_ROW3 P4_1_SCB0_I2C_SDA P4_1_BTSS_DEBUG2 P4_1_BTSS_SPI_MOSI P4_1_SCB0_SPI_MISO P5_0_GPIO P5_0_TCPWM0_LINE0 P5_0_TCPWM0_LINE260 P5_0_BTSS_TXD_SYMB_DATA_TEST2 P5_0_KEYSCAN_KS_COL0 P5_0_SCB2_UART_CTS P5_0_SCB1_SPI_SELECT0 P5_0_PDM_PDM_CLK0 P5_0_ADCMIC_CLK_PDM P5_0_BTSS_UART_CTS P5_1_GPIO P5_1_TCPWM0_LINE_COMPL0 P5_1_TCPWM0_LINE_COMPL260 P5_1_BTSS_GPIO3 P5_1_BTSS_TXD_SYMB_DATA_TEST3 P5_1_KEYSCAN_KS_COL1 P5_1_PDM_PDM_DATA0 P5_1_ADCMIC_PDM_DATA P5_1_BTSS_DEBUG0 P5_1_BTSS_UART_RXD P5_1_SCB0_SPI_SELECT0 P5_2_GPIO P5_2_TCPWM0_LINE1 P5_2_TCPWM0_LINE261 P5_2_BTSS_GPIO4 P5_2_KEYSCAN_KS_COL2 P5_2_BTSS_DEBUG8 AMUX_SPLIT_CTL_0 CY_GPIO_AMUX_OPENALL CY_GPIO_AMUX_L CY_GPIO_AMUX_R CY_GPIO_AMUX_LR CY_GPIO_AMUX_G CY_GPIO_AMUX_GL CY_GPIO_AMUX_GR CY_GPIO_AMUX_GLR CY_GPIO_AMUXBUSA CY_GPIO_AMUXBUSB OUT uint32_t OUT_CLR OUT_SET OUT_INV IN INTR INTR_MASK INTR_MASKED INTR_SET RESERVED __ARRAY_SIZE_TYPE__ INTR_CFG CFG CFG_IN CFG_OUT CFG_SIO RESERVED1 CFG_IN_AUTOLVL RESERVED2 CFG_OUT2 CFG_SLEW_EXT CFG_DRIVE_EXT0 CFG_DRIVE_EXT1 RESERVED3 GPIO_PRT_Type PORT_SEL0 PORT_SEL1 HSIOM_PRT_Type cy_en_gpio_amuxconnect_t en_hsiom_sel_t Cy_GPIO_SetSlewRate base pinNum value pinLoc tempReg Cy_GPIO_SetDrivemode prtCfg Cy_GPIO_SetInterruptEdge intrCfg Cy_GPIO_SetInterruptMask intrMask Cy_GPIO_SetVtrip cfgIn Cy_GPIO_Write outMask Cy_GPIO_Pin_Init cy_en_gpio_status_t Cy_GPIO_SetDriveSel Cy_GPIO_SetHSIOM Cy_GPIO_Port_Init Cy_GPIO_Pin_FastInit Cy_GPIO_Port_Deinit Cy_GPIO_SetAmuxSplit Cy_GPIO_GetAmuxSplit Cy_GPIO_GetHSIOM Cy_GPIO_Read Cy_GPIO_ReadOut Cy_GPIO_Set Cy_GPIO_Clr Cy_GPIO_Inv Cy_GPIO_GetDrivemode Cy_GPIO_GetVtrip Cy_GPIO_GetSlewRate Cy_GPIO_GetDriveSel Cy_GPIO_SetVregEn Cy_GPIO_GetVregEn Cy_GPIO_SetIbufMode Cy_GPIO_GetIbufMode Cy_GPIO_SetVtripSel Cy_GPIO_GetVtripSel Cy_GPIO_SetVrefSel Cy_GPIO_GetVrefSel Cy_GPIO_SetVohSel Cy_GPIO_GetVohSel Cy_GPIO_GetInterruptStatus Cy_GPIO_ClearInterrupt Cy_GPIO_GetInterruptMask Cy_GPIO_GetInterruptStatusMasked Cy_GPIO_SetSwInterrupt Cy_GPIO_GetInterruptEdge Cy_GPIO_SetFilter Cy_GPIO_GetFilter OUTLINED_FUNCTION_0 config outVal driveMode hsiom intEdge intMask vtrip slewRate driveSel vregEn ibufMode vtripSel vrefSel vohSel nonSec cy_stc_gpio_pin_config_t status tempReg2 portNum portAddrHSIOM hsiomReg out cfg cfgOut cfgSIO sel0Active sel1Active cfgSlew cfgDriveSel0 cfgDriveSel1 nonSecMask cy_stc_gpio_prt_config_t baseHSIOM switchCtrl cy_en_amux_split_t amuxConnect amuxBus cy_en_gpio_amuxselect_t returnValue ret prtIntr intrSet Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/devices/COMPONENT_CAT1B/source\cy_device.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv cy_device hsiomBase unsigned int uint32_t gpioBase dwVersion unsigned char uint8_t cpussDw0ChNr cpussDw1ChNr epMonitorNr dwChOffset unsigned short uint16_t dwChSize dwChCtlPrioPos dwChCtlPreemptablePos dwStatusChIdxPos dwStatusChIdxMsk tcpwmCC1Present tcpwmAMCPresent tcpwmSMCPrecent cy_stc_device_t cy_deviceIpBlockCfg Cy_PDL_Init device Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_syslib.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv cy_assertFileName char char_t __ARRAY_SIZE_TYPE__ cy_assertLine unsigned int uint32_t cy_faultFrame r0 r1 r2 r3 r12 lr pc psr cy_stc_fault_frame_t CY_SYSLIB_SUCCESS CY_SYSLIB_BAD_PARAM CY_SYSLIB_TIMEOUT CY_SYSLIB_INVALID_STATE CY_SYSLIB_UNKNOWN CY_EFUSE_SUCCESS CY_EFUSE_INVALID_PROTECTION CY_EFUSE_INVALID_FUSE_ADDR CY_EFUSE_BAD_PARAM CY_EFUSE_IPC_BUSY CY_EFUSE_WRITE_BUSY CY_EFUSE_WRITE_ERROR CY_EFUSE_WRITE_TIMEOUT_ERROR CY_EFUSE_ERR_UNC CTL RESERVED RTC_RW CAL_CTL STATUS RTC_TIME RTC_DATE ALM1_TIME ALM1_DATE ALM2_TIME ALM2_DATE INTR INTR_SET INTR_MASK INTR_MASKED RESERVED1 PMIC_CTL RESET RESERVED2 LPECO_CTL LPECO_PRESCALE LPECO_STATUS RESERVED3 WCO_STATUS RESERVED4 CSV_BAK CSV REF_CTL REF_LIMIT MON_CTL BACKUP_CSV_BAK_CSV_Type BACKUP_CSV_BAK_Type RESERVED5 BREG_SET0 BREG_SET1 BREG_SET2 RESERVED6 BREG_SET3 BACKUP_Type PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED SRSS_AINTR SRSS_AINTR_SET SRSS_AINTR_MASK SRSS_AINTR_MASKED TST_DEBUG_CTL TST_DEBUG_STATUS RES_SOFT_CTL PWR_HIB_DATA RESERVED7 PWR_HIB_WAKE_CTL PWR_HIB_WAKE_CTL2 RESERVED8 PWR_HIB_WAKE_CAUSE RESERVED9 PWR_CTL PWR_CTL2 PWR_HIBERNATE RESERVED10 PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 RESERVED11 PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 RESERVED12 PWR_PMIC_CTL4 RESERVED13 CLK_PATH_SELECT CLK_ROOT_SELECT CLK_DIRECT_SELECT RESERVED14 CSV_HF CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT RESERVED15 CLK_ILO0_CONFIG CLK_ILO1_CONFIG RESERVED16 CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG RESERVED17 CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 CLK_ILO_CONFIG CLK_TRIM_ILO_CTL CLK_TRIM_ILO0_CTL CLK_MF_SELECT CLK_MFO_CONFIG RESERVED18 CLK_IHO_CONFIG CLK_ALTHF_CTL RESERVED19 CLK_PLL_CONFIG RESERVED20 CLK_PLL_STATUS RESERVED21 CSV_REF_SEL RESERVED22 CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RESERVED23 RES_CAUSE RES_CAUSE2 RES_CAUSE_EXTEND RESERVED24 RES_PXRES_CTL RESERVED25 CLK_PLL400M CONFIG CONFIG2 CONFIG3 CLK_PLL400M_Type RESERVED26 PWR_CBUCK_CTL PWR_CBUCK_CTL2 PWR_CBUCK_CTL3 PWR_CBUCK_STATUS PWR_SDR0_CTL PWR_SDR1_CTL RESERVED27 PWR_HVLDO0_CTL RESERVED28 TST_XRES_SECURE RESERVED29 PWR_TRIM_CBUCK_CTL RESERVED30 CLK_TRIM_ECO_CTL RESERVED31 CLK_TRIM_ILO1_CTL RESERVED32 WDT_CTL WDT_CNT WDT_MATCH WDT_MATCH2 RESERVED33 MCWDT_STRUCT MCWDT_CNTLOW MCWDT_CNTHIGH MCWDT_MATCH MCWDT_CONFIG MCWDT_CTL MCWDT_INTR MCWDT_INTR_SET MCWDT_INTR_MASK MCWDT_INTR_MASKED MCWDT_LOCK MCWDT_LOWER_LIMIT MCWDT_STRUCT_Type SRSS_Type TEST CMD SEQ_DEFAULT SEQ_READ_CTL_0 SEQ_READ_CTL_1 SEQ_READ_CTL_2 SEQ_READ_CTL_3 SEQ_READ_CTL_4 SEQ_READ_CTL_5 SEQ_READ_CTL_6 SEQ_READ_CTL_7 SEQ_PROGRAM_CTL_0 SEQ_PROGRAM_CTL_1 SEQ_PROGRAM_CTL_2 SEQ_PROGRAM_CTL_3 SEQ_PROGRAM_CTL_4 SEQ_PROGRAM_CTL_5 SEQ_PROGRAM_CTL_6 SEQ_PROGRAM_CTL_7 BOOTROW EFUSE_Type unsigned long long uint64_t unsigned char uint8_t IDENTITY PRODUCT_ID DP_STATUS BUFF_CTL CAL_SUP_SET CAL_SUP_CLR INFRA_CTL SYSTICK_S_CTL SYSTICK_NS_CTL INTR_MSC INTR_MASK_MSC INTR_MASKED_MSC AHB_ERROR_STATUS1 AHB_ERROR_STATUS2 INTR_AHB_ERROR INTR_SET_AHB_ERROR INTR_MASK_AHB_ERROR INTR_MASKED_AHB_ERROR AP_CTL PROTECTION TRIM_ROM_CTL TRIM_RAM_CTL TRIM_RAM_CTL2 TRIM_RAM_CTL3 TRIM_RAM_CTL4 CPUSS_Type Cy_SysLib_DelayCycles Cy_SysLib_Halt reason Cy_SysLib_GetResetStatus cy_en_syslib_status_t Cy_SysLib_AsmInfiniteLoop Cy_SysLib_Delay Cy_SysLib_DelayUs Cy_SysLib_Rtos_Delay Cy_SysLib_Rtos_DelayUs Cy_SysLib_AssertFailed Cy_SysLib_ResetBackupDomain Cy_SysLib_GetResetReason Cy_SysLib_ClearResetReason Cy_SysLib_GetUniqueId Cy_SysLib_FaultHandler Cy_SysLib_ProcessingFault Cy_SysLib_SetWaitStates Cy_SysLib_GetDeviceRevision Cy_SysLib_GetDevice unsigned short uint16_t Cy_Syslib_SetWarmBootEntryPoint milliseconds max_delay_ms microseconds file line retVal dieRead status cy_en_efuse_status_t uniqueIdHi uniqueIdLo faultStackAddr ulpMode _Bool clkHfMHz entryPoint enable Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_smif_sfdp.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES CY_SMIF_SFDP_QER_0 CY_SMIF_SFDP_QER_1 CY_SMIF_SFDP_QER_2 CY_SMIF_SFDP_QER_3 CY_SMIF_SFDP_QER_4 CY_SMIF_SFDP_QER_5 CY_SMIF_SFDP_QER_6 PROTOCOL_MODE_1S_1S_1S PROTOCOL_MODE_1S_1S_2S PROTOCOL_MODE_1S_2S_2S PROTOCOL_MODE_1S_1S_4S PROTOCOL_MODE_1S_4S_4S PROTOCOL_MODE_1S_4D_4D PROTOCOL_MODE_1S_1S_8S PROTOCOL_MODE_1S_8S_8S PROTOCOL_MODE_8D_8D_8D PROTOCOL_MODE_WRONG uint8_t cy_en_smif_qer_t uint32_t CTL STATUS RESERVED __ARRAY_SIZE_TYPE__ INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DL_CTL RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 TX_CMD_FIFO_STATUS TX_CMD_MMIO_FIFO_STATUS RESERVED3 TX_CMD_MMIO_FIFO_WR RESERVED4 TX_DATA_MMIO_FIFO_CTL TX_DATA_FIFO_STATUS TX_DATA_MMIO_FIFO_STATUS RESERVED5 TX_DATA_MMIO_FIFO_WR1 TX_DATA_MMIO_FIFO_WR2 TX_DATA_MMIO_FIFO_WR4 TX_DATA_MMIO_FIFO_WR1ODD RESERVED6 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED7 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED8 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED9 SLOW_CA_CTL RESERVED10 SLOW_CA_CMD RESERVED11 FAST_CA_CTL RESERVED12 FAST_CA_CMD RESERVED13 SMIF_CRYPTO_BLOCK CRYPTO_CMD CRYPTO_ADDR CRYPTO_MASK CRYPTO_SUBREGION CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 SMIF_SMIF_CRYPTO_Type CRC_CMD RESERVED14 CRC_INPUT0 CRC_INPUT1 RESERVED15 CRC_OUTPUT RESERVED16 INTR INTR_SET INTR_MASK INTR_MASKED INTR_CAUSE RESERVED17 DEVICE ADDR MASK ADDR_CTL DELAY_TAP_SEL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type RESERVED18 MPC CFG INTR_INFO1 INTR_INFO2 CTRL BLK_MAX BLK_CFG BLK_IDX BLK_LUT ROT_CTRL ROT_CFG ROT_BLK_MAX ROT_BLK_CFG ROT_BLK_IDX ROT_BLK_PC ROT_BLK_LUT SMIF_MPC_Type SMIF_Type _Bool unsigned short uint16_t SfdpGetEraseSizeAndCmd sfdpBuffer eraseType eraseCmd eraseSize eraseTime cy_stc_smif_erase_type_t idx currET Cy_SMIF_PackBytesArray buff fourBytes result SfdpGetMemoryDensity locSize memorySize SfdpGetNumOfAddrBytes addrBytesNum sfdpAddrCode SfdpSetWriteEnableCommand cmdWriteEnable command cmdWidth cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate cy_en_smif_data_rate_t dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t SfdpSetWriteDisableCommand cmdWriteDisable SfdpSetWipStatusRegisterCommand readStsRegWipCmd SfdpSetChipEraseCommand cmdChipErase SfdpGetPageSize size SfdpGetChipEraseTime readEraseTime chipEraseProgTime eraseMul chipEraseMs chipEraseCount chipEraseTimeMax chipEraseUnits SfdpGetPageProgramTime programTimeCount progUs progMul programTimeUnits programTimeMax SfdpGetReadCmdParams cy_en_smif_protocol_mode_t dataSelect cy_en_smif_data_select_t maxDataWidth cmdRead protocolMode sfdpDataIndex quadEnabled SfdpGetReadCmd_1_1_1 SfdpGetReadCmd_1_4_4 SfdpGetReadCmd_1_2_2 SfdpGetReadCmd_1_1_4 SfdpGetReadCmd_1S_4D_4D SfdpGetReadCmd_1_1_2 SfdpEnterFourByteAddressing cy_en_smif_status_t base entryMethodByte device numOfAddrBytes memSize readCmd writeEnCmd writeDisCmd chipEraseCmd programCmd programSize readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t slaveSelect cy_en_smif_slave_select_t context txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate preCmdWidth preXIPDataRate cy_stc_smif_context_t writeEn GetOctalDDRParams cmdSeqODDRAddr cmdSeqODDRTableLength xSPiProfile1Addr xSPIProfile1TableLength sccrMapAddr sccrMapTableLength xSPiProfile1AddrBuffer cmdSfdp pMode i cmdSeqODDRAddrBuffer cfr_reg_address cfr_value oDDREnSeq SfdpGetReadFourBytesCmd sfdpForBytesTableDword1 SfdpSetVariableLatencyCmd cmdWriteLatency cmdReadLatency sccrMapDWord9Value sccrMapDW9_Address latencyBits latencyMaskoffset SfdpGetProgramFourBytesCmd cmdProgram SfdpSetProgramCommandFourBytes_1_4_4 SfdpGetEraseTime eraseOffset eraseMs eraseCount eraseUnits eraseTimeDefaultIndex eraseTypeTypicalTime SfdpPopulateRegionInfo sectorMapBuff buffLength currRegisterAddr addrCode currTableIdx regionInfoIdx regValue currCmd regMask numOfRegions regionSize currRegionAddr eraseTypeMask supportedEraseType currRegionPtr eraseTypeCode currRegion ReadAnyReg value address addressSize Cy_SMIF_GetDeviceBySlot XipRegInit dev memCfg flags baseAddress memMappedSize dualQuadSlots deviceCfg mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t read prog devCfg ByteArrayToValue byteArray Cy_SMIF_MemCmdWriteRegister writeCmd cmdParam paramSize SfdpFindParameterHeader id headerOffset maxMinorRevison sfdpAddress Cy_SMIF_MemInitSfdpMode SfdpReadBuffer SfdpFindParameterTableAddress SfdpGetQuadEnableParameters SfdpGetSectorEraseCommand SfdpSetProgramCommand_1_1_1 Cy_SMIF_MemSfdpDetect ValueToByteArray SfdpSetProgramCommandFourBytes_1_1_4 SfdpSetProgramCommandFourBytes_1_1_1 OUTLINED_FUNCTION_0 OUTLINED_FUNCTION_1 OUTLINED_FUNCTION_2 addr4ByteAddress sectorMapAddr fourByteAddressBuffer maxdataWidth qer_id basicSpiTableLength addr4ByteTableLength sectorMapTableLength eraseTypeOffset octalProtocolMode sfdp_minor_revision device_base sfdpAddr_4byte int is2byte_command tableLength qerId eraseTypeStc memSfdpDetect startPos Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_smif_memslot.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES CY_RSLT_TYPE_INFO CY_RSLT_TYPE_WARNING CY_RSLT_TYPE_ERROR CY_RSLT_TYPE_FATAL uint32_t CTL RESERVED ADDR MASK RESERVED1 __ARRAY_SIZE_TYPE__ ADDR_CTL RESERVED2 DELAY_TAP_SEL RD_STATUS RESERVED3 RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL RESERVED4 WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL RESERVED5 SMIF_DEVICE_Type STATUS INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DL_CTL DL_STATUS0 DL_STATUS1 TX_CMD_FIFO_STATUS TX_CMD_MMIO_FIFO_STATUS TX_CMD_MMIO_FIFO_WR TX_DATA_MMIO_FIFO_CTL TX_DATA_FIFO_STATUS TX_DATA_MMIO_FIFO_STATUS TX_DATA_MMIO_FIFO_WR1 TX_DATA_MMIO_FIFO_WR2 TX_DATA_MMIO_FIFO_WR4 TX_DATA_MMIO_FIFO_WR1ODD RESERVED6 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED7 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED8 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED9 SLOW_CA_CTL RESERVED10 SLOW_CA_CMD RESERVED11 FAST_CA_CTL RESERVED12 FAST_CA_CMD RESERVED13 SMIF_CRYPTO_BLOCK CRYPTO_CMD CRYPTO_ADDR CRYPTO_MASK CRYPTO_SUBREGION CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 SMIF_SMIF_CRYPTO_Type CRC_CMD RESERVED14 CRC_INPUT0 CRC_INPUT1 RESERVED15 CRC_OUTPUT RESERVED16 INTR INTR_SET INTR_MASK INTR_MASKED INTR_CAUSE RESERVED17 DEVICE RESERVED18 MPC CFG INTR_INFO1 INTR_INFO2 CTRL BLK_MAX BLK_CFG BLK_IDX BLK_LUT ROT_CTRL ROT_CFG ROT_BLK_MAX ROT_BLK_CFG ROT_BLK_IDX ROT_BLK_PC ROT_BLK_LUT SMIF_MPC_Type SMIF_Type _Bool cy_en_smif_status_t unsigned short uint16_t uint8_t cy_en_smif_slave_select_t slaveSelect flags dataSelect cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg numOfAddrBytes memSize readCmd command cmdWidth cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate cy_en_smif_data_rate_t dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t writeEnCmd writeDisCmd eraseCmd eraseSize chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask eraseTime chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t Cy_SMIF_GetDeviceBySlot base device XipRegInit dev memCfg read prog devCfg Cy_SMIF_ReceiveDataBlocking txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate preCmdWidth preXIPDataRate cy_stc_smif_context_t cy_smif_octalddrenable memDevice context result oDDREnSeq ReadAnyReg value address addressSize ByteArrayToValue byteArray size idx Cy_SMIF_MemInit Cy_SMIF_MemDeInit Cy_SMIF_MemCmdWriteEnable Cy_SMIF_MemCmdWriteDisable Cy_SMIF_MemIsBusy Cy_SMIF_MemCmdReadStatus Cy_SMIF_MemQuadEnable Cy_SMIF_MemCmdWriteStatus Cy_SMIF_MemOctalEnable Cy_SMIF_MemCmdChipErase Cy_SMIF_MemCmdSectorErase Cy_SMIF_MemLocateHybridRegion Cy_SMIF_MemCmdProgram Cy_SMIF_MemCmdRead Cy_SMIF_SetReadyPollingDelay Cy_SMIF_MemIsReady Cy_SMIF_MemIsQuadEnabled Cy_SMIF_MemEnableQuadMode Cy_SMIF_MemRead ValueToByteArray Cy_SMIF_MemWrite Cy_SMIF_MemEraseSector Cy_SMIF_MemEraseChip Cy_SMIF_MemCmdPowerDown Cy_SMIF_MemCmdReleasePowerDown OUTLINED_FUNCTION_0 OUTLINED_FUNCTION_1 OUTLINED_FUNCTION_2 OUTLINED_FUNCTION_3 OUTLINED_FUNCTION_4 OUTLINED_FUNCTION_5 OUTLINED_FUNCTION_6 OUTLINED_FUNCTION_7 blockConfig memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t sfdpRes sfdpRet extMemCfg deviceIndex writeEn writeDis status readStsResult addr_param statusReg readWipCmd readQeCmd qeMask writeQeCmd octalEnableAddr writeOeCmd readOeCmd oeMask cmdErase sectorAddr hybrInfo eraseCommand regionInfo currInfo regionEndAddr regionStartAddr addr writeBuff cmdCompleteCb cmdProg slaveSelected readBuff cmdRead pollTimeoutUs timeoutUs isBusy pollingDelay delayMs timeoutSlice delayUs isQuadEnabled readStatus maskQE statusCmd rxBuffer length chunk addrArray interruptState startPos txBuffer offset pageSize cmdProgram hybridRegionStart hybridRegionEnd endAddress maxEraseTime eraseSectorSize sectorOffsetInRegion offsetInRegion Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/pdl/drivers/source\cy_smif.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_NORMAL CY_SMIF_MEMORY CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_STARTED CY_SMIF_SEND_COMPLETE CY_SMIF_SEND_BUSY CY_SMIF_RX_COMPLETE CY_SMIF_RX_BUSY CY_SMIF_XIP_ERROR CY_SMIF_CMD_ERROR CY_SMIF_TX_ERROR CY_SMIF_RX_ERROR CY_SMIF_CACHE_SLOW CY_SMIF_CACHE_FAST CY_SMIF_CACHE_BOTH CY_SYSPM_SUCCESS CY_SYSPM_BAD_PARAM CY_SYSPM_TIMEOUT CY_SYSPM_INVALID_STATE CY_SYSPM_CANCELED CY_SYSPM_SYSCALL_PENDING CY_SYSPM_FAIL CY_SYSPM_CHECK_READY CY_SYSPM_CHECK_FAIL CY_SYSPM_BEFORE_TRANSITION CY_SYSPM_AFTER_TRANSITION CY_SYSPM_AFTER_DS_WFI_TRANSITION CTL uint32_t STATUS RESERVED __ARRAY_SIZE_TYPE__ INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DL_CTL RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 TX_CMD_FIFO_STATUS TX_CMD_MMIO_FIFO_STATUS RESERVED3 TX_CMD_MMIO_FIFO_WR RESERVED4 TX_DATA_MMIO_FIFO_CTL TX_DATA_FIFO_STATUS TX_DATA_MMIO_FIFO_STATUS RESERVED5 TX_DATA_MMIO_FIFO_WR1 TX_DATA_MMIO_FIFO_WR2 TX_DATA_MMIO_FIFO_WR4 TX_DATA_MMIO_FIFO_WR1ODD RESERVED6 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED7 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED8 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED9 SLOW_CA_CTL RESERVED10 SLOW_CA_CMD RESERVED11 FAST_CA_CTL RESERVED12 FAST_CA_CMD RESERVED13 SMIF_CRYPTO_BLOCK CRYPTO_CMD CRYPTO_ADDR CRYPTO_MASK CRYPTO_SUBREGION CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 SMIF_SMIF_CRYPTO_Type CRC_CMD RESERVED14 CRC_INPUT0 CRC_INPUT1 RESERVED15 CRC_OUTPUT RESERVED16 INTR INTR_SET INTR_MASK INTR_MASKED INTR_CAUSE RESERVED17 DEVICE ADDR MASK ADDR_CTL DELAY_TAP_SEL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type RESERVED18 MPC CFG INTR_INFO1 INTR_INFO2 CTRL BLK_MAX BLK_CFG BLK_IDX BLK_LUT ROT_CTRL ROT_CFG ROT_BLK_MAX ROT_BLK_CFG ROT_BLK_IDX ROT_BLK_PC ROT_BLK_LUT SMIF_MPC_Type SMIF_Type unsigned short uint16_t uint8_t txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate cy_en_smif_data_rate_t preCmdWidth cy_en_smif_txfr_width_t preXIPDataRate cy_stc_smif_context_t cy_en_smif_txfr_status_t Cy_SMIF_GetInterruptMask base Cy_SMIF_SetInterruptMask interrupt Cy_SMIF_GetDeviceBySlot slaveSelect cy_en_smif_slave_select_t device Cy_SMIF_GetCmdFifoStatus Cy_SMIF_PushTxFifo baseaddr context buffCounter buff writeBytes freeFifoBytes Cy_SMIF_PackBytesArray fourBytes _Bool result Cy_SMIF_PopRxFifo readBytes loadedFifoBytes Cy_SMIF_UnPackByteArray inValue outBuff Cy_SMIF_GetTransferStatus Cy_SMIF_BusyCheck Cy_SMIF_GetMode cy_en_smif_mode_t Cy_SMIF_Disable Cy_SMIF_Init cy_en_smif_status_t Cy_SMIF_DeInit Cy_SMIF_SetMode Cy_SMIF_SetDataSelect Cy_SMIF_TransmitCommand Cy_SMIF_TransmitCommand_Ext Cy_SMIF_TransmitData Cy_SMIF_TransmitData_Ext Cy_SMIF_TransmitDataBlocking Cy_SMIF_TransmitDataBlocking_Ext Cy_SMIF_ReceiveData Cy_SMIF_ReceiveData_Ext Cy_SMIF_ReceiveDataBlocking Cy_SMIF_ReceiveDataBlocking_Ext Cy_SMIF_SendDummyCycles Cy_SMIF_SendDummyCycles_Ext Cy_SMIF_Enable Cy_SMIF_TimeoutRun Cy_SMIF_SetCryptoKey Cy_SMIF_SetCryptoIV Cy_SMIF_ConvertSlaveSlotToIndex Cy_SMIF_SetCryptoEnable Cy_SMIF_SetCryptoDisable Cy_SMIF_Encrypt Cy_SMIF_CacheEnable Cy_SMIF_CacheDisable Cy_SMIF_CachePrefetchingEnable Cy_SMIF_CachePrefetchingDisable Cy_SMIF_CacheInvalidate Cy_SMIF_DeepSleepCallback cy_en_syspm_status_t Cy_SMIF_HibernateCallback OUTLINED_FUNCTION_0 OUTLINED_FUNCTION_1 OUTLINED_FUNCTION_2 OUTLINED_FUNCTION_3 OUTLINED_FUNCTION_4 config mode deselectDelay rxClockSel blockEvent cy_stc_smif_config_t smif_ctl_vlaue idx read_cmd_data_ctl temp dataSelect cy_en_smif_data_select_t cmd cmdTxfrWidth cmdParam paramSize completeTxfr paramTxfrWidth isCommand2byte cmdDataRate bufIndex timeoutUnits constCmdPart paramDataRate txBuffer size transferWidth TxCompleteCb TxCmpltCb dataDataRate trUnitNum contextLoc rxBuffer RxCompleteCb RxCmpltCb dataRate rxUnitNum cycles status key nonce ss device_idx ret slaveId cryptoOut address data outIndex dataIndex cacheType cy_en_smif_cache_t callbackParams cy_stc_syspm_callback_params_t cy_en_syspm_callback_mode_t retStatus locBase locContext checkFail Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/cycfg\cycfg_qspi_memslot_SFDP.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv CFGSMIF_SlaveSlot_0_readCmd command unsigned int uint32_t cmdWidth unsigned char CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate CY_SMIF_SDR CY_SMIF_DDR cy_en_smif_data_rate_t dummyCyclesPresence CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t CFGSMIF_SlaveSlot_0_writeEnCmd CFGSMIF_SlaveSlot_0_writeDisCmd CFGSMIF_SlaveSlot_0_eraseCmd CFGSMIF_SlaveSlot_0_chipEraseCmd CFGSMIF_SlaveSlot_0_programCmd CFGSMIF_SlaveSlot_0_readStsRegQeCmd CFGSMIF_SlaveSlot_0_readStsRegWipCmd CFGSMIF_SlaveSlot_0_writeStsRegQeCmd CFGSMIF_SlaveSlot_0_readSfdpCmd CFGSMIF_SlaveSlot_0_region0 regionAddress sectorsCount eraseCmd eraseSize eraseTime cy_stc_smif_hybrid_region_info_t CFGSMIF_SlaveSlot_0_region1 CFGSMIF_SlaveSlot_0_region2 CFGSMIF_SlaveSlot_0_region3 CFGSMIF_SlaveSlot_0_region4 CFGSMIF_SlaveSlot_0_region5 CFGSMIF_SlaveSlot_0_region6 CFGSMIF_SlaveSlot_0_region7 CFGSMIF_SlaveSlot_0_region8 CFGSMIF_SlaveSlot_0_region9 CFGSMIF_SlaveSlot_0_region10 CFGSMIF_SlaveSlot_0_region11 CFGSMIF_SlaveSlot_0_region12 CFGSMIF_SlaveSlot_0_region13 CFGSMIF_SlaveSlot_0_region14 CFGSMIF_SlaveSlot_0_region15 CFGSMIF_SlaveSlot_0_regionInfo __ARRAY_SIZE_TYPE__ CFGSMIF_deviceCfg_SlaveSlot_0 numOfAddrBytes memSize readCmd writeEnCmd writeDisCmd chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask chipEraseTime programTime hybridRegionCount hybridRegionInfo readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len uint8_t cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t CFGSMIF_SlaveSlot_0 slaveSelect CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 cy_en_smif_slave_select_t flags dataSelect CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg mergeTimeout CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t CFGSMIF_SlaveSlot_1_readCmd CFGSMIF_SlaveSlot_1_writeEnCmd CFGSMIF_SlaveSlot_1_writeDisCmd CFGSMIF_SlaveSlot_1_eraseCmd CFGSMIF_SlaveSlot_1_chipEraseCmd CFGSMIF_SlaveSlot_1_programCmd CFGSMIF_SlaveSlot_1_readStsRegQeCmd CFGSMIF_SlaveSlot_1_readStsRegWipCmd CFGSMIF_SlaveSlot_1_writeStsRegQeCmd CFGSMIF_SlaveSlot_1_readSfdpCmd CFGSMIF_SlaveSlot_1_region0 CFGSMIF_SlaveSlot_1_region1 CFGSMIF_SlaveSlot_1_region2 CFGSMIF_SlaveSlot_1_region3 CFGSMIF_SlaveSlot_1_region4 CFGSMIF_SlaveSlot_1_region5 CFGSMIF_SlaveSlot_1_region6 CFGSMIF_SlaveSlot_1_region7 CFGSMIF_SlaveSlot_1_region8 CFGSMIF_SlaveSlot_1_region9 CFGSMIF_SlaveSlot_1_region10 CFGSMIF_SlaveSlot_1_region11 CFGSMIF_SlaveSlot_1_region12 CFGSMIF_SlaveSlot_1_region13 CFGSMIF_SlaveSlot_1_region14 CFGSMIF_SlaveSlot_1_region15 CFGSMIF_SlaveSlot_1_regionInfo CFGSMIF_deviceCfg_SlaveSlot_1 CFGSMIF_SlaveSlot_1 CFGSMIF_SlaveSlot_2_readCmd CFGSMIF_SlaveSlot_2_writeEnCmd CFGSMIF_SlaveSlot_2_writeDisCmd CFGSMIF_SlaveSlot_2_eraseCmd CFGSMIF_SlaveSlot_2_chipEraseCmd CFGSMIF_SlaveSlot_2_programCmd CFGSMIF_SlaveSlot_2_readStsRegQeCmd CFGSMIF_SlaveSlot_2_readStsRegWipCmd CFGSMIF_SlaveSlot_2_writeStsRegQeCmd CFGSMIF_SlaveSlot_2_readSfdpCmd CFGSMIF_SlaveSlot_2_region0 CFGSMIF_SlaveSlot_2_region1 CFGSMIF_SlaveSlot_2_region2 CFGSMIF_SlaveSlot_2_region3 CFGSMIF_SlaveSlot_2_region4 CFGSMIF_SlaveSlot_2_region5 CFGSMIF_SlaveSlot_2_region6 CFGSMIF_SlaveSlot_2_region7 CFGSMIF_SlaveSlot_2_region8 CFGSMIF_SlaveSlot_2_region9 CFGSMIF_SlaveSlot_2_region10 CFGSMIF_SlaveSlot_2_region11 CFGSMIF_SlaveSlot_2_region12 CFGSMIF_SlaveSlot_2_region13 CFGSMIF_SlaveSlot_2_region14 CFGSMIF_SlaveSlot_2_region15 CFGSMIF_SlaveSlot_2_regionInfo CFGSMIF_deviceCfg_SlaveSlot_2 CFGSMIF_SlaveSlot_2 CFGSMIF_SlaveSlot_3_readCmd CFGSMIF_SlaveSlot_3_writeEnCmd CFGSMIF_SlaveSlot_3_writeDisCmd CFGSMIF_SlaveSlot_3_eraseCmd CFGSMIF_SlaveSlot_3_chipEraseCmd CFGSMIF_SlaveSlot_3_programCmd CFGSMIF_SlaveSlot_3_readStsRegQeCmd CFGSMIF_SlaveSlot_3_readStsRegWipCmd CFGSMIF_SlaveSlot_3_writeStsRegQeCmd CFGSMIF_SlaveSlot_3_readSfdpCmd CFGSMIF_SlaveSlot_3_region0 CFGSMIF_SlaveSlot_3_region1 CFGSMIF_SlaveSlot_3_region2 CFGSMIF_SlaveSlot_3_region3 CFGSMIF_SlaveSlot_3_region4 CFGSMIF_SlaveSlot_3_region5 CFGSMIF_SlaveSlot_3_region6 CFGSMIF_SlaveSlot_3_region7 CFGSMIF_SlaveSlot_3_region8 CFGSMIF_SlaveSlot_3_region9 CFGSMIF_SlaveSlot_3_region10 CFGSMIF_SlaveSlot_3_region11 CFGSMIF_SlaveSlot_3_region12 CFGSMIF_SlaveSlot_3_region13 CFGSMIF_SlaveSlot_3_region14 CFGSMIF_SlaveSlot_3_region15 CFGSMIF_SlaveSlot_3_regionInfo CFGSMIF_deviceCfg_SlaveSlot_3 CFGSMIF_SlaveSlot_3 CFGSMIF_smifMemConfigs CFGSMIF_smifBlockConfig memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/algo\algo_smif.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv SMIF_State isSystemInitialized _Bool isSmifBlockInitialized isSmifStructLoaded cy_smif_state_t SMIF_context txBufferAddress unsigned char uint8_t txBufferSize unsigned int uint32_t txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy unsigned short uint16_t preCmdDataRate CY_SMIF_SDR CY_SMIF_DDR cy_en_smif_data_rate_t preCmdWidth CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA cy_en_smif_txfr_width_t preXIPDataRate cy_stc_smif_context_t isReleasedFromPowerDown CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES CY_SMIF_NORMAL CY_SMIF_MEMORY CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY CY_SMIF_SFDP_QER_0 CY_SMIF_SFDP_QER_1 CY_SMIF_SFDP_QER_2 CY_SMIF_SFDP_QER_3 CY_SMIF_SFDP_QER_4 CY_SMIF_SFDP_QER_5 CY_SMIF_SFDP_QER_6 CY_SMIF_STARTED CY_SMIF_SEND_COMPLETE CY_SMIF_SEND_BUSY CY_SMIF_RX_COMPLETE CY_SMIF_RX_BUSY CY_SMIF_XIP_ERROR CY_SMIF_CMD_ERROR CY_SMIF_TX_ERROR CY_SMIF_RX_ERROR slaveSelect cy_en_smif_slave_select_t flags dataSelect cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg numOfAddrBytes memSize readCmd command cmdWidth addrWidth mode modeWidth dummyCycles dataWidth dataRate dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t writeEnCmd writeDisCmd eraseCmd eraseSize chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask eraseTime chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 __ARRAY_SIZE_TYPE__ cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t CTL STATUS RESERVED INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DL_CTL RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 TX_CMD_FIFO_STATUS TX_CMD_MMIO_FIFO_STATUS RESERVED3 TX_CMD_MMIO_FIFO_WR RESERVED4 TX_DATA_MMIO_FIFO_CTL TX_DATA_FIFO_STATUS TX_DATA_MMIO_FIFO_STATUS RESERVED5 TX_DATA_MMIO_FIFO_WR1 TX_DATA_MMIO_FIFO_WR2 TX_DATA_MMIO_FIFO_WR4 TX_DATA_MMIO_FIFO_WR1ODD RESERVED6 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED7 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED8 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED9 SLOW_CA_CTL RESERVED10 SLOW_CA_CMD RESERVED11 FAST_CA_CTL RESERVED12 FAST_CA_CMD RESERVED13 SMIF_CRYPTO_BLOCK CRYPTO_CMD CRYPTO_ADDR CRYPTO_MASK CRYPTO_SUBREGION CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 SMIF_SMIF_CRYPTO_Type CRC_CMD RESERVED14 CRC_INPUT0 CRC_INPUT1 RESERVED15 CRC_OUTPUT RESERVED16 INTR INTR_SET INTR_MASK INTR_MASKED INTR_CAUSE RESERVED17 DEVICE ADDR MASK ADDR_CTL DELAY_TAP_SEL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type RESERVED18 MPC CFG INTR_INFO1 INTR_INFO2 CTRL BLK_MAX BLK_CFG BLK_IDX BLK_LUT ROT_CTRL ROT_CFG ROT_BLK_MAX ROT_BLK_CFG ROT_BLK_IDX ROT_BLK_PC ROT_BLK_LUT SMIF_MPC_Type SMIF_Type memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t int int32_t __disable_irq SMIF_SetCmdPtr dst_cmd src_cmd Cy_SMIF_Disable base Cy_SMIF_BusyCheck SMIF_InitSystem result_t SMIF_PrepareConfigs SMIF_TuneConfigs SMIF_FindMappedDevice SMIF_FindDualQuadPair SMIF_Init_XIP SMIF_Init SMIF_EnableQuad SMIF_SetMode SMIF_UnInit SMIF_PollBlockBusy SMIF_Read SMIF_EraseChip SMIF_Erase SMIF_Program SMIF_Verify SMIF_IsMemoryFilled SMIF_PollMemBusy SMIF_PollTransferStatus OUTLINED_FUNCTION_0 result address memIdx pMem maxSize dualChMask smifMode cy_en_smif_mode_t smifstat cy_en_smif_status_t readStatus maskQE statusCmd isQuadEnabled currentMode timeoutAttempts isBusy attemptsElapsed size buffer dualQuadMembers i isDualQuadPair blockSize memConfigDualQuadPair memAddress regionInfo addrAlign sectorsInRegion offsetInRegion sizeAlign pageSize addrEnd maxMemSize blockAddr offsetInBlock xipAddr memAbsAddr lastVerifiedAddr result1 value currAddr valueWord chunkEnd memConfigSecondDev isMem1Busy isMem2Busy cy_en_smif_txfr_status_t transferTimeout Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/algo\algo_base.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv Backup gpio_prt1_cfg out unsigned int uint32_t intrMask intrCfg cfg cfgIn cfgOut cfgSIO sel0Active sel1Active cfgSlew cfgDriveSel0 cfgDriveSel1 nonSecMask cy_stc_gpio_prt_config_t gpio_prt8_cfg gpio_prt11_cfg gpio_prt12_cfg clk_root2 cy_backup_t Loader_Backup int result_t Loader_Restore result Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/algo\algo_common.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv char Count unsigned char uint8_t NumToStr number unsigned int uint32_t base res num ptr digs Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/framework/cmsis\FlashPrg.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv CFGALGO_EraseChunkSize unsigned int uint32_t algo_extra_buffer unsigned char __ARRAY_SIZE_TYPE__ uint8_t SMIF_Init_XIP int result_t Loader_Restore SMIF_EraseChip SMIF_Erase SMIF_Program SMIF_IsMemoryFilled Init UnInit EraseChip EraseSector ProgramPage Verify unsigned long BlankCheck adr clk fnc result sz buf pat Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] ../src/framework/cmsis\FlashDev.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1b\prj_cmsis_uv FlashDevice Vers unsigned short DevName char __ARRAY_SIZE_TYPE__ DevType DevAdr unsigned long szDev szPage Res valEmpty unsigned char toProg toErase sectors szSector AddrSector FlashSectors
$t.0 $d.2 $t.3 $d.1 $t.2 $d.3 $t.4 $d.5 $t.6 $d.7 $t.8 $d.9 $t.10 $d.11 $t.12 $d.13 $t.14 $d.15 $t.16 $d.17 $t.18 $d.19 $t.20 $d.21 $t.22 $d.23 $t.24 $d.25 $t.26 $d.27 $t.28 $t $d.29 $t.30 $d.31 $t.32 $d.33 $t.34 $d.35 $t.36 $d.37 $t.38 $d.39 $t.40 $d.41 $t.42 $d.43 $t.44 $d.45 $t.46 $d.47 $t.48 $d.49 $t.50 $d.51 $t.52 $d.53 $t.54 $d.55 $t.56 $d.57 $t.58 $d.59 $t.60 $d.61 $t.62 $d.63 $t.64 $d.65 $t.66 $d.67 $t.68 $d.69 $t.70 $d.71 $t.72 $d.73 $t.74 $d.75 $t.76 $d.77 $t.78 $d.79 $t.80 $d.81 $t.82 $d.83 $t.84 $d.85 $t.86 $d.87 $t.88 $d.89 $t.90 $d.91 $t.92 $d.93 $t.94 $d.95 $t.96 $d.97 $t.98 $d.99 $t.100 $d.101 $t.102 $d.103 $t.104 $d.105 $t.106 $d.107 $t.108 $d.109 $t.110 $d.111 $t.112 $d.113 $t.114 $d.115 $t.116 $d.117 $t.118 $d.119 $t.120 $d.121 $t.122 $d.123 $t.124 $d.125 $t.126 $d.127 $t.128 $d.129 $t.130 $d.131 $t.132 $d.133 $t.134 $d.135 $t.136 $d.137 $t.138 $d.139 $t.140 $d.141 $t.142 $d.143 $t.144 $d.145 $t.146 $d.147 $t.148 $d.149 $t.150 $d.151 $t.152 $d.153 $t.154 $d.155 $t.156 $d.157 $t.158 $d.159 $t.160 $d.161 $t.162 $d.163 $t.164 $d.165 $t.166 $d.167 $t.168 $d.169 $t.170 $d.171 $t.172 $d.173 $t.174 $d.175 $t.176 $d.177 $t.178 $d.179 $t.180 $d.181 $t.182 $d.183 $t.184 $d.185 $t.186 $d.187 $t.188 $d.189 $t.190 $d.191 $t.192 $d.193 $t.194 $d.195 $t.196 $d.realdata FlashDev.c FlashPrg.c algo_common.c algo_base.c algo_smif.c OUTLINED_FUNCTION_0 SMIF_State.0 SMIF_State.1 SMIF_State.2 isReleasedFromPowerDown SMIF_context dbg_main.c dbg_main_cmsis.c cycfg_qspi_memslot_SFDP.c ..\src\pdl\drivers\source\TOOLCHAIN_ARM\cy_syslib_ext.s .text cy_smif.c Cy_SMIF_TimeoutRun Cy_SMIF_PackBytesArray OUTLINED_FUNCTION_1 OUTLINED_FUNCTION_2 OUTLINED_FUNCTION_3 OUTLINED_FUNCTION_4 cy_smif_memslot.c ValueToByteArray OUTLINED_FUNCTION_5 OUTLINED_FUNCTION_6 OUTLINED_FUNCTION_7 cy_smif_sfdp.c SfdpReadBuffer SfdpFindParameterTableAddress SfdpGetQuadEnableParameters SfdpGetSectorEraseCommand SfdpSetProgramCommand_1_1_1 SfdpSetProgramCommandFourBytes_1_1_4 SfdpSetProgramCommandFourBytes_1_1_1 cy_syslib.c .L_MergedGlobals cy_device.c cy_gpio.c cy_sysclk_v2.c cySysClkExtFreq clkCounting preventCounting clk1Count1 ns_system_cyw20829.c cy_pd_pdcm.c cy_efuse_v3.c cy_syspm_btss.c cy_btss_lock_count cy_cpuss_lock_count cycfg.c cycfg_peripherals.c cycfg_pins.c cycfg_system.c srss_0_clock_0_fll_0_fllConfig cycfg_clocks.c dc.s ../clib/longlong.s ../clib/string.c ../clib/memcpset.s ../clib/angel/rt.s ../clib/signal.c ../clib/angel/sysapp.c ../clib/angel/sys.s ../clib/signal.s BuildAttributes$$THM_ISAv4$P$D$K$B$S$8M$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$~IW$RWPI$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 Init UnInit EraseChip EraseSector ProgramPage Verify BlankCheck Count NumToStr Loader_Backup Loader_Restore SMIF_InitSystem SMIF_PrepareConfigs SMIF_SetCmdPtr SMIF_TuneConfigs SMIF_FindMappedDevice SMIF_FindDualQuadPair SMIF_Init_XIP SMIF_Init SMIF_EnableQuad SMIF_SetMode SMIF_UnInit SMIF_PollBlockBusy SMIF_Read SMIF_EraseChip SMIF_Erase SMIF_Program SMIF_Verify SMIF_IsMemoryFilled SMIF_PollMemBusy SMIF_PollTransferStatus Cy_SysLib_DelayCycles Cy_SysLib_EnterCriticalSection Cy_SysLib_ExitCriticalSection Cy_SMIF_Init Cy_SMIF_DeInit Cy_SMIF_SetMode Cy_SMIF_GetMode Cy_SMIF_SetDataSelect Cy_SMIF_TransmitCommand Cy_SMIF_TransmitCommand_Ext Cy_SMIF_TransmitData Cy_SMIF_TransmitData_Ext Cy_SMIF_TransmitDataBlocking Cy_SMIF_TransmitDataBlocking_Ext Cy_SMIF_ReceiveData Cy_SMIF_ReceiveData_Ext Cy_SMIF_ReceiveDataBlocking Cy_SMIF_ReceiveDataBlocking_Ext Cy_SMIF_SendDummyCycles Cy_SMIF_SendDummyCycles_Ext Cy_SMIF_GetTransferStatus Cy_SMIF_Enable Cy_SMIF_SetCryptoKey Cy_SMIF_SetCryptoIV Cy_SMIF_ConvertSlaveSlotToIndex Cy_SMIF_SetCryptoEnable Cy_SMIF_SetCryptoDisable Cy_SMIF_Encrypt Cy_SMIF_CacheEnable Cy_SMIF_CacheDisable Cy_SMIF_CachePrefetchingEnable Cy_SMIF_CachePrefetchingDisable Cy_SMIF_CacheInvalidate Cy_SMIF_DeepSleepCallback Cy_SMIF_HibernateCallback Cy_SMIF_MemInit Cy_SMIF_MemDeInit Cy_SMIF_MemCmdWriteEnable Cy_SMIF_MemCmdWriteDisable Cy_SMIF_MemIsBusy Cy_SMIF_MemCmdReadStatus Cy_SMIF_MemQuadEnable Cy_SMIF_MemCmdWriteStatus Cy_SMIF_MemOctalEnable Cy_SMIF_MemCmdChipErase Cy_SMIF_MemCmdSectorErase Cy_SMIF_MemLocateHybridRegion Cy_SMIF_MemCmdProgram Cy_SMIF_MemCmdRead Cy_SMIF_SetReadyPollingDelay Cy_SMIF_MemIsReady Cy_SMIF_MemIsQuadEnabled Cy_SMIF_MemEnableQuadMode Cy_SMIF_MemRead Cy_SMIF_MemWrite Cy_SMIF_MemEraseSector Cy_SMIF_MemEraseChip Cy_SMIF_MemCmdPowerDown Cy_SMIF_MemCmdReleasePowerDown Cy_SMIF_MemInitSfdpMode Cy_SMIF_MemSfdpDetect Cy_SysLib_Delay Cy_SysLib_DelayUs Cy_SysLib_Rtos_Delay Cy_SysLib_Rtos_DelayUs Cy_SysLib_Halt Cy_SysLib_AssertFailed Cy_SysLib_ResetBackupDomain Cy_SysLib_GetResetReason Cy_SysLib_ClearResetReason Cy_SysLib_GetUniqueId Cy_SysLib_FaultHandler Cy_SysLib_ProcessingFault Cy_SysLib_SetWaitStates Cy_SysLib_GetDeviceRevision Cy_SysLib_GetDevice Cy_Syslib_SetWarmBootEntryPoint Cy_PDL_Init Cy_GPIO_Pin_Init Cy_GPIO_SetSlewRate Cy_GPIO_SetDriveSel Cy_GPIO_SetHSIOM Cy_GPIO_SetDrivemode Cy_GPIO_SetInterruptEdge Cy_GPIO_SetInterruptMask Cy_GPIO_SetVtrip Cy_GPIO_Write Cy_GPIO_Port_Init Cy_GPIO_Pin_FastInit Cy_GPIO_Port_Deinit Cy_GPIO_SetAmuxSplit Cy_GPIO_GetAmuxSplit Cy_GPIO_GetHSIOM Cy_GPIO_Read Cy_GPIO_ReadOut Cy_GPIO_Set Cy_GPIO_Clr Cy_GPIO_Inv Cy_GPIO_GetDrivemode Cy_GPIO_GetVtrip Cy_GPIO_GetSlewRate Cy_GPIO_GetDriveSel Cy_GPIO_SetVregEn Cy_GPIO_GetVregEn Cy_GPIO_SetIbufMode Cy_GPIO_GetIbufMode Cy_GPIO_SetVtripSel Cy_GPIO_GetVtripSel Cy_GPIO_SetVrefSel Cy_GPIO_GetVrefSel Cy_GPIO_SetVohSel Cy_GPIO_GetVohSel Cy_GPIO_GetInterruptStatus Cy_GPIO_ClearInterrupt Cy_GPIO_GetInterruptMask Cy_GPIO_GetInterruptStatusMasked Cy_GPIO_SetSwInterrupt Cy_GPIO_GetInterruptEdge Cy_GPIO_SetFilter Cy_GPIO_GetFilter Cy_SysClk_PeriPclkSetDivider Cy_SysClk_PeriPclkGetDivider Cy_SysClk_PeriPclkSetFracDivider Cy_SysClk_PeriPclkGetFracDivider Cy_SysClk_PeriPclkAssignDivider Cy_SysClk_PeriPclkGetAssignedDivider Cy_SysClk_PeriPclkEnableDivider Cy_SysClk_PeriPclkDisableDivider Cy_SysClk_PeriPclkEnablePhaseAlignDivider Cy_SysClk_PeriphDisableDivider Cy_SysClk_PeriPclkGetDividerEnabled Cy_SysClk_PeriphSetDivider Cy_SysClk_PeriphGetDivider Cy_SysClk_PeriphSetFracDivider Cy_SysClk_PeriphGetFracDivider Cy_SysClk_PeriphAssignDivider Cy_SysClk_PeriphGetAssignedDivider Cy_SysClk_PeriphEnableDivider Cy_SysClk_PeriphEnablePhaseAlignDivider Cy_SysClk_PeriphGetDividerEnabled Cy_SysClk_ClkPumpSetSource Cy_SysClk_ClkPumpGetSource Cy_SysClk_ClkPumpSetDivider Cy_SysClk_ClkPumpGetDivider Cy_SysClk_ClkPumpIsEnabled Cy_SysClk_ClkPumpEnable Cy_SysClk_ClkPumpDisable Cy_SysClk_ClkPumpGetFrequency Cy_SysClk_ClkPathGetFrequency Cy_SysClk_ClkBakSetSource Cy_SysClk_ClkBakGetSource Cy_SysClk_ClkLfSetSource Cy_SysClk_ClkLfGetSource Cy_SysClk_PeriGroupSetDivider Cy_SysClk_PeriGroupGetDivider Cy_SysClk_PeriGroupSetSlaveCtl Cy_SysClk_PeriGroupGetSlaveCtl Cy_SysClk_IsPeriGroupSlaveCtlSet Cy_SysClk_ClkHfEnable Cy_SysClk_ClkHfGetFrequency Cy_SysClk_ClkHfIsEnabled Cy_SysClk_ClkHfDisable Cy_SysClk_ClkHfSetSource Cy_SysClk_ClkHfGetSource Cy_SysClk_ClkHfSetDivider Cy_SysClk_ClkHfGetDivider Cy_SysClk_IsClkHfDirectSelEnabled Cy_SysClk_ClkHfDirectSel Cy_SysClk_MfoEnable Cy_SysClk_MfoIsEnabled Cy_SysClk_MfoDisable Cy_SysClk_ClkMfEnable Cy_SysClk_ClkMfIsEnabled Cy_SysClk_ClkMfDisable Cy_SysClk_ClkMfSetDivider Cy_SysClk_ClkMfGetDivider Cy_SysClk_ClkMfGetFrequency Cy_SysClk_ClkMfSetSource Cy_SysClk_ClkMfGetSource Cy_SysClk_WcoEnable Cy_SysClk_WcoOkay Cy_SysClk_WcoDisable Cy_SysClk_WcoBypass Cy_SysClk_PiloEnable Cy_SysClk_PiloBackupEnable Cy_SysClk_PiloBackupDisable Cy_SysClk_PiloTcscEnable Cy_SysClk_PiloTcscDisable Cy_SysClk_PiloIsEnabled Cy_SysClk_PiloDisable Cy_SysClk_AltHfGetFrequency Cy_SysClk_AltHfEnable Cy_SysClk_IsAltHfEnabled Cy_SysClk_AltLfGetFrequency Cy_SysClk_AltLfIsEnabled Cy_SysClk_IloEnable Cy_SysClk_IloDisable Cy_SysClk_IloIsEnabled Cy_SysClk_IloHibernateOn Cy_SysClk_ExtClkSetFrequency Cy_SysClk_ExtClkGetFrequency Cy_SysClk_IhoIsEnabled Cy_SysClk_IhoDisable Cy_SysClk_IhoEnable Cy_SysClk_ClkPathSetSource Cy_SysClk_ClkPathGetSource Cy_SysClk_ClkPathMuxGetFrequency Cy_SysClk_FllGetConfiguration Cy_SysClk_FllIsEnabled Cy_SysClk_FllLocked Cy_SysClk_FllDisable Cy_SysClk_FllOutputDividerEnable Cy_SysClk_FllConfigure Cy_SysClk_FllManualConfigure Cy_SysClk_FllEnable Cy_SysClk_FllGetFrequency Cy_SysClk_ClkMeasurementCountersDone Cy_SysClk_StartClkMeasurementCounters Cy_SysClk_ClkMeasurementCountersGetFreq Cy_SysClk_PiloTrim Cy_SysClk_PiloInitialTrim Cy_SysClk_PiloUpdateTrimStep Cy_SysClk_PiloSetTrim Cy_SysClk_PiloGetTrim Cy_SysClk_IloTrim Cy_SysClk_IloGetTrim Cy_SysClk_IloSetTrim Cy_SysClk_DeepSleepCallback Cy_SysClk_PeriphGetFrequency Cy_SysClk_PeriPclkGetFrequency Cy_Sysclk_PeriPclkGetClkHfNum SystemInit Cy_SystemInit SystemCoreClockUpdate cy_pd_pdcm_get_dependency cy_pd_pdcm_set_dependency cy_pd_pdcm_clear_dependency Cy_EFUSE_Enable Cy_EFUSE_Disable Cy_EFUSE_IsEnabled Cy_EFUSE_Init Cy_EFUSE_DeInit Cy_EFUSE_WriteBit Cy_EFUSE_ReadByte Cy_EFUSE_WriteByte Cy_EFUSE_WriteWord Cy_EFUSE_ReadWord Cy_EFUSE_WriteWordArray Cy_EFUSE_ReadBit Cy_EFUSE_ReadWordArray Cy_EFUSE_WriteBootRow Cy_EFUSE_ReadBootRow Cy_BTSS_GetXtalOscFreq Cy_BTSS_PowerDep Cy_BTSS_CPUSSPowerDep init_cycfg_all cycfg_config_init cycfg_config_reservations reserve_cycfg_peripherals init_cycfg_pins reserve_cycfg_pins cycfg_ClockStartupError init_cycfg_system reserve_cycfg_system init_cycfg_clocks reserve_cycfg_clocks __aeabi_uldivmod _ll_udiv memcmp __aeabi_memcpy __rt_memcpy _memcpy_lastbytes __aeabi_memclr4 __aeabi_memclr8 __rt_memclr_w _memset_w strncpy __aeabi_memcpy4 __aeabi_memcpy8 __rt_memcpy_w _memcpy_lastbytes_aligned __aeabi_memclr __rt_memclr _memset SMIF_config cy_deviceIpBlockCfg ioss_0_port_2_pin_0_config ioss_0_port_2_pin_1_config ioss_0_port_2_pin_2_config ioss_0_port_2_pin_3_config ioss_0_port_2_pin_4_config ioss_0_port_2_pin_5_config cy_device Backup CFGALGO_EraseChunkSize CFGSMIF_SlaveSlot_0 CFGSMIF_SlaveSlot_0_chipEraseCmd CFGSMIF_SlaveSlot_0_eraseCmd CFGSMIF_SlaveSlot_0_programCmd CFGSMIF_SlaveSlot_0_readCmd CFGSMIF_SlaveSlot_0_readSfdpCmd CFGSMIF_SlaveSlot_0_readStsRegQeCmd CFGSMIF_SlaveSlot_0_readStsRegWipCmd CFGSMIF_SlaveSlot_0_region0 CFGSMIF_SlaveSlot_0_region1 CFGSMIF_SlaveSlot_0_region10 CFGSMIF_SlaveSlot_0_region11 CFGSMIF_SlaveSlot_0_region12 CFGSMIF_SlaveSlot_0_region13 CFGSMIF_SlaveSlot_0_region14 CFGSMIF_SlaveSlot_0_region15 CFGSMIF_SlaveSlot_0_region2 CFGSMIF_SlaveSlot_0_region3 CFGSMIF_SlaveSlot_0_region4 CFGSMIF_SlaveSlot_0_region5 CFGSMIF_SlaveSlot_0_region6 CFGSMIF_SlaveSlot_0_region7 CFGSMIF_SlaveSlot_0_region8 CFGSMIF_SlaveSlot_0_region9 CFGSMIF_SlaveSlot_0_regionInfo CFGSMIF_SlaveSlot_0_writeDisCmd CFGSMIF_SlaveSlot_0_writeEnCmd CFGSMIF_SlaveSlot_0_writeStsRegQeCmd CFGSMIF_SlaveSlot_1 CFGSMIF_SlaveSlot_1_chipEraseCmd CFGSMIF_SlaveSlot_1_eraseCmd CFGSMIF_SlaveSlot_1_programCmd CFGSMIF_SlaveSlot_1_readCmd CFGSMIF_SlaveSlot_1_readSfdpCmd CFGSMIF_SlaveSlot_1_readStsRegQeCmd CFGSMIF_SlaveSlot_1_readStsRegWipCmd CFGSMIF_SlaveSlot_1_region0 CFGSMIF_SlaveSlot_1_region1 CFGSMIF_SlaveSlot_1_region10 CFGSMIF_SlaveSlot_1_region11 CFGSMIF_SlaveSlot_1_region12 CFGSMIF_SlaveSlot_1_region13 CFGSMIF_SlaveSlot_1_region14 CFGSMIF_SlaveSlot_1_region15 CFGSMIF_SlaveSlot_1_region2 CFGSMIF_SlaveSlot_1_region3 CFGSMIF_SlaveSlot_1_region4 CFGSMIF_SlaveSlot_1_region5 CFGSMIF_SlaveSlot_1_region6 CFGSMIF_SlaveSlot_1_region7 CFGSMIF_SlaveSlot_1_region8 CFGSMIF_SlaveSlot_1_region9 CFGSMIF_SlaveSlot_1_regionInfo CFGSMIF_SlaveSlot_1_writeDisCmd CFGSMIF_SlaveSlot_1_writeEnCmd CFGSMIF_SlaveSlot_1_writeStsRegQeCmd CFGSMIF_SlaveSlot_2 CFGSMIF_SlaveSlot_2_chipEraseCmd CFGSMIF_SlaveSlot_2_eraseCmd CFGSMIF_SlaveSlot_2_programCmd CFGSMIF_SlaveSlot_2_readCmd CFGSMIF_SlaveSlot_2_readSfdpCmd CFGSMIF_SlaveSlot_2_readStsRegQeCmd CFGSMIF_SlaveSlot_2_readStsRegWipCmd CFGSMIF_SlaveSlot_2_region0 CFGSMIF_SlaveSlot_2_region1 CFGSMIF_SlaveSlot_2_region10 CFGSMIF_SlaveSlot_2_region11 CFGSMIF_SlaveSlot_2_region12 CFGSMIF_SlaveSlot_2_region13 CFGSMIF_SlaveSlot_2_region14 CFGSMIF_SlaveSlot_2_region15 CFGSMIF_SlaveSlot_2_region2 CFGSMIF_SlaveSlot_2_region3 CFGSMIF_SlaveSlot_2_region4 CFGSMIF_SlaveSlot_2_region5 CFGSMIF_SlaveSlot_2_region6 CFGSMIF_SlaveSlot_2_region7 CFGSMIF_SlaveSlot_2_region8 CFGSMIF_SlaveSlot_2_region9 CFGSMIF_SlaveSlot_2_regionInfo CFGSMIF_SlaveSlot_2_writeDisCmd CFGSMIF_SlaveSlot_2_writeEnCmd CFGSMIF_SlaveSlot_2_writeStsRegQeCmd CFGSMIF_SlaveSlot_3 CFGSMIF_SlaveSlot_3_chipEraseCmd CFGSMIF_SlaveSlot_3_eraseCmd CFGSMIF_SlaveSlot_3_programCmd CFGSMIF_SlaveSlot_3_readCmd CFGSMIF_SlaveSlot_3_readSfdpCmd CFGSMIF_SlaveSlot_3_readStsRegQeCmd CFGSMIF_SlaveSlot_3_readStsRegWipCmd CFGSMIF_SlaveSlot_3_region0 CFGSMIF_SlaveSlot_3_region1 CFGSMIF_SlaveSlot_3_region10 CFGSMIF_SlaveSlot_3_region11 CFGSMIF_SlaveSlot_3_region12 CFGSMIF_SlaveSlot_3_region13 CFGSMIF_SlaveSlot_3_region14 CFGSMIF_SlaveSlot_3_region15 CFGSMIF_SlaveSlot_3_region2 CFGSMIF_SlaveSlot_3_region3 CFGSMIF_SlaveSlot_3_region4 CFGSMIF_SlaveSlot_3_region5 CFGSMIF_SlaveSlot_3_region6 CFGSMIF_SlaveSlot_3_region7 CFGSMIF_SlaveSlot_3_region8 CFGSMIF_SlaveSlot_3_region9 CFGSMIF_SlaveSlot_3_regionInfo CFGSMIF_SlaveSlot_3_writeDisCmd CFGSMIF_SlaveSlot_3_writeEnCmd CFGSMIF_SlaveSlot_3_writeStsRegQeCmd CFGSMIF_deviceCfg_SlaveSlot_0 CFGSMIF_deviceCfg_SlaveSlot_1 CFGSMIF_deviceCfg_SlaveSlot_2 CFGSMIF_deviceCfg_SlaveSlot_3 CFGSMIF_smifBlockConfig CFGSMIF_smifMemConfigs SystemCoreClock cy_Hfclk0FreqHz cy_PeriClkFreqHz cy_delay32kMs cy_delayFreqHz cy_delayFreqKhz cy_delayFreqMhz cy_faultFrame cy_assertLine cy_assertFileName algo_extra_buffer FlashDevice
Component: Arm Compiler for Embedded 6.18 Tool: armlink [5e4cc100] ArmLink --strict --load_addr_map_info --map --symbols --diag_suppress=9931,L6305,L9529,L9931 --cpu=Cortex-M33.no_dsp --fpu=SoftVFP --list=..\output\objects\cmsis\CYW208xx_SMIF\CYW208xx_SMIF.map --output=..\output\objects\cmsis\CYW208xx_SMIF\CYW208xx_SMIF.axf --scatter=..\src\framework\cmsis\link_uv_CYW208xx.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\c_we.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\fz_ws.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\h_we.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcpp-experimental_we.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcpp_we.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcppabi_we.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\m_ws.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\vfpsupport.l Input Comments: flashdev.o flashprg.o algo_common.o algo_base.o algo_smif.o dbg_main.o dbg_main_cmsis.o cycfg_qspi_memslot_sfdp.o cy_smif.o cy_smif_memslot.o cy_smif_sfdp.o cy_syslib.o cy_device.o cy_gpio.o cy_sysclk_v2.o ns_system_cyw20829.o cy_pd_pdcm.o cy_efuse_v3.o cy_syspm_btss.o cycfg.o cycfg_peripherals.o cycfg_pins.o cycfg_system.o cycfg_clocks.o Component: Arm Compiler for Embedded 6.18 Tool: armclang [5e4cca00] cy_syslib_ext.o Component: Arm Compiler for Embedded 6.18 Tool: armasm [5e4cbe00] ArmAsm --debug --diag_suppress=9931,A9931 --cpu=Cortex-M33.no_dsp --fpu=SoftVFP --apcs=/ropi//rwpi --depend=..\output\objects\cmsis\cyw208xx_smif\cy_syslib_ext.d -IC:\Keil_v5\ARM\Packs\ARM\CMSIS\5.9.0\Devic
PrgCode PrgData DevDscr .debug_abbrev .debug_frame .debug_info .debug_line .debug_loc .debug_str .debug_ranges .symtab .strtab .note .comment .shstrtab