1 /***************************************************************************//**
2 * \file cybsp.c
3 *
4 * Description:
5 * Provides initialization code for starting up the hardware contained on the
6 * Infineon board.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 #include <stdlib.h>
29 #include "cy_syspm.h"
30 #include "cy_sysclk.h"
31 #include "cybsp.h"
32 #if defined(CY_USING_HAL)
33 #include "cyhal_hwmgr.h"
34 #include "cyhal_syspm.h"
35 #endif
36 #if defined(COMPONENT_MW_CAT1CM0P)
37 #include "mtb_cat1cm0p.h"
38 #endif
39
40 #if defined(__cplusplus)
41 extern "C" {
42 #endif
43
44 // The sysclk deep sleep callback is recommended to be the last callback that is executed before
45 // entry into deep sleep mode and the first one upon exit the deep sleep mode.
46 // Doing so minimizes the time spent on low power mode entry and exit.
47 #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
48 #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
49 #endif
50
51 #if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
52 //--------------------------------------------------------------------------------------------------
53 // cybsp_register_sysclk_pm_callback
54 //
55 // Registers a power management callback that prepares the clock system for entering deep sleep mode
56 // and restore the clocks upon wakeup from deep sleep.
57 // NOTE: This is called automatically as part of \ref cybsp_init
58 //--------------------------------------------------------------------------------------------------
cybsp_register_sysclk_pm_callback(void)59 static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
60 {
61 cy_rslt_t result = CY_RSLT_SUCCESS;
62 static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
63 static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
64 {
65 .callback = &Cy_SysClk_DeepSleepCallback,
66 .type = CY_SYSPM_DEEPSLEEP,
67 .callbackParams = &cybsp_sysclk_pm_callback_param,
68 .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
69 };
70
71 if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
72 {
73 result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
74 }
75 return result;
76 }
77
78
79 #endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
80
81
82 //--------------------------------------------------------------------------------------------------
83 // cybsp_init
84 //--------------------------------------------------------------------------------------------------
cybsp_init(void)85 cy_rslt_t cybsp_init(void)
86 {
87 // Setup hardware manager to track resource usage then initialize all system (clock/power) board
88 // configuration
89 #if defined(CY_USING_HAL)
90 cy_rslt_t result = cyhal_hwmgr_init();
91
92 if (CY_RSLT_SUCCESS == result)
93 {
94 result = cyhal_syspm_init();
95 }
96
97 #ifdef CY_CFG_PWR_VDDA_MV
98 if (CY_RSLT_SUCCESS == result)
99 {
100 cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
101 }
102 #endif
103
104 #else // if defined(CY_USING_HAL)
105 cy_rslt_t result = CY_RSLT_SUCCESS;
106 #endif // if defined(CY_USING_HAL)
107
108 // By default, the peripheral configuration will be done on the first core running user code.
109 // This is the CM0+ if it is available and not running a pre-built image, and the CM7 otherwise.
110 // This is done to ensure configuration is available for all cores that might need to use it.
111 // In the case of a dual core project, this can be changed below to perform initialization on
112 // the CM7 if necessary.
113 #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM7_0) && \
114 defined(CY_USING_PREBUILT_CM0P_IMAGE))
115 cycfg_config_init();
116 #endif
117
118 cycfg_config_reservations();
119
120 if (CY_RSLT_SUCCESS == result)
121 {
122 #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
123 result = cybsp_register_custom_sysclk_pm_callback();
124 #else
125 result = cybsp_register_sysclk_pm_callback();
126 #endif
127 }
128
129 // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
130 // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
131 // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
132 return result;
133 }
134
135
136 #if defined(__cplusplus)
137 }
138 #endif
139
