1 /***************************************************************************//**
2 * \file cybsp.c
3 *
4 * Description:
5 * Provides initialization code for starting up the hardware contained on the
6 * Infineon board.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 #include <stdlib.h>
29 #include "cy_syspm.h"
30 #include "cy_sysclk.h"
31 #include "cybsp.h"
32 #if defined(CY_USING_HAL)
33 #include "cyhal_hwmgr.h"
34 #include "cyhal_syspm.h"
35
36 #if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
37 #include "SDIO_HOST.h"
38 #endif
39 #endif // defined(CY_USING_HAL)
40
41 #if defined(COMPONENT_MW_CAT1CM0P)
42 #include "mtb_cat1cm0p.h"
43 #endif
44
45 #if defined(__cplusplus)
46 extern "C" {
47 #endif
48
49 // The sysclk deep sleep callback is recommended to be the last callback that is executed before
50 // entry into deep sleep mode and the first one upon exit the deep sleep mode.
51 // Doing so minimizes the time spent on low power mode entry and exit.
52 #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
53 #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
54 #endif
55
56 #if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
57 //--------------------------------------------------------------------------------------------------
58 // cybsp_register_sysclk_pm_callback
59 //
60 // Registers a power management callback that prepares the clock system for entering deep sleep mode
61 // and restore the clocks upon wakeup from deep sleep.
62 // NOTE: This is called automatically as part of \ref cybsp_init
63 //--------------------------------------------------------------------------------------------------
cybsp_register_sysclk_pm_callback(void)64 static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
65 {
66 cy_rslt_t result = CY_RSLT_SUCCESS;
67 static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
68 static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
69 {
70 .callback = &Cy_SysClk_DeepSleepCallback,
71 .type = CY_SYSPM_DEEPSLEEP,
72 .callbackParams = &cybsp_sysclk_pm_callback_param,
73 .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
74 };
75
76 if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
77 {
78 result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
79 }
80 return result;
81 }
82
83
84 #endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
85
86
87 //--------------------------------------------------------------------------------------------------
88 // cybsp_init
89 //--------------------------------------------------------------------------------------------------
cybsp_init(void)90 cy_rslt_t cybsp_init(void)
91 {
92 // Setup hardware manager to track resource usage then initialize all system (clock/power) board
93 // configuration
94 #if defined(CY_USING_HAL)
95 cy_rslt_t result = cyhal_hwmgr_init();
96
97 if (CY_RSLT_SUCCESS == result)
98 {
99 result = cyhal_syspm_init();
100 }
101
102 #ifdef CY_CFG_PWR_VDDA_MV
103 if (CY_RSLT_SUCCESS == result)
104 {
105 cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
106 }
107 #endif
108
109 #else // if defined(CY_USING_HAL)
110 cy_rslt_t result = CY_RSLT_SUCCESS;
111 #endif // if defined(CY_USING_HAL)
112
113 // By default, the peripheral configuration will be done on the first core running user code.
114 // This is the CM0+ if it is available and not running a pre-built image, and the CM4 otherwise.
115 // This is done to ensure configuration is available for all cores that might need to use it.
116 // In the case of a dual core project, this can be changed below to perform initialization on
117 // the CM4 if necessary.
118 #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
119 defined(CY_USING_PREBUILT_CM0P_IMAGE))
120 cycfg_config_init();
121 #endif
122
123 // Do any additional configuration reservations that are needed on all cores.
124 cycfg_config_reservations();
125
126 if (CY_RSLT_SUCCESS == result)
127 {
128 #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
129 result = cybsp_register_custom_sysclk_pm_callback();
130 #else
131 result = cybsp_register_sysclk_pm_callback();
132 #endif
133 }
134
135 #if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
136
137 // Reserve resources for the UDB SDIO interface that might want to be used by others. This
138 // includes specific clock and DMA instances. This must be done before other HAL API calls as
139 // specific peripheral instances are needed
140 // NOTE: The full SDIO/WiFi interface still needs to be initialized via
141 // cybsp_wifi_init_primary(). This is typically done when starting up WiFi.
142 if (CY_RSLT_SUCCESS == result)
143 {
144 result = SDIO_ReserveResources();
145 }
146 #endif // defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
147
148 // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
149 // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
150 // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
151 return result;
152 }
153
154
155 #if defined(__cplusplus)
156 }
157 #endif
158
