1 /***************************************************************************//**
2 * \file cy_wdt.c
3 * \version 1.80
4 *
5 * This file provides the source code to the API for the WDT driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXS28SRSS)|| defined (CY_IP_MXS40SSRSS ) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) || defined (CY_IP_MXS22SRSS )
29
30 #include "cy_wdt.h"
31
32 #if defined(__cplusplus)
33 extern "C" {
34 #endif
35
36
37
38 /*******************************************************************************
39 * Function Name: Cy_WDT_Init
40 ****************************************************************************//**
41 *
42 * Initializes the Watchdog timer to its default state.
43 *
44 * The given default setting of the WDT:
45 * The WDT is unlocked and disabled.
46 * The WDT match value is 4096.
47 * None of ignore bits are set: the whole WDT counter bits are checked against
48 * the match value.
49 *
50 * \sideeffect
51 * This function clears the WDT interrupt.
52 *
53 *******************************************************************************/
Cy_WDT_Init(void)54 void Cy_WDT_Init(void)
55 {
56 /* Unlock the WDT by two writes */
57 SRSS_WDT_CTL = ((SRSS_WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
58 SRSS_WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
59
60 Cy_WDT_Disable();
61 Cy_WDT_SetMatch(CY_SRSS_WDT_DEFAULT_MATCH_VALUE);
62 Cy_WDT_SetIgnoreBits(CY_SRSS_WDT_DEFAULT_IGNORE_BITS);
63 Cy_WDT_ClearInterrupt();
64 }
65
66
67 /*******************************************************************************
68 * Function Name: Cy_WDT_Lock
69 ****************************************************************************//**
70 *
71 * Locks out configuration changes to the Watchdog Timer register.
72 *
73 * After this function is called, the WDT configuration cannot be changed until
74 * Cy_WDT_Unlock() is called.
75 *
76 * \warning
77 * The WDT lock state is not retained during system Deep Sleep. After the wakeup
78 * from system Deep Sleep the WDT is locked.
79 *
80 *******************************************************************************/
Cy_WDT_Lock(void)81 void Cy_WDT_Lock(void)
82 {
83 SRSS_WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_LOCK, CY_SRSS_WDT_LOCK_BITS);
84 }
85
86
87 /*******************************************************************************
88 * Function Name: Cy_WDT_Locked
89 ****************************************************************************//**
90 *
91 * Returns the WDT lock state.
92 *
93 * \return
94 * True - if WDT is locked.
95 * False - if WDT is unlocked.
96 *
97 *******************************************************************************/
Cy_WDT_Locked(void)98 bool Cy_WDT_Locked(void)
99 {
100 /* Prohibits writing to the WDT registers and other CLK_LF */
101 return (0u != _FLD2VAL(SRSS_WDT_CTL_WDT_LOCK, SRSS_WDT_CTL));
102 }
103
104
105 /*******************************************************************************
106 * Function Name: Cy_WDT_Unlock
107 ****************************************************************************//**
108 *
109 * Unlocks the Watchdog Timer configuration register.
110 *
111 * \warning
112 * The WDT lock state is not retained during system Deep Sleep. After the wakeup
113 * from system Deep Sleep the WDT is locked.
114 *
115 *******************************************************************************/
Cy_WDT_Unlock(void)116 void Cy_WDT_Unlock(void)
117 {
118 /* The WDT lock is to be removed by two writes */
119 SRSS_WDT_CTL = ((SRSS_WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
120
121 SRSS_WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
122 }
123
124
125 /*******************************************************************************
126 * Function Name: Cy_WDT_SetMatch
127 ****************************************************************************//**
128 *
129 * Configures the WDT counter match comparison value. The Watchdog timer
130 * should be unlocked before changing the match value. Call the Cy_WDT_Unlock()
131 * function to unlock the WDT.
132 *
133 * \param match
134 * The valid valid range is [0-65535]. The value to be used to match
135 * against the counter.
136 *
137 *******************************************************************************/
Cy_WDT_SetMatch(uint32_t match)138 void Cy_WDT_SetMatch(uint32_t match)
139 {
140 CY_ASSERT_L2(CY_WDT_IS_MATCH_VAL_VALID(match));
141
142 if (false == Cy_WDT_Locked())
143 {
144 SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_MATCH, match);
145 }
146 }
147
148 /*******************************************************************************
149 * Function Name: Cy_WDT_SetIgnoreBits
150 ****************************************************************************//**
151 *
152 * Configures the number of the most significant bits of the Watchdog timer that
153 * are not checked against the match. Unlock the Watchdog timer before
154 * ignoring the bits setting. Call the Cy_WDT_Unlock() API to unlock the WDT.
155 *
156 * \param bitsNum
157 * The valid range is [0-15] for CAT1A devices, The bitsNum over 12 are considered as 12.
158 * The valid range is [0-21] for CAT1B/CAT1D devices, The bitsNum over 18 are
159 * considered as 18.
160 *
161 * \details The value of bitsNum controls the time-to-reset of the Watchdog timer
162 * This happens after 3 successive matches.
163 *
164 * \warning This function changes the WDT interrupt period, therefore
165 * the device can go into an infinite WDT reset loop. This may happen
166 * if a WDT reset occurs faster that a device start-up.
167 *
168 *******************************************************************************/
Cy_WDT_SetIgnoreBits(uint32_t bitsNum)169 void Cy_WDT_SetIgnoreBits(uint32_t bitsNum)
170 {
171 CY_ASSERT_L1(CY_WDT_IS_IGNORE_BITS_VALID(bitsNum));
172 (void)bitsNum;
173
174 if (false == Cy_WDT_Locked())
175 {
176 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
177 SRSS_WDT_MATCH2 = _CLR_SET_FLD32U((SRSS_WDT_MATCH2), SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, (WDT_MAX_IGNORE_BITS - bitsNum));
178 #else
179 SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_IGNORE_BITS, bitsNum);
180 #endif
181 }
182 }
183
184
185 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
186
187 /*******************************************************************************
188 * Function Name: Cy_WDT_SetMatchBits
189 ****************************************************************************//**
190 *
191 * Configures the bit position above which the bits will be ignored for match.
192 *
193 * \param bitPos
194 * The bit position above which the match should be ignored.
195 *
196 * \details The value of bitPos controls the time-to-reset of the Watchdog timer
197 * This happens after 3 successive matches.
198 *
199 * \warning This function changes the WDT interrupt period, therefore
200 * the device can go into an infinite WDT reset loop. This may happen
201 * if a WDT reset occurs faster that a device start-up.
202 *
203 * \note
204 * This API is available for CAT1B devices.
205 *
206 *******************************************************************************/
Cy_WDT_SetMatchBits(uint32_t bitPos)207 void Cy_WDT_SetMatchBits(uint32_t bitPos)
208 {
209 CY_ASSERT_L2(CY_WDT_IS_IGNORE_BITS_ABOVE_VALID(bitPos));
210 (void)bitPos;
211
212 if (false == Cy_WDT_Locked())
213 {
214 SRSS_WDT_MATCH2 = _CLR_SET_FLD32U((SRSS_WDT_MATCH2), SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, bitPos);
215 }
216 }
217 #endif
218
219 /*******************************************************************************
220 * Function Name: Cy_WDT_ClearInterrupt
221 ****************************************************************************//**
222 *
223 * Clears the WDT match flag which is set every time the WDT counter reaches a
224 * WDT match value. Two unserviced interrupts lead to a system reset
225 * (i.e. at the third match).
226 *
227 *******************************************************************************/
Cy_WDT_ClearInterrupt(void)228 void Cy_WDT_ClearInterrupt(void)
229 {
230 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
231 CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR, _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U));
232 #else
233 SRSS_SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U);
234 #endif
235
236 /* Read the interrupt register to ensure that the initial clearing write has
237 * been flushed out to the hardware.
238 */
239 (void) SRSS_SRSS_INTR;
240 }
241
242
243 /*******************************************************************************
244 * Function Name: Cy_WDT_ClearWatchdog
245 ****************************************************************************//**
246 *
247 * Clears ("feeds") the watchdog, to prevent a XRES device reset.
248 * This function simply call Cy_WDT_ClearInterrupt() function.
249 *
250 *******************************************************************************/
Cy_WDT_ClearWatchdog(void)251 void Cy_WDT_ClearWatchdog(void)
252 {
253 Cy_WDT_ClearInterrupt();
254 }
255
256 #if defined(__cplusplus)
257 }
258 #endif
259
260 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SRSS */
261
262 /* [] END OF FILE */
263
